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Commit 7703dea

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Minor refactoring.
Signed-off-by: Jaehyun Kim <[email protected]>
1 parent bb482de commit 7703dea

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5 files changed

+20
-42
lines changed

5 files changed

+20
-42
lines changed

src/dbSta/src/dbEditHierarchy.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -562,7 +562,7 @@ void dbEditHierarchy::hierarchicalConnect(dbITerm* source_pin,
562562
db_network_->reassociatePinConnection(sta_source_pin);
563563
db_network_->reassociatePinConnection(sta_dest_pin);
564564

565-
// 3.8. Rename flat net name if needed
565+
// 3.7. Rename flat net name if needed
566566
new_flat_net->renameWithModNetInHighestHier();
567567

568568
// 3.8. During the addition of new ports and new wiring we may

src/dbSta/src/dbNetwork.cc

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4605,18 +4605,22 @@ void dbNetwork::checkSanityNetNames() const
46054605
break;
46064606
}
46074607
}
4608-
if (name_match == false) {
4608+
4609+
if (name_match) {
4610+
continue;
4611+
}
4612+
4613+
// Found name mismatch b/w flat net and hierarchical nets
4614+
logger_->warn(ORD,
4615+
2050,
4616+
"SanityCheck: Flat net name '{}' does not match any of "
4617+
"its hierarchical net names.",
4618+
net->getName());
4619+
for (odb::dbModNet* mod_net : mod_nets) {
46094620
logger_->warn(ORD,
4610-
2050,
4611-
"SanityCheck: Flat net name '{}' does not match any of "
4612-
"its hierarchical net names.",
4613-
net->getName());
4614-
for (odb::dbModNet* mod_net : mod_nets) {
4615-
logger_->warn(ORD,
4616-
2055,
4617-
" hierarchical net: {}",
4618-
mod_net->getHierarchicalName());
4619-
}
4621+
2055,
4622+
" hierarchical net: {}",
4623+
mod_net->getHierarchicalName());
46204624
}
46214625
}
46224626
}

src/odb/include/odb/db.h

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2475,12 +2475,7 @@ class dbNet : public dbObject
24752475
///
24762476
/// Find the modnet in the highest hierarchy related to this net.
24772477
///
2478-
dbModNet* findHighestModNet() const;
2479-
2480-
///
2481-
/// Find the modnet on the driver iterm of this net.
2482-
///
2483-
dbModNet* findModNetOfDriver() const;
2478+
dbModNet* findModNetInHighestHier() const;
24842479

24852480
///
24862481
/// Rename this net with the name of the modnet in the highest hierarchy

src/odb/src/db/dbNet.cpp

Lines changed: 2 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -2413,7 +2413,7 @@ bool dbNet::isDeeperThan(const dbNet* net) const
24132413
return (other_depth < this_depth);
24142414
}
24152415

2416-
dbModNet* dbNet::findHighestModNet() const
2416+
dbModNet* dbNet::findModNetInHighestHier() const
24172417
{
24182418
std::set<dbModNet*> modnets;
24192419
if (findRelatedModNets(modnets) == false) {
@@ -2436,28 +2436,9 @@ dbModNet* dbNet::findHighestModNet() const
24362436
return highest;
24372437
}
24382438

2439-
dbModNet* dbNet::findModNetOfDriver() const
2440-
{
2441-
for (dbITerm* iterm : getITerms()) {
2442-
if (iterm->getIoType() == dbIoType::OUTPUT
2443-
|| iterm->getIoType() == dbIoType::INOUT) {
2444-
return iterm->getModNet();
2445-
}
2446-
}
2447-
2448-
for (dbBTerm* bterm : getBTerms()) {
2449-
if (bterm->getIoType() == dbIoType::INPUT
2450-
|| bterm->getIoType() == dbIoType::INOUT) {
2451-
return bterm->getModNet();
2452-
}
2453-
}
2454-
2455-
return nullptr;
2456-
}
2457-
24582439
void dbNet::renameWithModNetInHighestHier()
24592440
{
2460-
dbModNet* highest_mod_net = findHighestModNet();
2441+
dbModNet* highest_mod_net = findModNetInHighestHier();
24612442
if (highest_mod_net) {
24622443
rename(highest_mod_net->getHierarchicalName().c_str());
24632444
}

src/rcx/test/net_name_consistency.tcl

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,4 @@
1-
# Tests the handling of hierarchical and escaped names in read/write spef
2-
# This test starts with read_verilog to make sure that the names generated
3-
# in odb are what are generated during verilog parsing and not from DEF.
1+
# Tests a net name consistency b/w Verilog and SPEF.
42
source helpers.tcl
53
source Nangate45/Nangate45.vars
64

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