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braydenlouiebraydenlouie
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ram: fixed clang-tidy comments, added ram header file to src
Signed-off-by: braydenl9988 <braydenl9988@gmail.com>
1 parent 97493df commit 7b12927

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5 files changed

+33
-36
lines changed

5 files changed

+33
-36
lines changed

‎src/OpenRoad.cc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@
4141
#include "exa/example.h"
4242
#include "fin/Finale.h"
4343
#include "fin/MakeFinale.h"
44+
#include "ram/ram.h"
4445
#include "ram/MakeRam.h"
4546
#include "gpl/MakeReplace.h"
4647
#include "gpl/Replace.h"

‎src/ram/include/ram/ram.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -36,9 +36,9 @@ class RamGen
3636
RamGen(sta::dbNetwork* network, odb::dbDatabase* db, Logger* logger);
3737
~RamGen();
3838

39-
void generate(const int bytes_per_word,
40-
const int word_count,
41-
const int read_ports,
39+
void generate(int bytes_per_word,
40+
int word_count,
41+
int read_ports,
4242
odb::dbMaster* storage_cell,
4343
odb::dbMaster* tristate_cell,
4444
odb::dbMaster* inv_cell);
@@ -61,16 +61,16 @@ class RamGen
6161
odb::dbMaster* master,
6262
const std::vector<std::pair<std::string, odb::dbNet*>>& connections);
6363
std::unique_ptr<Cell> makeCellBit(const std::string& prefix,
64-
const int read_ports,
64+
int read_ports,
6565
odb::dbNet* clock,
6666
std::vector<odb::dbNet*>& select,
6767
odb::dbNet* data_input,
6868
std::vector<odb::dbNet*>& data_output);
6969
void makeCellByte(
7070
Grid& ram_grid,
71-
const int byte_number,
71+
int byte_number,
7272
const std::string& prefix,
73-
const int read_ports,
73+
int read_ports,
7474
odb::dbNet* clock,
7575
odb::dbNet* write_enable,
7676
const std::vector<odb::dbNet*>& selects,
@@ -80,13 +80,13 @@ class RamGen
8080
odb::dbBTerm* makeBTerm(const std::string& name, odb::dbIoType io_type);
8181

8282
std::unique_ptr<Cell> makeDecoder(const std::string& prefix,
83-
const int num_word,
84-
const int read_ports,
83+
int num_word,
84+
int read_ports,
8585
const std::vector<odb::dbNet*>& selects,
86-
const std::vector<odb::dbNet*>& ram_inputs);
86+
const std::vector<odb::dbNet*>& addr_nets);
8787

8888
std::vector<odb::dbNet*> selectNets(const std::string& prefix,
89-
const int read_ports);
89+
int read_ports);
9090

9191
sta::dbNetwork* network_;
9292
odb::dbDatabase* db_;

‎src/ram/src/layout.cpp‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,11 @@
88

99
namespace ram {
1010

11-
using odb::dbBTerm;
1211
using odb::dbInst;
13-
using odb::dbNet;
1412
using odb::dbOrientType;
1513
using odb::Point;
1614
using odb::Rect;
1715

18-
using utl::RAM;
19-
2016
//////////////////////////////////////////////////////////////
2117

2218
Cell::Cell() : origin_(0, 0), orient_(dbOrientType::R0)
@@ -64,12 +60,12 @@ void Cell::setOrigin(Point position)
6460
origin_ = position;
6561
}
6662

67-
const int Cell::getHeight()
63+
int Cell::getHeight()
6864
{
6965
return height;
7066
}
7167

72-
const int Cell::getWidth()
68+
int Cell::getWidth()
7369
{
7470
return width;
7571
}
@@ -131,12 +127,12 @@ void Layout::setOrigin(odb::Point position)
131127
origin_ = position;
132128
}
133129

134-
const int Layout::getHeight()
130+
int Layout::getHeight()
135131
{
136132
return cell_height;
137133
}
138134

139-
const int Layout::getWidth()
135+
int Layout::getWidth()
140136
{
141137
return cell_width;
142138
}
@@ -210,22 +206,22 @@ void Grid::setOrigin(odb::Point position)
210206
origin_ = position;
211207
}
212208

213-
const int Grid::getHeight()
209+
int Grid::getHeight()
214210
{
215211
return cell_height;
216212
}
217213

218-
const int Grid::getWidth()
214+
int Grid::getWidth()
219215
{
220216
return cell_width;
221217
}
222218

223-
const int Grid::numLayouts()
219+
int Grid::numLayouts()
224220
{
225221
return layouts_.size();
226222
}
227223

228-
const int Grid::getRowWidth()
224+
int Grid::getRowWidth()
229225
{
230226
int row_width = 0;
231227
for (auto& layout : layouts_) {

‎src/ram/src/layout.h‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -28,9 +28,9 @@ class Cell
2828

2929
void setOrigin(odb::Point position);
3030

31-
const int getHeight();
31+
int getHeight();
3232

33-
const int getWidth();
33+
int getWidth();
3434

3535
private:
3636
odb::Point origin_;
@@ -55,9 +55,9 @@ class Layout
5555

5656
void setOrigin(odb::Point position);
5757

58-
const int getHeight();
58+
int getHeight();
5959

60-
const int getWidth();
60+
int getWidth();
6161

6262
private:
6363
odb::Orientation2D orientation_;
@@ -86,13 +86,13 @@ class Grid
8686

8787
void setOrigin(odb::Point position);
8888

89-
const int getHeight();
89+
int getHeight();
9090

91-
const int getWidth();
91+
int getWidth();
9292

93-
const int numLayouts();
93+
int numLayouts();
9494

95-
const int getRowWidth();
95+
int getRowWidth();
9696

9797
private:
9898
odb::Orientation2D orientation_;

‎src/ram/src/ram.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -295,15 +295,15 @@ void RamGen::findMasters()
295295
{
296296
if (!inv_cell_) {
297297
inv_cell_ = findMaster(
298-
[this](sta::LibertyPort* port) {
298+
[](sta::LibertyPort* port) {
299299
return port->libertyCell()->isInverter();
300300
},
301301
"inverter");
302302
}
303303

304304
if (!tristate_cell_) {
305305
tristate_cell_ = findMaster(
306-
[this](sta::LibertyPort* port) {
306+
[](sta::LibertyPort* port) {
307307
if (!port->direction()->isTristate()) {
308308
return false;
309309
}
@@ -315,7 +315,7 @@ void RamGen::findMasters()
315315

316316
if (!and2_cell_) {
317317
and2_cell_ = findMaster(
318-
[this](sta::LibertyPort* port) {
318+
[](sta::LibertyPort* port) {
319319
if (!port->direction()->isOutput()) {
320320
return false;
321321
}
@@ -330,7 +330,7 @@ void RamGen::findMasters()
330330
if (!storage_cell_) {
331331
// FIXME
332332
storage_cell_ = findMaster(
333-
[this](sta::LibertyPort* port) {
333+
[](sta::LibertyPort* port) {
334334
if (!port->direction()->isOutput()) {
335335
return false;
336336
}
@@ -344,15 +344,15 @@ void RamGen::findMasters()
344344

345345
if (!clock_gate_cell_) {
346346
clock_gate_cell_ = findMaster(
347-
[this](sta::LibertyPort* port) {
347+
[](sta::LibertyPort* port) {
348348
return port->libertyCell()->isClockGate();
349349
},
350350
"clock gate");
351351
}
352352
// for input buffers
353353
if (!buffer_cell_) {
354354
buffer_cell_ = findMaster(
355-
[this](sta::LibertyPort* port) {
355+
[](sta::LibertyPort* port) {
356356
return port->libertyCell()->isBuffer();
357357
},
358358
"buffer");

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