@@ -25,16 +25,6 @@ POWER_STAGE_STEM = {
2525# each number is a unit
2626# current unit is configured as 2.16 which is on the routing grid for M5
2727
28- # table of Elements - (rows cols width height pitch_x pitch_y)
29- MOCK_ARRAY_TABLE = [
30- 8 ,
31- 8 ,
32- 20 ,
33- 20 ,
34- 20 ,
35- 22 ,
36- ]
37-
3828MOCK_ARRAY_SCALE = 45
3929
4030# Routing pitches for relevant metal layers.
@@ -50,7 +40,7 @@ placement_grid_x = 0.048 * MOCK_ARRAY_SCALE
5040placement_grid_y = 0.048 * MOCK_ARRAY_SCALE
5141
5242# number of Elements in row and column, can be control by user via environment variable
53- # MOCK_ARRAY_TABLE (rows, cols, width, height, pitch_x, pitch_y)
43+ #
5444# rows, cols - number of Element in rows, cols
5545# width, height - width and height of each Element
5646#
@@ -59,7 +49,17 @@ placement_grid_y = 0.048 * MOCK_ARRAY_SCALE
5949#
6050# pitch_x, pitch_y - placement pitch for each Element, in x and y direction
6151# specification are in unit of placement grid
62- rows , cols , ce_x , ce_y , pitch_x , pitch_y = MOCK_ARRAY_TABLE
52+ rows = 8
53+
54+ cols = 8
55+
56+ ce_x = 20
57+
58+ ce_y = 20
59+
60+ pitch_x = 20
61+
62+ pitch_y = 22
6363
6464# Element size is set to multiple of placement grid above
6565ce_width = ce_x * placement_grid_x
@@ -83,16 +83,16 @@ array_spacing_y = margin_y * 2
8383
8484# top level core and die size
8585core_width = (
86- 2 * array_spacing_x + ((placement_grid_x * pitch_x ) * (cols - 1 )) + ce_width
86+ 2 * margin_x + ((placement_grid_x * pitch_x ) * (cols - 1 )) + ce_width
8787)
8888
8989core_height = (
90- 2 * array_spacing_y + ((placement_grid_y * pitch_y ) * (rows - 1 )) + ce_height
90+ 2 * margin_y + ((placement_grid_y * pitch_y ) * (rows - 1 )) + ce_height
9191)
9292
93- die_width = core_width + (margin_x * 2 )
93+ die_width = core_width + (array_spacing_x * 2 )
9494
95- die_height = core_height + (margin_y * 2 )
95+ die_height = core_height + (array_spacing_y * 2 )
9696
9797filegroup (
9898 name = "mock-array-constraints" ,
@@ -122,10 +122,10 @@ VARIANTS = [
122122 name = "MockArray" ,
123123 arguments = {
124124 "CORE_AREA" : "{} {} {} {}" .format (
125- margin_x ,
126- margin_y ,
127- core_width + margin_x ,
128- core_height + margin_y ,
125+ array_spacing_x ,
126+ array_spacing_y ,
127+ array_spacing_x + core_width ,
128+ array_spacing_y + core_height ,
129129 ),
130130 "DETAILED_ROUTE_END_ITERATION" : "6" ,
131131 "DIE_AREA" : "0 0 {} {}" .format (
@@ -155,7 +155,7 @@ VARIANTS = [
155155 macros = ["Element_generate_abstract" ],
156156 sources = {
157157 "IO_CONSTRAINTS" : [":mock-array-io" ],
158- "RULES_JSON" : [":rules-base .json" ],
158+ "RULES_JSON" : [":rules-{variant} .json" . format ( variant = variant ) ],
159159 "SDC_FILE" : [":mock-array-constraints" ],
160160 },
161161 tags = ["manual" ],
@@ -232,8 +232,8 @@ fir_library(
232232 ],
233233 generator = ":generate_verilog" ,
234234 opts = [
235- "--width=8" ,
236- "--height=8" ,
235+ "--width=" + str ( cols ) ,
236+ "--height=" + str ( rows ) ,
237237 "--dataWidth=64" ,
238238 "--" ,
239239 # Imagine Chisel arguments here
0 commit comments