Added a new regression get_ports2.tcl and get_ports2_hier.tcl.

Signed-off-by: Jaehyun Kim <[email protected]>

Author: jhkim-pii

src/dbSta/test/BUILD

@@ -12,6 +12,8 @@ COMPULSORY_TESTS = [
     "find_clks2",
     "get_ports1",
     "get_ports1_hier",
+    "get_ports2",
+    "get_ports2_hier",
     "hier2",
     "hierclock",
     "hierwrite",
@@ -114,6 +116,7 @@ filegroup(
         "example1_slow.lib",
         "example1_typ.lib",
         "get_ports1.v",
+        "get_ports2.v",
         "helpers.tcl",
         "hier1.def",
         "hier1.sdc",

src/dbSta/test/CMakeLists.txt

@@ -9,6 +9,8 @@ or_integration_tests(
     find_clks2
     get_ports1
     get_ports1_hier
+    get_ports2
+    get_ports2_hier
     hier2
     hierclock
     hierwrite

src/dbSta/test/get_ports2.ok

@@ -0,0 +1,29 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: Nangate45/fakeram45_64x7.lef, created 1 library cells
+clk
+count: 1
+
+ce_in
+count: 1
+
+we_in
+count: 1
+
+{addr_in[0]} {addr_in[1]} {addr_in[2]} {addr_in[3]} {addr_in[4]} {addr_in[5]}
+count: 6
+
+{wd_in[0]} {wd_in[1]} {wd_in[2]} {wd_in[3]} {wd_in[4]} {wd_in[5]} {wd_in[6]}
+count: 7
+
+{w_mask_in[0]} {w_mask_in[1]} {w_mask_in[2]} {w_mask_in[3]} {w_mask_in[4]} {w_mask_in[5]} {w_mask_in[6]}
+count: 7
+
+{rd_out[0]} {rd_out[1]} {rd_out[2]} {rd_out[3]} {rd_out[4]} {rd_out[5]} {rd_out[6]}
+count: 7
+
+clk
+count: 1
+
+{addr_in[0]} {addr_in[1]} {addr_in[2]} {addr_in[3]} {addr_in[4]} {addr_in[5]}
+count: 6
+

src/dbSta/test/get_ports2.tcl

@@ -0,0 +1,29 @@
+# get_pins on a bus port of leaf liberty instance
+source "helpers.tcl"
+
+proc print_info { objs } {
+  set obj_names {}
+  foreach obj $objs {
+    lappend obj_names [get_name $obj]
+  }
+  puts "[lsort $obj_names]"
+  puts "count: [llength $objs]"
+  puts ""
+}
+
+read_liberty Nangate45/Nangate45_typ.lib
+read_liberty Nangate45/fakeram45_64x7.lib
+read_lef Nangate45/Nangate45.lef
+read_lef Nangate45/fakeram45_64x7.lef
+read_verilog get_ports2.v
+link_design top
+
+print_info [get_ports clk]
+print_info [get_ports ce_in]
+print_info [get_ports we_in]
+print_info [get_ports addr_in*]
+print_info [get_ports wd_in*]
+print_info [get_ports w_mask_in*]
+print_info [get_ports rd_out*]
+print_info [get_pins sram/clk]
+print_info [get_pins sram/addr_in*]

src/dbSta/test/get_ports2.v

@@ -0,0 +1,21 @@
+module top (
+  input clk,
+  input ce_in,
+  input we_in,
+  input [5:0] addr_in,
+  input [6:0] wd_in,
+  input [6:0] w_mask_in,
+  output [6:0] rd_out
+);
+
+  fakeram45_64x7 sram (
+    .clk(clk),
+    .ce_in(ce_in),
+    .we_in(we_in),
+    .addr_in(addr_in),
+    .wd_in(wd_in),
+    .w_mask_in(w_mask_in),
+    .rd_out(rd_out)
+  );
+
+endmodule

src/dbSta/test/get_ports2_hier.ok

@@ -0,0 +1,30 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: Nangate45/fakeram45_64x7.lef, created 1 library cells
+[WARNING ORD-0011] Hierarchical flow (-hier) is currently in development and may cause multiple issues. Do not use in production environments.
+clk
+count: 1
+
+ce_in
+count: 1
+
+we_in
+count: 1
+
+{addr_in[0]} {addr_in[1]} {addr_in[2]} {addr_in[3]} {addr_in[4]} {addr_in[5]}
+count: 6
+
+{wd_in[0]} {wd_in[1]} {wd_in[2]} {wd_in[3]} {wd_in[4]} {wd_in[5]} {wd_in[6]}
+count: 7
+
+{w_mask_in[0]} {w_mask_in[1]} {w_mask_in[2]} {w_mask_in[3]} {w_mask_in[4]} {w_mask_in[5]} {w_mask_in[6]}
+count: 7
+
+{rd_out[0]} {rd_out[1]} {rd_out[2]} {rd_out[3]} {rd_out[4]} {rd_out[5]} {rd_out[6]}
+count: 7
+
+clk
+count: 1
+
+{addr_in[0]} {addr_in[1]} {addr_in[2]} {addr_in[3]} {addr_in[4]} {addr_in[5]}
+count: 6
+

src/dbSta/test/get_ports2_hier.tcl

@@ -0,0 +1,29 @@
+# get_pins on a bus port of leaf liberty instance
+source "helpers.tcl"
+
+proc print_info { objs } {
+  set obj_names {}
+  foreach obj $objs {
+    lappend obj_names [get_name $obj]
+  }
+  puts "[lsort $obj_names]"
+  puts "count: [llength $objs]"
+  puts ""
+}
+
+read_liberty Nangate45/Nangate45_typ.lib
+read_liberty Nangate45/fakeram45_64x7.lib
+read_lef Nangate45/Nangate45.lef
+read_lef Nangate45/fakeram45_64x7.lef
+read_verilog get_ports2.v
+link_design -hier top
+
+print_info [get_ports clk]
+print_info [get_ports ce_in]
+print_info [get_ports we_in]
+print_info [get_ports addr_in*]
+print_info [get_ports wd_in*]
+print_info [get_ports w_mask_in*]
+print_info [get_ports rd_out*]
+print_info [get_pins sram/clk]
+print_info [get_pins sram/addr_in*]