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cts: Update tests after rsz change
Signed-off-by: Martin Povišer <[email protected]>
1 parent b6b55e8 commit 812d6a0

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4 files changed

+340
-359
lines changed

4 files changed

+340
-359
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‎src/cts/test/array.ok‎

Lines changed: 101 additions & 106 deletions
Original file line numberDiff line numberDiff line change
@@ -125,22 +125,22 @@ Dummys used:
125125
INV_X4: 1
126126
[INFO RSZ-0058] Using max wire length 693um.
127127
[INFO RSZ-0047] Found 41 long wires.
128-
[INFO RSZ-0048] Inserted 165 buffers in 41 nets.
128+
[INFO RSZ-0048] Inserted 92 buffers in 41 nets.
129129
Placement Analysis
130130
---------------------------------
131-
total displacement 4186.7 u
132-
average displacement 1.3 u
133-
max displacement 143.4 u
134-
original HPWL 192698.4 u
135-
legalized HPWL 193625.0 u
136-
delta HPWL 0 %
131+
total displacement 3816.2 u
132+
average displacement 1.2 u
133+
max displacement 140.5 u
134+
original HPWL 192614.2 u
135+
legalized HPWL 193656.0 u
136+
delta HPWL 1 %
137137

138138
Clock clk
139-
1.03 source latency inst_5_4/clk ^
140-
-1.18 target latency inst_6_4/clk ^
139+
1.15 source latency inst_3_9/clk ^
140+
-1.01 target latency inst_5_9/clk ^
141141
0.00 CRPR
142142
--------------
143-
-0.15 setup skew
143+
0.14 setup skew
144144

145145
Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk)
146146
Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)
@@ -152,76 +152,74 @@ Path Type: max
152152
0.00 0.00 clock clk (rise edge)
153153
0.00 0.00 clock source latency
154154
0.00 0.00 ^ clk (in)
155-
0.04 0.04 ^ wire9/Z (BUF_X8)
156-
0.03 0.07 ^ wire8/Z (BUF_X16)
157-
0.06 0.13 ^ wire6/Z (BUF_X8)
158-
0.05 0.18 ^ wire5/Z (BUF_X16)
159-
0.05 0.23 ^ wire4/Z (BUF_X16)
160-
0.06 0.29 ^ wire3/Z (BUF_X32)
161-
0.06 0.34 ^ wire2/Z (BUF_X32)
162-
0.04 0.39 ^ wire1/Z (BUF_X32)
163-
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
164-
0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
165-
0.04 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
155+
0.05 0.05 ^ wire7/Z (BUF_X16)
156+
0.05 0.10 ^ wire6/Z (BUF_X16)
157+
0.06 0.15 ^ wire5/Z (BUF_X8)
158+
0.03 0.18 ^ wire4/Z (BUF_X16)
159+
0.07 0.25 ^ wire3/Z (BUF_X32)
160+
0.07 0.32 ^ wire2/Z (BUF_X32)
161+
0.07 0.38 ^ wire1/Z (BUF_X32)
162+
0.06 0.44 ^ clkbuf_0_clk/Z (BUF_X4)
163+
0.04 0.48 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
164+
0.04 0.52 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
166165
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
167-
0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
168-
0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
166+
0.03 0.59 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
167+
0.04 0.63 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
169168
0.03 0.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
170-
0.03 0.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
169+
0.03 0.70 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
171170
0.03 0.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
172171
0.03 0.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
173172
0.04 0.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
174-
0.03 0.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
173+
0.03 0.84 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
175174
0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
176-
0.03 0.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
175+
0.03 0.91 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
177176
0.04 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
178177
0.05 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
179-
0.04 1.05 ^ wire14/Z (BUF_X8)
180-
0.05 1.10 ^ load_slew11/Z (BUF_X1)
181-
0.03 1.13 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
182-
0.00 1.13 ^ inst_1_1/clk (array_tile)
183-
0.21 1.35 ^ inst_1_1/e_out (array_tile)
184-
0.00 1.35 ^ inst_2_1/w_in (array_tile)
185-
1.35 data arrival time
178+
0.04 1.04 ^ wire9/Z (BUF_X8)
179+
0.04 1.09 ^ max_length8/Z (BUF_X8)
180+
0.05 1.14 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
181+
0.00 1.14 ^ inst_1_1/clk (array_tile)
182+
0.21 1.36 ^ inst_1_1/e_out (array_tile)
183+
0.00 1.36 ^ inst_2_1/w_in (array_tile)
184+
1.36 data arrival time
186185

187186
5.00 5.00 clock clk (rise edge)
188187
0.00 5.00 clock source latency
189188
0.00 5.00 ^ clk (in)
190-
0.04 5.04 ^ wire9/Z (BUF_X8)
191-
0.03 5.07 ^ wire8/Z (BUF_X16)
192-
0.06 5.13 ^ wire6/Z (BUF_X8)
193-
0.05 5.18 ^ wire5/Z (BUF_X16)
194-
0.05 5.23 ^ wire4/Z (BUF_X16)
195-
0.06 5.29 ^ wire3/Z (BUF_X32)
196-
0.06 5.34 ^ wire2/Z (BUF_X32)
197-
0.04 5.39 ^ wire1/Z (BUF_X32)
198-
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
199-
0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
200-
0.04 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
189+
0.05 5.05 ^ wire7/Z (BUF_X16)
190+
0.05 5.10 ^ wire6/Z (BUF_X16)
191+
0.06 5.15 ^ wire5/Z (BUF_X8)
192+
0.03 5.18 ^ wire4/Z (BUF_X16)
193+
0.07 5.25 ^ wire3/Z (BUF_X32)
194+
0.07 5.32 ^ wire2/Z (BUF_X32)
195+
0.07 5.38 ^ wire1/Z (BUF_X32)
196+
0.06 5.44 ^ clkbuf_0_clk/Z (BUF_X4)
197+
0.04 5.48 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
198+
0.04 5.52 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
201199
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
202-
0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
203-
0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
200+
0.03 5.59 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
201+
0.04 5.63 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
204202
0.03 5.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
205-
0.03 5.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
203+
0.03 5.70 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
206204
0.03 5.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
207205
0.03 5.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
208206
0.04 5.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
209-
0.03 5.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
207+
0.03 5.84 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
210208
0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
211-
0.03 5.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
209+
0.03 5.91 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
212210
0.04 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
213211
0.05 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
214-
0.04 6.04 ^ load_slew18/Z (BUF_X8)
215-
0.03 6.07 ^ load_slew16/Z (BUF_X1)
216-
0.00 6.07 ^ inst_2_1/clk (array_tile)
217-
0.00 6.07 clock reconvergence pessimism
218-
-0.05 6.02 library setup time
219-
6.02 data required time
212+
0.04 6.04 ^ max_length11/Z (BUF_X8)
213+
0.04 6.07 ^ max_length10/Z (BUF_X8)
214+
0.02 6.10 ^ inst_2_1/clk (array_tile)
215+
0.00 6.10 clock reconvergence pessimism
216+
-0.05 6.05 library setup time
217+
6.05 data required time
220218
---------------------------------------------------------
221-
6.02 data required time
222-
-1.35 data arrival time
219+
6.05 data required time
220+
-1.36 data arrival time
223221
---------------------------------------------------------
224-
4.67 slack (MET)
222+
4.69 slack (MET)
225223

226224

227225
Startpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)
@@ -234,75 +232,72 @@ Path Type: max
234232
0.00 0.00 clock clk (rise edge)
235233
0.00 0.00 clock source latency
236234
0.00 0.00 ^ clk (in)
237-
0.04 0.04 ^ wire9/Z (BUF_X8)
238-
0.03 0.07 ^ wire8/Z (BUF_X16)
239-
0.06 0.13 ^ wire6/Z (BUF_X8)
240-
0.05 0.18 ^ wire5/Z (BUF_X16)
241-
0.05 0.23 ^ wire4/Z (BUF_X16)
242-
0.06 0.29 ^ wire3/Z (BUF_X32)
243-
0.06 0.34 ^ wire2/Z (BUF_X32)
244-
0.04 0.39 ^ wire1/Z (BUF_X32)
245-
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
246-
0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
247-
0.04 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
235+
0.05 0.05 ^ wire7/Z (BUF_X16)
236+
0.05 0.10 ^ wire6/Z (BUF_X16)
237+
0.06 0.15 ^ wire5/Z (BUF_X8)
238+
0.03 0.18 ^ wire4/Z (BUF_X16)
239+
0.07 0.25 ^ wire3/Z (BUF_X32)
240+
0.07 0.32 ^ wire2/Z (BUF_X32)
241+
0.07 0.38 ^ wire1/Z (BUF_X32)
242+
0.06 0.44 ^ clkbuf_0_clk/Z (BUF_X4)
243+
0.04 0.48 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
244+
0.04 0.52 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
248245
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
249-
0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
250-
0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
246+
0.03 0.59 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
247+
0.04 0.63 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
251248
0.03 0.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
252-
0.03 0.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
249+
0.03 0.70 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
253250
0.03 0.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
254251
0.03 0.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
255252
0.04 0.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
256-
0.03 0.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
253+
0.03 0.84 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
257254
0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
258-
0.03 0.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
255+
0.03 0.91 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
259256
0.04 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
260257
0.05 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
261-
0.04 1.04 ^ load_slew18/Z (BUF_X8)
262-
0.03 1.07 ^ load_slew16/Z (BUF_X1)
263-
0.00 1.07 ^ inst_2_1/clk (array_tile)
264-
0.21 1.28 ^ inst_2_1/e_out (array_tile)
265-
0.00 1.28 ^ inst_3_1/w_in (array_tile)
266-
1.28 data arrival time
258+
0.04 1.04 ^ max_length11/Z (BUF_X8)
259+
0.04 1.07 ^ max_length10/Z (BUF_X8)
260+
0.02 1.10 ^ inst_2_1/clk (array_tile)
261+
0.21 1.31 ^ inst_2_1/e_out (array_tile)
262+
0.00 1.31 ^ inst_3_1/w_in (array_tile)
263+
1.31 data arrival time
267264

268265
5.00 5.00 clock clk (rise edge)
269266
0.00 5.00 clock source latency
270267
0.00 5.00 ^ clk (in)
271-
0.04 5.04 ^ wire9/Z (BUF_X8)
272-
0.03 5.07 ^ wire8/Z (BUF_X16)
273-
0.06 5.13 ^ wire6/Z (BUF_X8)
274-
0.05 5.18 ^ wire5/Z (BUF_X16)
275-
0.05 5.23 ^ wire4/Z (BUF_X16)
276-
0.06 5.29 ^ wire3/Z (BUF_X32)
277-
0.06 5.34 ^ wire2/Z (BUF_X32)
278-
0.04 5.39 ^ wire1/Z (BUF_X32)
279-
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
280-
0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
281-
0.04 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
268+
0.05 5.05 ^ wire7/Z (BUF_X16)
269+
0.05 5.10 ^ wire6/Z (BUF_X16)
270+
0.06 5.15 ^ wire5/Z (BUF_X8)
271+
0.03 5.18 ^ wire4/Z (BUF_X16)
272+
0.07 5.25 ^ wire3/Z (BUF_X32)
273+
0.07 5.32 ^ wire2/Z (BUF_X32)
274+
0.07 5.38 ^ wire1/Z (BUF_X32)
275+
0.06 5.44 ^ clkbuf_0_clk/Z (BUF_X4)
276+
0.04 5.48 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
277+
0.04 5.52 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
282278
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
283-
0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
284-
0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
279+
0.03 5.59 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
280+
0.04 5.63 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
285281
0.03 5.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
286-
0.03 5.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
282+
0.03 5.70 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
287283
0.03 5.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
288284
0.03 5.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
289285
0.04 5.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
290-
0.03 5.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
286+
0.03 5.84 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
291287
0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
292-
0.03 5.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
288+
0.03 5.91 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
293289
0.04 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
294290
0.05 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
295-
0.04 6.04 ^ load_slew18/Z (BUF_X8)
296-
0.04 6.08 ^ wire17/Z (BUF_X4)
297-
0.04 6.12 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
298-
0.00 6.12 ^ inst_3_1/clk (array_tile)
299-
0.00 6.12 clock reconvergence pessimism
300-
-0.05 6.07 library setup time
301-
6.07 data required time
291+
0.04 6.04 ^ max_length11/Z (BUF_X8)
292+
0.05 6.09 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
293+
0.00 6.09 ^ inst_3_1/clk (array_tile)
294+
0.00 6.09 clock reconvergence pessimism
295+
-0.05 6.04 library setup time
296+
6.04 data required time
302297
---------------------------------------------------------
303-
6.07 data required time
304-
-1.28 data arrival time
298+
6.04 data required time
299+
-1.31 data arrival time
305300
---------------------------------------------------------
306-
4.79 slack (MET)
301+
4.73 slack (MET)
307302

308303

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