@@ -431,22 +431,6 @@ uint extRCModel::benchDB_WS(extMainOptions* opt, extMeasure* measure)
431431 }
432432 } else if (opt->_nondefault_lef_rules ) {
433433 return 0 ;
434- wTable->resetCnt ();
435- sTable ->resetCnt ();
436- dbSet<dbTechNonDefaultRule> nd_rules = opt->_tech ->getNonDefaultRules ();
437- dbSet<dbTechNonDefaultRule>::iterator nditr;
438- dbTechLayerRule* tst_rule;
439-
440- for (nditr = nd_rules.begin (); nditr != nd_rules.end (); ++nditr) {
441- tst_rule = (*nditr)->getLayerRule (layer);
442- if (tst_rule == NULL )
443- continue ;
444-
445- double w = tst_rule->getWidth ();
446- double s = tst_rule->getSpacing ();
447- wTable->add (w);
448- sTable ->add (s);
449- }
450434 } else {
451435 if (measure->_diag )
452436 spaceTable->add (0.0 );
@@ -646,7 +630,6 @@ int extRCModel::writeBenchWires_DB(extMeasure* measure)
646630 uint WW2 = measure->_w2_nm ;
647631 uint SS2 = measure->_s2_nm ;
648632
649- uint base;
650633 if (n > 1 ) {
651634 cnt++;
652635 measure->createNetSingleWire (_wireDirName, idCnt, WW, s_layout);
@@ -655,7 +638,6 @@ int extRCModel::writeBenchWires_DB(extMeasure* measure)
655638 cnt++;
656639 if (!measure->_diag ) {
657640 measure->createNetSingleWire (_wireDirName, idCnt, WW, SS1);
658- base = measure->_ll [measure->_dir ] + WW / 2 ;
659641 idCnt++;
660642 cnt++;
661643 measure->createNetSingleWire (_wireDirName, idCnt, WW2, SS2);
@@ -681,40 +663,13 @@ int extRCModel::writeBenchWires_DB(extMeasure* measure)
681663 idCnt++;
682664 }
683665 } else {
684- base = measure->_ll [measure->_dir ] + WW / 2 ;
685666 cnt++;
686667 measure->createNetSingleWire (_wireDirName, 3 , w_layout, s_layout);
687668 idCnt++;
688669 }
689670
690671 if (measure->_diag ) {
691672 return cnt;
692-
693- int met;
694- if (measure->_overMet > 0 )
695- met = measure->_overMet ;
696- else if (measure->_underMet > 0 )
697- met = measure->_underMet ;
698-
699- double minWidth = measure->_minWidth ;
700- double minSpace = measure->_minSpace ;
701- double min_pitch = minWidth + minSpace;
702- measure->clean2dBoxTable (met, false );
703- int i;
704- uint begin = base - Ath__double2int (measure->_seff * 1000 )
705- + Ath__double2int (minWidth * 1000 ) / 2 ;
706- for (i = 0 ; i < n + 1 ; i++) {
707- measure->createDiagNetSingleWire (_wireDirName,
708- idCnt,
709- begin,
710- Ath__double2int (1000 * minWidth),
711- Ath__double2int (1000 * minSpace),
712- measure->_dir );
713- begin -= Ath__double2int (min_pitch * 1000 );
714- idCnt++;
715- }
716- measure->_ur [measure->_dir ] += grid_gap_cnt * (w_layout + s_layout);
717- return cnt;
718673 }
719674 bool grid_context = true ;
720675 bool grid_context_same_dir = false ;
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