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gadfortgadfort
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pad: correct rounding error when target spacing is not a multiple of the site
Signed-off-by: Peter Gadfort <[email protected]>
1 parent 364cb4b commit 8285e9c

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4 files changed

+504
-491
lines changed

4 files changed

+504
-491
lines changed

‎src/pad/src/ICeWall.cpp‎

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1042,9 +1042,22 @@ void ICeWall::placePadsUniform(const std::vector<odb::dbInst*>& insts,
10421042
const bool gui_debug
10431043
= logger_->debugCheck(utl::PAD, "Place", 1) && gui::Gui::get()->enabled();
10441044

1045-
const double dbus = getBlock()->getDbUnitsPerMicron();
1046-
const int target_spacing = (row_width - pads_width) / (insts.size() + 1);
1045+
const float initial_target_spacing
1046+
= static_cast<float>(row_width - pads_width) / (insts.size() + 1);
1047+
const int site_width
1048+
= std::min(row->getSite()->getWidth(), row->getSite()->getHeight());
1049+
const int target_spacing
1050+
= std::floor(initial_target_spacing / site_width) * site_width;
10471051
int offset = row_start + target_spacing;
1052+
1053+
const double dbus = getBlock()->getDbUnitsPerMicron();
1054+
debugPrint(logger_,
1055+
utl::PAD,
1056+
"Place",
1057+
1,
1058+
"Placing pads with uniform: spacing {:.4f} um",
1059+
target_spacing / dbus);
1060+
10481061
for (auto* inst : insts) {
10491062
debugPrint(logger_,
10501063
utl::PAD,

‎src/pad/test/place_pads_bumps_strategy.defok‎

Lines changed: 88 additions & 88 deletions
Original file line numberDiff line numberDiff line change
@@ -309,35 +309,35 @@ COMPONENTS 543 ;
309309
- BUMP_9_6 DUMMY_BUMP + FIXED ( 3300000 2350000 ) N ;
310310
- BUMP_9_7 DUMMY_BUMP + FIXED ( 3300000 2670000 ) N ;
311311
- BUMP_9_9 DUMMY_BUMP + FIXED ( 3300000 3310000 ) N ;
312-
- u_bsg_tag_clk_i PADCELL_SIG_H + FIXED ( 5690000 3108000 ) W ;
312+
- u_bsg_tag_clk_i PADCELL_SIG_H + FIXED ( 5690000 3076000 ) W ;
313313
- u_bsg_tag_clk_o PADCELL_SIG_H + FIXED ( 30000 3826000 ) FW ;
314-
- u_bsg_tag_data_i PADCELL_SIG_H + FIXED ( 5690000 3376000 ) W ;
314+
- u_bsg_tag_data_i PADCELL_SIG_H + FIXED ( 5690000 3340000 ) W ;
315315
- u_bsg_tag_data_o PADCELL_SIG_H + FIXED ( 30000 3626000 ) FW ;
316-
- u_bsg_tag_en_i PADCELL_SIG_H + FIXED ( 5690000 3464000 ) W ;
316+
- u_bsg_tag_en_i PADCELL_SIG_H + FIXED ( 5690000 3428000 ) W ;
317317
- u_ci2_0_o PADCELL_SIG_V + FIXED ( 3940000 5690000 ) FS ;
318318
- u_ci2_1_o PADCELL_SIG_V + FIXED ( 3990000 5690000 ) FS ;
319319
- u_ci2_2_o PADCELL_SIG_V + FIXED ( 4206000 5690000 ) FS ;
320320
- u_ci2_3_o PADCELL_SIG_V + FIXED ( 4256000 5690000 ) FS ;
321321
- u_ci2_4_o PADCELL_SIG_V + FIXED ( 4306000 5690000 ) FS ;
322322
- u_ci2_5_o PADCELL_SIG_V + FIXED ( 4920000 5690000 ) FS ;
323323
- u_ci2_6_o PADCELL_SIG_V + FIXED ( 5240000 5690000 ) FS ;
324-
- u_ci2_7_o PADCELL_SIG_V + FIXED ( 5690000 5600000 ) W ;
325-
- u_ci2_8_o PADCELL_SIG_V + FIXED ( 5690000 5512000 ) W ;
324+
- u_ci2_7_o PADCELL_SIG_V + FIXED ( 5690000 5540000 ) W ;
325+
- u_ci2_8_o PADCELL_SIG_V + FIXED ( 5690000 5452000 ) W ;
326326
- u_ci2_clk_o PADCELL_SIG_V + FIXED ( 4356000 5690000 ) FS ;
327327
- u_ci2_tkn_i PADCELL_SIG_V + FIXED ( 4576000 5690000 ) FS ;
328328
- u_ci2_v_o PADCELL_SIG_V + FIXED ( 4626000 5690000 ) FS ;
329-
- u_ci_0_i PADCELL_SIG_H + FIXED ( 5690000 5422000 ) W ;
330-
- u_ci_1_i PADCELL_SIG_H + FIXED ( 5690000 5156000 ) W ;
331-
- u_ci_2_i PADCELL_SIG_H + FIXED ( 5690000 4888000 ) W ;
332-
- u_ci_3_i PADCELL_SIG_H + FIXED ( 5690000 4800000 ) W ;
333-
- u_ci_4_i PADCELL_SIG_H + FIXED ( 5690000 4710000 ) W ;
334-
- u_ci_5_i PADCELL_SIG_H + FIXED ( 5690000 4176000 ) W ;
335-
- u_ci_6_i PADCELL_SIG_H + FIXED ( 5690000 4088000 ) W ;
336-
- u_ci_7_i PADCELL_SIG_H + FIXED ( 5690000 3820000 ) W ;
337-
- u_ci_8_i PADCELL_SIG_H + FIXED ( 5690000 3554000 ) W ;
338-
- u_ci_clk_i PADCELL_SIG_H + FIXED ( 5690000 4622000 ) W ;
339-
- u_ci_tkn_o PADCELL_SIG_H + FIXED ( 5690000 4354000 ) W ;
340-
- u_ci_v_i PADCELL_SIG_H + FIXED ( 5690000 4266000 ) W ;
329+
- u_ci_0_i PADCELL_SIG_H + FIXED ( 5690000 5364000 ) W ;
330+
- u_ci_1_i PADCELL_SIG_H + FIXED ( 5690000 5100000 ) W ;
331+
- u_ci_2_i PADCELL_SIG_H + FIXED ( 5690000 4836000 ) W ;
332+
- u_ci_3_i PADCELL_SIG_H + FIXED ( 5690000 4748000 ) W ;
333+
- u_ci_4_i PADCELL_SIG_H + FIXED ( 5690000 4660000 ) W ;
334+
- u_ci_5_i PADCELL_SIG_H + FIXED ( 5690000 4132000 ) W ;
335+
- u_ci_6_i PADCELL_SIG_H + FIXED ( 5690000 4044000 ) W ;
336+
- u_ci_7_i PADCELL_SIG_H + FIXED ( 5690000 3780000 ) W ;
337+
- u_ci_8_i PADCELL_SIG_H + FIXED ( 5690000 3516000 ) W ;
338+
- u_ci_clk_i PADCELL_SIG_H + FIXED ( 5690000 4572000 ) W ;
339+
- u_ci_tkn_o PADCELL_SIG_H + FIXED ( 5690000 4308000 ) W ;
340+
- u_ci_v_i PADCELL_SIG_H + FIXED ( 5690000 4220000 ) W ;
341341
- u_clk_A_i PADCELL_SIG_V + FIXED ( 2686000 5690000 ) FS ;
342342
- u_clk_B_i PADCELL_SIG_V + FIXED ( 3000000 5690000 ) FS ;
343343
- u_clk_C_i PADCELL_SIG_V + FIXED ( 3100000 5690000 ) FS ;
@@ -368,16 +368,16 @@ COMPONENTS 543 ;
368368
- u_co_tkn_o PADCELL_SIG_V + FIXED ( 2066000 5690000 ) FS ;
369369
- u_co_v_i PADCELL_SIG_V + FIXED ( 2116000 5690000 ) FS ;
370370
- u_core_async_reset_i PADCELL_SIG_V + FIXED ( 4040000 5690000 ) FS ;
371-
- u_ddr_addr_0_o PADCELL_SIG_V + FIXED ( 3574000 30000 ) N ;
371+
- u_ddr_addr_0_o PADCELL_SIG_V + FIXED ( 3572000 30000 ) N ;
372372
- u_ddr_addr_10_o PADCELL_SIG_V + FIXED ( 1916000 30000 ) N ;
373373
- u_ddr_addr_11_o PADCELL_SIG_V + FIXED ( 1824000 30000 ) N ;
374374
- u_ddr_addr_12_o PADCELL_SIG_V + FIXED ( 1548000 30000 ) N ;
375375
- u_ddr_addr_13_o PADCELL_SIG_V + FIXED ( 1456000 30000 ) N ;
376376
- u_ddr_addr_14_o PADCELL_SIG_V + FIXED ( 1364000 30000 ) N ;
377377
- u_ddr_addr_15_o PADCELL_SIG_V + FIXED ( 1272000 30000 ) N ;
378-
- u_ddr_addr_1_o PADCELL_SIG_V + FIXED ( 3298000 30000 ) N ;
379-
- u_ddr_addr_2_o PADCELL_SIG_V + FIXED ( 3206000 30000 ) N ;
380-
- u_ddr_addr_3_o PADCELL_SIG_V + FIXED ( 3114000 30000 ) N ;
378+
- u_ddr_addr_1_o PADCELL_SIG_V + FIXED ( 3296000 30000 ) N ;
379+
- u_ddr_addr_2_o PADCELL_SIG_V + FIXED ( 3204000 30000 ) N ;
380+
- u_ddr_addr_3_o PADCELL_SIG_V + FIXED ( 3112000 30000 ) N ;
381381
- u_ddr_addr_4_o PADCELL_SIG_V + FIXED ( 2836000 30000 ) N ;
382382
- u_ddr_addr_5_o PADCELL_SIG_V + FIXED ( 2744000 30000 ) N ;
383383
- u_ddr_addr_6_o PADCELL_SIG_V + FIXED ( 2652000 30000 ) N ;
@@ -387,40 +387,40 @@ COMPONENTS 543 ;
387387
- u_ddr_ba_0_o PADCELL_SIG_V + FIXED ( 996000 30000 ) N ;
388388
- u_ddr_ba_1_o PADCELL_SIG_V + FIXED ( 904000 30000 ) N ;
389389
- u_ddr_ba_2_o PADCELL_SIG_V + FIXED ( 812000 30000 ) N ;
390-
- u_ddr_cas_n_o PADCELL_SIG_V + FIXED ( 4126000 30000 ) N ;
391-
- u_ddr_ck_n_o PADCELL_SIG_V + FIXED ( 4678000 30000 ) N ;
392-
- u_ddr_ck_p_o PADCELL_SIG_V + FIXED ( 5138000 30000 ) N ;
393-
- u_ddr_cke_o PADCELL_SIG_V + FIXED ( 4586000 30000 ) N ;
394-
- u_ddr_cs_n_o PADCELL_SIG_V + FIXED ( 4494000 30000 ) N ;
390+
- u_ddr_cas_n_o PADCELL_SIG_V + FIXED ( 4124000 30000 ) N ;
391+
- u_ddr_ck_n_o PADCELL_SIG_V + FIXED ( 4676000 30000 ) N ;
392+
- u_ddr_ck_p_o PADCELL_SIG_V + FIXED ( 5136000 30000 ) N ;
393+
- u_ddr_cke_o PADCELL_SIG_V + FIXED ( 4584000 30000 ) N ;
394+
- u_ddr_cs_n_o PADCELL_SIG_V + FIXED ( 4492000 30000 ) N ;
395395
- u_ddr_dm_0_o PADCELL_SIG_H + FIXED ( 30000 2666000 ) FW ;
396396
- u_ddr_dm_1_o PADCELL_SIG_V + FIXED ( 352000 30000 ) N ;
397-
- u_ddr_dm_2_o PADCELL_SIG_V + FIXED ( 5414000 30000 ) N ;
398-
- u_ddr_dm_3_o PADCELL_SIG_H + FIXED ( 5690000 3020000 ) W ;
397+
- u_ddr_dm_2_o PADCELL_SIG_V + FIXED ( 5412000 30000 ) N ;
398+
- u_ddr_dm_3_o PADCELL_SIG_H + FIXED ( 5690000 2988000 ) W ;
399399
- u_ddr_dq_0_io PADCELL_SIG_H + FIXED ( 30000 2866000 ) FW ;
400400
- u_ddr_dq_10_io PADCELL_SIG_H + FIXED ( 30000 1680000 ) FW ;
401401
- u_ddr_dq_11_io PADCELL_SIG_H + FIXED ( 30000 2026000 ) FW ;
402402
- u_ddr_dq_12_io PADCELL_SIG_H + FIXED ( 30000 2076000 ) FW ;
403403
- u_ddr_dq_13_io PADCELL_SIG_H + FIXED ( 30000 2226000 ) FW ;
404404
- u_ddr_dq_14_io PADCELL_SIG_H + FIXED ( 30000 2320000 ) FW ;
405405
- u_ddr_dq_15_io PADCELL_SIG_H + FIXED ( 30000 2370000 ) FW ;
406-
- u_ddr_dq_16_io PADCELL_SIG_H + FIXED ( 5690000 1328000 ) W ;
407-
- u_ddr_dq_17_io PADCELL_SIG_H + FIXED ( 5690000 1240000 ) W ;
408-
- u_ddr_dq_18_io PADCELL_SIG_H + FIXED ( 5690000 1150000 ) W ;
409-
- u_ddr_dq_19_io PADCELL_SIG_H + FIXED ( 5690000 1062000 ) W ;
406+
- u_ddr_dq_16_io PADCELL_SIG_H + FIXED ( 5690000 1316000 ) W ;
407+
- u_ddr_dq_17_io PADCELL_SIG_H + FIXED ( 5690000 1228000 ) W ;
408+
- u_ddr_dq_18_io PADCELL_SIG_H + FIXED ( 5690000 1140000 ) W ;
409+
- u_ddr_dq_19_io PADCELL_SIG_H + FIXED ( 5690000 1052000 ) W ;
410410
- u_ddr_dq_1_io PADCELL_SIG_H + FIXED ( 30000 3010000 ) FW ;
411-
- u_ddr_dq_20_io PADCELL_SIG_H + FIXED ( 5690000 794000 ) W ;
412-
- u_ddr_dq_21_io PADCELL_SIG_H + FIXED ( 5690000 528000 ) W ;
413-
- u_ddr_dq_22_io PADCELL_SIG_H + FIXED ( 5690000 438000 ) W ;
414-
- u_ddr_dq_23_io PADCELL_SIG_H + FIXED ( 5690000 350000 ) W ;
415-
- u_ddr_dq_24_io PADCELL_SIG_H + FIXED ( 5690000 2574000 ) W ;
416-
- u_ddr_dq_25_io PADCELL_SIG_H + FIXED ( 5690000 2486000 ) W ;
417-
- u_ddr_dq_26_io PADCELL_SIG_H + FIXED ( 5690000 2396000 ) W ;
418-
- u_ddr_dq_27_io PADCELL_SIG_H + FIXED ( 5690000 2130000 ) W ;
419-
- u_ddr_dq_28_io PADCELL_SIG_H + FIXED ( 5690000 1862000 ) W ;
420-
- u_ddr_dq_29_io PADCELL_SIG_H + FIXED ( 5690000 1774000 ) W ;
411+
- u_ddr_dq_20_io PADCELL_SIG_H + FIXED ( 5690000 788000 ) W ;
412+
- u_ddr_dq_21_io PADCELL_SIG_H + FIXED ( 5690000 524000 ) W ;
413+
- u_ddr_dq_22_io PADCELL_SIG_H + FIXED ( 5690000 436000 ) W ;
414+
- u_ddr_dq_23_io PADCELL_SIG_H + FIXED ( 5690000 348000 ) W ;
415+
- u_ddr_dq_24_io PADCELL_SIG_H + FIXED ( 5690000 2548000 ) W ;
416+
- u_ddr_dq_25_io PADCELL_SIG_H + FIXED ( 5690000 2460000 ) W ;
417+
- u_ddr_dq_26_io PADCELL_SIG_H + FIXED ( 5690000 2372000 ) W ;
418+
- u_ddr_dq_27_io PADCELL_SIG_H + FIXED ( 5690000 2108000 ) W ;
419+
- u_ddr_dq_28_io PADCELL_SIG_H + FIXED ( 5690000 1844000 ) W ;
420+
- u_ddr_dq_29_io PADCELL_SIG_H + FIXED ( 5690000 1756000 ) W ;
421421
- u_ddr_dq_2_io PADCELL_SIG_H + FIXED ( 30000 3160000 ) FW ;
422-
- u_ddr_dq_30_io PADCELL_SIG_H + FIXED ( 5690000 1684000 ) W ;
423-
- u_ddr_dq_31_io PADCELL_SIG_H + FIXED ( 5690000 1596000 ) W ;
422+
- u_ddr_dq_30_io PADCELL_SIG_H + FIXED ( 5690000 1668000 ) W ;
423+
- u_ddr_dq_31_io PADCELL_SIG_H + FIXED ( 5690000 1580000 ) W ;
424424
- u_ddr_dq_3_io PADCELL_SIG_H + FIXED ( 30000 3210000 ) FW ;
425425
- u_ddr_dq_4_io PADCELL_SIG_H + FIXED ( 30000 3306000 ) FW ;
426426
- u_ddr_dq_5_io PADCELL_SIG_H + FIXED ( 30000 3356000 ) FW ;
@@ -430,28 +430,28 @@ COMPONENTS 543 ;
430430
- u_ddr_dq_9_io PADCELL_SIG_H + FIXED ( 30000 1780000 ) FW ;
431431
- u_ddr_dqs_n_0_io PADCELL_SIG_H + FIXED ( 30000 2716000 ) FW ;
432432
- u_ddr_dqs_n_1_io PADCELL_SIG_V + FIXED ( 444000 30000 ) N ;
433-
- u_ddr_dqs_n_2_io PADCELL_SIG_V + FIXED ( 5230000 30000 ) N ;
434-
- u_ddr_dqs_n_3_io PADCELL_SIG_H + FIXED ( 5690000 2842000 ) W ;
433+
- u_ddr_dqs_n_2_io PADCELL_SIG_V + FIXED ( 5228000 30000 ) N ;
434+
- u_ddr_dqs_n_3_io PADCELL_SIG_H + FIXED ( 5690000 2812000 ) W ;
435435
- u_ddr_dqs_p_0_io PADCELL_SIG_H + FIXED ( 30000 2420000 ) FW ;
436436
- u_ddr_dqs_p_1_io PADCELL_SIG_V + FIXED ( 628000 30000 ) N ;
437-
- u_ddr_dqs_p_2_io PADCELL_SIG_V + FIXED ( 5322000 30000 ) N ;
438-
- u_ddr_dqs_p_3_io PADCELL_SIG_H + FIXED ( 5690000 2930000 ) W ;
439-
- u_ddr_odt_o PADCELL_SIG_V + FIXED ( 3850000 30000 ) N ;
440-
- u_ddr_ras_n_o PADCELL_SIG_V + FIXED ( 4402000 30000 ) N ;
441-
- u_ddr_reset_n_o PADCELL_SIG_V + FIXED ( 3942000 30000 ) N ;
442-
- u_ddr_we_n_o PADCELL_SIG_V + FIXED ( 4034000 30000 ) N ;
437+
- u_ddr_dqs_p_2_io PADCELL_SIG_V + FIXED ( 5320000 30000 ) N ;
438+
- u_ddr_dqs_p_3_io PADCELL_SIG_H + FIXED ( 5690000 2900000 ) W ;
439+
- u_ddr_odt_o PADCELL_SIG_V + FIXED ( 3848000 30000 ) N ;
440+
- u_ddr_ras_n_o PADCELL_SIG_V + FIXED ( 4400000 30000 ) N ;
441+
- u_ddr_reset_n_o PADCELL_SIG_V + FIXED ( 3940000 30000 ) N ;
442+
- u_ddr_we_n_o PADCELL_SIG_V + FIXED ( 4032000 30000 ) N ;
443443
- u_misc_o PADCELL_SIG_V + FIXED ( 3420000 5690000 ) FS ;
444444
- u_sel_0_i PADCELL_SIG_V + FIXED ( 3470000 5690000 ) FS ;
445445
- u_sel_1_i PADCELL_SIG_V + FIXED ( 3640000 5690000 ) FS ;
446446
- u_sel_2_i PADCELL_SIG_V + FIXED ( 3790000 5690000 ) FS ;
447447
- u_v18_1 PADCELL_VDDIO_V + FIXED ( 1180000 30000 ) N ;
448-
- u_v18_10 PADCELL_VDDIO_H + FIXED ( 5690000 1506000 ) W ;
449-
- u_v18_11 PADCELL_VDDIO_H + FIXED ( 5690000 2040000 ) W ;
450-
- u_v18_12 PADCELL_VDDIO_H + FIXED ( 5690000 2752000 ) W ;
451-
- u_v18_13 PADCELL_VDDIO_H + FIXED ( 5690000 3286000 ) W ;
452-
- u_v18_14 PADCELL_VDDIO_H + FIXED ( 5690000 3998000 ) W ;
453-
- u_v18_15 PADCELL_VDDIO_H + FIXED ( 5690000 4532000 ) W ;
454-
- u_v18_16 PADCELL_VDDIO_H + FIXED ( 5690000 5066000 ) W ;
448+
- u_v18_10 PADCELL_VDDIO_H + FIXED ( 5690000 1492000 ) W ;
449+
- u_v18_11 PADCELL_VDDIO_H + FIXED ( 5690000 2020000 ) W ;
450+
- u_v18_12 PADCELL_VDDIO_H + FIXED ( 5690000 2724000 ) W ;
451+
- u_v18_13 PADCELL_VDDIO_H + FIXED ( 5690000 3252000 ) W ;
452+
- u_v18_14 PADCELL_VDDIO_H + FIXED ( 5690000 3956000 ) W ;
453+
- u_v18_15 PADCELL_VDDIO_H + FIXED ( 5690000 4484000 ) W ;
454+
- u_v18_16 PADCELL_VDDIO_H + FIXED ( 5690000 5012000 ) W ;
455455
- u_v18_17 PADCELL_VDDIO_V + FIXED ( 5290000 5690000 ) FS ;
456456
- u_v18_18 PADCELL_VDDIO_V + FIXED ( 4406000 5690000 ) FS ;
457457
- u_v18_19 PADCELL_VDDIO_V + FIXED ( 4090000 5690000 ) FS ;
@@ -471,11 +471,11 @@ COMPONENTS 543 ;
471471
- u_v18_31 PADCELL_VDDIO_H + FIXED ( 30000 2470000 ) FW ;
472472
- u_v18_32 PADCELL_VDDIO_H + FIXED ( 30000 2126000 ) FW ;
473473
- u_v18_4 PADCELL_VDDIO_V + FIXED ( 3020000 30000 ) N ;
474-
- u_v18_5 PADCELL_VDDIO_V + FIXED ( 3758000 30000 ) N ;
475-
- u_v18_6 PADCELL_VDDIO_V + FIXED ( 4310000 30000 ) N ;
476-
- u_v18_7 PADCELL_VDDIO_V + FIXED ( 4862000 30000 ) N ;
477-
- u_v18_8 PADCELL_VDDIO_V + FIXED ( 5598000 30000 ) N ;
478-
- u_v18_9 PADCELL_VDDIO_H + FIXED ( 5690000 972000 ) W ;
474+
- u_v18_5 PADCELL_VDDIO_V + FIXED ( 3756000 30000 ) N ;
475+
- u_v18_6 PADCELL_VDDIO_V + FIXED ( 4308000 30000 ) N ;
476+
- u_v18_7 PADCELL_VDDIO_V + FIXED ( 4860000 30000 ) N ;
477+
- u_v18_8 PADCELL_VDDIO_V + FIXED ( 5596000 30000 ) N ;
478+
- u_v18_9 PADCELL_VDDIO_H + FIXED ( 5690000 964000 ) W ;
479479
- u_vdd_1 PADCELL_VDD_V + FIXED ( 2008000 30000 ) N ;
480480
- u_vdd_10 PADCELL_VDD_H + FIXED ( 2636000 5690000 ) FS ;
481481
- u_vdd_11 PADCELL_VDD_H + FIXED ( 1526000 5690000 ) FS ;
@@ -487,7 +487,7 @@ COMPONENTS 543 ;
487487
- u_vdd_17 PADCELL_VDD_V ;
488488
- u_vdd_18 PADCELL_VDD_V ;
489489
- u_vdd_19 PADCELL_VDD_V ;
490-
- u_vdd_2 PADCELL_VDD_V + FIXED ( 3390000 30000 ) N ;
490+
- u_vdd_2 PADCELL_VDD_V + FIXED ( 3388000 30000 ) N ;
491491
- u_vdd_20 PADCELL_VDD_V ;
492492
- u_vdd_21 PADCELL_VDD_V ;
493493
- u_vdd_22 PADCELL_VDD_V ;
@@ -498,14 +498,14 @@ COMPONENTS 543 ;
498498
- u_vdd_27 PADCELL_VDD_H ;
499499
- u_vdd_28 PADCELL_VDD_H ;
500500
- u_vdd_29 PADCELL_VDD_H ;
501-
- u_vdd_3 PADCELL_VDD_V + FIXED ( 4954000 30000 ) N ;
501+
- u_vdd_3 PADCELL_VDD_V + FIXED ( 4952000 30000 ) N ;
502502
- u_vdd_30 PADCELL_VDD_H ;
503503
- u_vdd_31 PADCELL_VDD_H ;
504504
- u_vdd_32 PADCELL_VDD_H ;
505-
- u_vdd_4 PADCELL_VDD_V + FIXED ( 5690000 616000 ) W ;
506-
- u_vdd_5 PADCELL_VDD_V + FIXED ( 5690000 2218000 ) W ;
507-
- u_vdd_6 PADCELL_VDD_V + FIXED ( 5690000 3642000 ) W ;
508-
- u_vdd_7 PADCELL_VDD_V + FIXED ( 5690000 5244000 ) W ;
505+
- u_vdd_4 PADCELL_VDD_V + FIXED ( 5690000 612000 ) W ;
506+
- u_vdd_5 PADCELL_VDD_V + FIXED ( 5690000 2196000 ) W ;
507+
- u_vdd_6 PADCELL_VDD_V + FIXED ( 5690000 3604000 ) W ;
508+
- u_vdd_7 PADCELL_VDD_V + FIXED ( 5690000 5188000 ) W ;
509509
- u_vdd_8 PADCELL_VDD_H + FIXED ( 4726000 5690000 ) FS ;
510510
- u_vdd_9 PADCELL_VDD_H + FIXED ( 3890000 5690000 ) FS ;
511511
- u_vdd_pll PADCELL_VDD_V + FIXED ( 3250000 5690000 ) FS ;
@@ -521,7 +521,7 @@ COMPONENTS 543 ;
521521
- u_vss_17 PADCELL_VSS_V ;
522522
- u_vss_18 PADCELL_VSS_V ;
523523
- u_vss_19 PADCELL_VSS_V ;
524-
- u_vss_2 PADCELL_VSS_V + FIXED ( 3482000 30000 ) N ;
524+
- u_vss_2 PADCELL_VSS_V + FIXED ( 3480000 30000 ) N ;
525525
- u_vss_20 PADCELL_VSS_V ;
526526
- u_vss_21 PADCELL_VSS_V ;
527527
- u_vss_22 PADCELL_VSS_V ;
@@ -532,26 +532,26 @@ COMPONENTS 543 ;
532532
- u_vss_27 PADCELL_VSS_H ;
533533
- u_vss_28 PADCELL_VSS_H ;
534534
- u_vss_29 PADCELL_VSS_H ;
535-
- u_vss_3 PADCELL_VSS_V + FIXED ( 5046000 30000 ) N ;
535+
- u_vss_3 PADCELL_VSS_V + FIXED ( 5044000 30000 ) N ;
536536
- u_vss_30 PADCELL_VSS_H ;
537537
- u_vss_31 PADCELL_VSS_H ;
538538
- u_vss_32 PADCELL_VSS_H ;
539-
- u_vss_4 PADCELL_VSS_V + FIXED ( 5690000 706000 ) W ;
540-
- u_vss_5 PADCELL_VSS_V + FIXED ( 5690000 2308000 ) W ;
541-
- u_vss_6 PADCELL_VSS_V + FIXED ( 5690000 3732000 ) W ;
542-
- u_vss_7 PADCELL_VSS_V + FIXED ( 5690000 5334000 ) W ;
539+
- u_vss_4 PADCELL_VSS_V + FIXED ( 5690000 700000 ) W ;
540+
- u_vss_5 PADCELL_VSS_V + FIXED ( 5690000 2284000 ) W ;
541+
- u_vss_6 PADCELL_VSS_V + FIXED ( 5690000 3692000 ) W ;
542+
- u_vss_7 PADCELL_VSS_V + FIXED ( 5690000 5276000 ) W ;
543543
- u_vss_8 PADCELL_VSS_H + FIXED ( 4676000 5690000 ) FS ;
544544
- u_vss_9 PADCELL_VSS_H + FIXED ( 3840000 5690000 ) FS ;
545545
- u_vss_pll PADCELL_VSS_V + FIXED ( 3370000 5690000 ) FS ;
546546
- u_vzz_0 PADCELL_VSSIO_V + FIXED ( 536000 30000 ) N ;
547547
- u_vzz_1 PADCELL_VSSIO_V + FIXED ( 1088000 30000 ) N ;
548-
- u_vzz_10 PADCELL_VSSIO_H + FIXED ( 5690000 1418000 ) W ;
549-
- u_vzz_11 PADCELL_VSSIO_H + FIXED ( 5690000 1952000 ) W ;
550-
- u_vzz_12 PADCELL_VSSIO_H + FIXED ( 5690000 2664000 ) W ;
551-
- u_vzz_13 PADCELL_VSSIO_H + FIXED ( 5690000 3198000 ) W ;
552-
- u_vzz_14 PADCELL_VSSIO_H + FIXED ( 5690000 3910000 ) W ;
553-
- u_vzz_15 PADCELL_VSSIO_H + FIXED ( 5690000 4444000 ) W ;
554-
- u_vzz_16 PADCELL_VSSIO_H + FIXED ( 5690000 4978000 ) W ;
548+
- u_vzz_10 PADCELL_VSSIO_H + FIXED ( 5690000 1404000 ) W ;
549+
- u_vzz_11 PADCELL_VSSIO_H + FIXED ( 5690000 1932000 ) W ;
550+
- u_vzz_12 PADCELL_VSSIO_H + FIXED ( 5690000 2636000 ) W ;
551+
- u_vzz_13 PADCELL_VSSIO_H + FIXED ( 5690000 3164000 ) W ;
552+
- u_vzz_14 PADCELL_VSSIO_H + FIXED ( 5690000 3868000 ) W ;
553+
- u_vzz_15 PADCELL_VSSIO_H + FIXED ( 5690000 4396000 ) W ;
554+
- u_vzz_16 PADCELL_VSSIO_H + FIXED ( 5690000 4924000 ) W ;
555555
- u_vzz_17 PADCELL_VSSIO_V + FIXED ( 5340000 5690000 ) FS ;
556556
- u_vzz_18 PADCELL_VSSIO_V + FIXED ( 4456000 5690000 ) FS ;
557557
- u_vzz_19 PADCELL_VSSIO_V + FIXED ( 4140000 5690000 ) FS ;
@@ -571,11 +571,11 @@ COMPONENTS 543 ;
571571
- u_vzz_31 PADCELL_VSSIO_H + FIXED ( 30000 2520000 ) FW ;
572572
- u_vzz_32 PADCELL_VSSIO_H + FIXED ( 30000 2176000 ) FW ;
573573
- u_vzz_4 PADCELL_VSSIO_V + FIXED ( 2928000 30000 ) N ;
574-
- u_vzz_5 PADCELL_VSSIO_V + FIXED ( 3666000 30000 ) N ;
575-
- u_vzz_6 PADCELL_VSSIO_V + FIXED ( 4218000 30000 ) N ;
576-
- u_vzz_7 PADCELL_VSSIO_V + FIXED ( 4770000 30000 ) N ;
577-
- u_vzz_8 PADCELL_VSSIO_V + FIXED ( 5506000 30000 ) N ;
578-
- u_vzz_9 PADCELL_VSSIO_H + FIXED ( 5690000 884000 ) W ;
574+
- u_vzz_5 PADCELL_VSSIO_V + FIXED ( 3664000 30000 ) N ;
575+
- u_vzz_6 PADCELL_VSSIO_V + FIXED ( 4216000 30000 ) N ;
576+
- u_vzz_7 PADCELL_VSSIO_V + FIXED ( 4768000 30000 ) N ;
577+
- u_vzz_8 PADCELL_VSSIO_V + FIXED ( 5504000 30000 ) N ;
578+
- u_vzz_9 PADCELL_VSSIO_H + FIXED ( 5690000 876000 ) W ;
579579
END COMPONENTS
580580
PINS 135 ;
581581
- p_bsg_tag_clk_i + NET p_bsg_tag_clk_i + SPECIAL + DIRECTION INPUT + USE SIGNAL

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