cgt: use pimpl to simplify the public interface

Signed-off-by: Matt Liberty <[email protected]>

Author: maliberty

src/cgt/include/cgt/ClockGating.h

@@ -3,48 +3,13 @@
 
 #pragma once
 
-#include <cstddef>
-#include <filesystem>
 #include <memory>
-#include <optional>
-#include <string>
-#include <vector>
 
-#include "cgt/NetworkBuilder.h"
-#include "cgt/RandomBits.h"
 #include "db_sta/dbSta.hh"
-#include "utl/deleter.h"
-#include "utl/unique_name.h"
-
-namespace abc {
-using Abc_Ntk_t = struct Abc_Ntk_t_;
-using Abc_Obj_t = struct Abc_Obj_t_;
-using Vec_Ptr_t = struct Vec_Ptr_t_;
-}  // namespace abc
-
-namespace utl {
-class Logger;
-}
-
-namespace odb {
-class dbDatabase;
-}  // namespace odb
-
-namespace sta {
-class dbSta;
-}  // namespace sta
-
-namespace cut {
-
-class AbcLibrary;
-class AbcLibraryFactory;
-
-}  // namespace cut
+#include "utl/Logger.h"
 
 namespace cgt {
 
-using utl::Logger;
-
 class ClockGating
 {
  public:
@@ -54,97 +19,13 @@ class ClockGating
   // Main function that performs the clock gating process
   void run();
 
-  void setMinInstances(size_t min_instances) { min_instances_ = min_instances; }
-  void setMaxCover(size_t max_cover) { max_cover_ = max_cover; }
+  void setMinInstances(int min_instances);
+  void setMaxCover(int max_cover);
   void setDumpDir(const char* dir);
 
  private:
-  // Searches for a minimal set of nets that can form a gating condition for the
-  // given instances. The given range of candidate nets (begin-end) is divided
-  // in two. If the first half can form a gating condition, the second half is
-  // dropped from the list. Otherwise, the second half is recursed into.
-  // Finally, the first half is recursed into.
-  void searchClockGates(sta::Instance* instance,
-                        std::vector<sta::Net*>& good_gate_conds,
-                        std::vector<sta::Net*>::iterator begin,
-                        std::vector<sta::Net*>::iterator end,
-                        abc::Abc_Ntk_t& abc_network_ref,
-                        bool clk_enable);
-  // Exports a part of the network that contains the given instances and nets to
-  // ABC.
-  utl::UniquePtrWithDeleter<abc::Abc_Ntk_t> exportToAbc(
-      sta::Instance* instance,
-      const std::vector<sta::Net*>& nets);
-  // Constructs an ABC network that will be used for testing if the given nets
-  // are correct gating conditions.
-  utl::UniquePtrWithDeleter<abc::Abc_Ntk_t> makeTestNetwork(
-      sta::Instance* instance,
-      const std::vector<sta::Net*>& gate_cond_nets,
-      abc::Abc_Ntk_t& abc_network_ref,
-      bool clk_enable);
-  // Performs a random simulation test on the given network and returns true if
-  // no counterexample for the given gating conditions was found.
-  bool simulationTest(abc::Abc_Ntk_t* abc_network,
-                      const std::string& combined_gate_name);
-  // Performs a SAT test on the given network and returns true if it is NOT
-  // satisfiable (the given nets are correct gating conditions).
-  bool satTest(abc::Abc_Ntk_t* abc_network,
-               const std::string& combined_gate_name);
-  // Returns true if the given gating conditions are correct for the given
-  // clocked instances.
-  bool isCorrectClockGate(sta::Instance* instance,
-                          const std::vector<sta::Net*>& gate_cond_nets,
-                          abc::Abc_Ntk_t& abc_network,
-                          bool clk_enable);
-  // Inserts a clock gate for the given clocked instances with the given gating
-  // conditions into the network.
-  void insertClockGate(const std::vector<sta::Instance*>& instances,
-                       const std::vector<sta::Net*>& gate_cond_nets,
-                       bool clk_enable);
-
-  void dump(const char* name);
-  void dumpAbc(const char* name, abc::Abc_Ntk_t* network);
-
-  std::filesystem::path getNetworkGraphvizDumpPath(const char* name);
-  std::filesystem::path getAbcGraphvizDumpPath(const char* name);
-  std::filesystem::path getAbcVerilogDumpPath(const char* name);
-  std::filesystem::path getDumpDir();
-
-  // Minimum number of instances that should be gated by one clock gate.
-  size_t min_instances_ = 10;
-  // Maximum number of nets that form the initial gating condition set for each
-  // instance.
-  size_t max_cover_ = 100;
-
-  // Path where dump files should be created.
-  std::optional<std::filesystem::path> dump_dir_;
-
-  // Debug counters and run time measurements
-  size_t dump_counter_ = 0;
-  size_t rejected_sim_count_ = 0;
-  size_t rejected_sat_count_ = 0;
-  size_t accepted_count_ = 0;
-  double reuse_check_time_ = 0;
-  double search_time_ = 0;
-  double exist_check_time_ = 0;
-  double network_export_time_ = 0;
-  double network_build_time_ = 0;
-  double sim_time_ = 0;
-  double sat_time_ = 0;
-
-  // For unique instance names
-  utl::UniqueName unique_name_cond_;
-  utl::UniqueName unique_name_cond_not_;
-  utl::UniqueName unique_name_gate_;
-  // Generates random bits (for random simulation).
-  RandomBits rand_bits_;
-  // Helper for inserting new instances/nets into a network.
-  NetworkBuilder network_builder_;
-
-  Logger* logger_ = nullptr;
-  sta::dbSta* sta_ = nullptr;
-  std::unique_ptr<cut::AbcLibraryFactory> abc_factory_;
-  std::unique_ptr<cut::AbcLibrary> abc_library_;
+  class Impl;
+  std::unique_ptr<Impl> impl_;
 };
 
 }  // namespace cgt

src/cgt/src/ClockGating.cpp

@@ -19,6 +19,7 @@
 #include <utility>
 #include <vector>
 
+#include "ClockGatingImpl.h"
 #include "base/abc/abc.h"
 #include "base/io/ioAbc.h"
 #include "base/main/abcapis.h"
@@ -63,14 +64,42 @@ extern void Abc_FrameSetLibGen(void* pLib);
 
 namespace cgt {
 
-ClockGating::ClockGating(utl::Logger* const logger, sta::dbSta* const sta)
+ClockGating::ClockGating(utl::Logger* logger, sta::dbSta* open_sta)
+  : impl_(std::make_unique<Impl>(logger, open_sta))
+{
+}
+
+ClockGating::~ClockGating() = default;
+
+void ClockGating::run()
+{
+  impl_->run();
+}
+
+void ClockGating::setMinInstances(int min_instances)
+{
+  impl_->setMinInstances(min_instances);
+}
+
+void ClockGating::setMaxCover(int max_cover)
+{
+  impl_->setMaxCover(max_cover);
+}
+
+void ClockGating::setDumpDir(const char* dir)
+{
+}
+
+//////////////////////////////////////////////////
+
+ClockGating::Impl::Impl(utl::Logger* const logger, sta::dbSta* const sta)
     : logger_(logger),
       sta_(sta),
       abc_factory_(std::make_unique<cut::AbcLibraryFactory>(logger_))
 {
 }
 
-ClockGating::~ClockGating() = default;
+ClockGating::Impl::~Impl() = default;
 
 // Dumps the given network as GraphViz.
 static void dumpGraphviz(sta::dbNetwork* const network,
@@ -204,7 +233,7 @@ static sta::Pin* getClockPin(sta::dbNetwork* const network,
   return nullptr;
 }
 
-void ClockGating::setDumpDir(const char* const dir)
+void ClockGating::Impl::setDumpDir(const char* const dir)
 {
   if (*dir == '\0') {
     return;
@@ -343,7 +372,7 @@ static std::string combinedInstanceNames(
   return result;
 }
 
-void ClockGating::run()
+void ClockGating::Impl::run()
 {
   debugPrint(logger_,
              CGT,
@@ -387,7 +416,7 @@ void ClockGating::run()
       if (!cell) {
         continue;
       }
-      size_t num_regs
+      int num_regs
           = std::count_if(cell->sequentials().begin(),
                           cell->sequentials().end(),
                           [](const auto* seq) { return seq->isRegister(); });
@@ -403,13 +432,13 @@ void ClockGating::run()
     delete inst_iter;
   }
 
-  using AcceptedIndex = size_t;
+  using AcceptedIndex = int;
   std::unordered_map<sta::Net*, std::vector<AcceptedIndex>> net_to_accepted;
   std::vector<
       std::tuple<std::vector<sta::Net*>, std::vector<sta::Instance*>, bool>>
       accepted_gates;
 
-  for (size_t i = 0; i < instances.size(); i++) {
+  for (int i = 0; i < instances.size(); i++) {
     auto instance = instances[i];
     if (i % 100 == 0) {
       logger_->info(CGT, 3, "Clock gating instance {}/{}", i, instances.size());
@@ -650,14 +679,14 @@ static std::vector<sta::Net*> except(
   return result;
 }
 
-void ClockGating::searchClockGates(sta::Instance* const instance,
+void ClockGating::Impl::searchClockGates(sta::Instance* const instance,
                                    std::vector<sta::Net*>& good_gate_conds,
                                    const std::vector<sta::Net*>::iterator begin,
                                    const std::vector<sta::Net*>::iterator end,
                                    abc::Abc_Ntk_t& abc_network,
                                    const bool clk_enable)
 {
-  size_t half_len = (end - begin) / 2;
+  int half_len = (end - begin) / 2;
   if (half_len == 0) {
     return;
   }
@@ -915,7 +944,7 @@ static abc::Abc_Obj_t* regDataFunctionToAbc(sta::dbNetwork* const network,
   return obj_stack.back();
 }
 
-utl::UniquePtrWithDeleter<abc::Abc_Ntk_t> ClockGating::makeTestNetwork(
+utl::UniquePtrWithDeleter<abc::Abc_Ntk_t> ClockGating::Impl::makeTestNetwork(
     sta::Instance* const instance,
     const std::vector<sta::Net*>& gate_cond_nets,
     abc::Abc_Ntk_t& abc_network_ref,
@@ -1075,7 +1104,7 @@ utl::UniquePtrWithDeleter<abc::Abc_Ntk_t> ClockGating::makeTestNetwork(
   }
 }
 
-bool ClockGating::simulationTest(abc::Abc_Ntk_t* const abc_network,
+bool ClockGating::Impl::simulationTest(abc::Abc_Ntk_t* const abc_network,
                                  const std::string& combined_gate_name)
 {
   DebugScopedTimer timer(
@@ -1114,7 +1143,7 @@ bool ClockGating::simulationTest(abc::Abc_Ntk_t* const abc_network,
   return true;
 }
 
-bool ClockGating::satTest(abc::Abc_Ntk_t* const abc_network,
+bool ClockGating::Impl::satTest(abc::Abc_Ntk_t* const abc_network,
                           const std::string& combined_gate_name)
 {
   DebugScopedTimer timer(
@@ -1145,7 +1174,7 @@ bool ClockGating::satTest(abc::Abc_Ntk_t* const abc_network,
   return true;
 }
 
-bool ClockGating::isCorrectClockGate(
+bool ClockGating::Impl::isCorrectClockGate(
     sta::Instance* const instance,
     const std::vector<sta::Net*>& gate_cond_nets,
     abc::Abc_Ntk_t& abc_network_ref,
@@ -1186,7 +1215,7 @@ bool ClockGating::isCorrectClockGate(
   return true;
 }
 
-void ClockGating::insertClockGate(const std::vector<sta::Instance*>& instances,
+void ClockGating::Impl::insertClockGate(const std::vector<sta::Instance*>& instances,
                                   const std::vector<sta::Net*>& gate_cond_nets,
                                   const bool clk_enable)
 {
@@ -1206,7 +1235,7 @@ void ClockGating::insertClockGate(const std::vector<sta::Instance*>& instances,
   std::vector<sta::Instance*> new_instances;
 
   auto gate_cond_net = gate_cond_nets[0];
-  for (size_t i = 1; i < gate_cond_nets.size(); i++) {
+  for (int i = 1; i < gate_cond_nets.size(); i++) {
     auto inst_name = unique_name_cond_.GetUniqueName("clk_gate_cond_");
     auto inst_builder = clk_enable ? network_builder_.makeOr(inst_name)
                                    : network_builder_.makeAnd(inst_name);
@@ -1227,7 +1256,7 @@ void ClockGating::insertClockGate(const std::vector<sta::Instance*>& instances,
   assert(clk_pin);
   auto clk_net = network->net(clk_pin);
   auto clocks = network->clkNetwork()->clocks(clk_pin);
-  for (size_t i = 1; i < instances.size(); i++) {
+  for (int i = 1; i < instances.size(); i++) {
     auto clk_pin = getClockPin(network, instances[i]);
     assert(clk_pin);
     if (*sta_->clkNetwork()->clocks(clk_pin) != *clocks) {
@@ -1274,7 +1303,7 @@ void ClockGating::insertClockGate(const std::vector<sta::Instance*>& instances,
   }
 }
 
-UniquePtrWithDeleter<abc::Abc_Ntk_t> ClockGating::exportToAbc(
+UniquePtrWithDeleter<abc::Abc_Ntk_t> ClockGating::Impl::exportToAbc(
     sta::Instance* const instance,
     const std::vector<sta::Net*>& nets)
 {
@@ -1346,7 +1375,7 @@ UniquePtrWithDeleter<abc::Abc_Ntk_t> ClockGating::exportToAbc(
   return abc_network;
 }
 
-void ClockGating::dump(const char* const name)
+void ClockGating::Impl::dump(const char* const name)
 {
   if (!dump_dir_) {
     return;
@@ -1358,7 +1387,7 @@ void ClockGating::dump(const char* const name)
   dump_counter_++;
 }
 
-void ClockGating::dumpAbc(const char* const name, abc::Abc_Ntk_t* const network)
+void ClockGating::Impl::dumpAbc(const char* const name, abc::Abc_Ntk_t* const network)
 {
   if (!dump_dir_) {
     return;
@@ -1386,26 +1415,26 @@ void ClockGating::dumpAbc(const char* const name, abc::Abc_Ntk_t* const network)
   dump_counter_++;
 }
 
-std::filesystem::path ClockGating::getNetworkGraphvizDumpPath(
+std::filesystem::path ClockGating::Impl::getNetworkGraphvizDumpPath(
     const char* const name)
 {
   return getDumpDir()
          / (std::to_string(dump_counter_) + "_openroad_" + name + ".dot");
 }
 
-std::filesystem::path ClockGating::getAbcGraphvizDumpPath(
+std::filesystem::path ClockGating::Impl::getAbcGraphvizDumpPath(
     const char* const name)
 {
   return getDumpDir()
          / (std::to_string(dump_counter_) + "_abc_" + name + ".dot");
 }
 
-std::filesystem::path ClockGating::getAbcVerilogDumpPath(const char* const name)
+std::filesystem::path ClockGating::Impl::getAbcVerilogDumpPath(const char* const name)
 {
   return getDumpDir() / (std::to_string(dump_counter_) + "_abc_" + name + ".v");
 }
 
-std::filesystem::path ClockGating::getDumpDir()
+std::filesystem::path ClockGating::Impl::getDumpDir()
 {
   if (dump_dir_) {
     return *dump_dir_;