Merge remote-tracking branch 'origin/master' into odb-database-chip

Author: osamahammad21

WORKSPACE

@@ -8,9 +8,9 @@ workspace(name = "openroad")
 
 load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive")
 
-rules_hdl_git_hash = "80266603b55778dd30531c9b286152a7b664fbb7"
+rules_hdl_git_hash = "56da46a87e8e5a4dbe84c0bbe5d00e92b936494f"
 
-rules_hdl_git_sha256 = "38f04d38cfbf46c52643325b496673d607ce5ea6fda99dc1dfa3997a520bb0c2"
+rules_hdl_git_sha256 = "dc184ad0fe92f315eb5600fb3293c94ce1fce3fc1d0fd79400107038ed917d70"
 
 http_archive(
     name = "rules_hdl",

src/Metrics.tcl

@@ -36,7 +36,6 @@ proc report_tns_metric { args } {
 
 define_cmd_args "report_worst_slack_metric" {[-setup]|[-hold]}
 proc report_worst_slack_metric { args } {
-  global sta_report_default_digits
   parse_key_args "report_worst_slack_metric" args keys {} flags {-setup -hold}
 
   set min_max "-max"
@@ -53,7 +52,6 @@ proc report_worst_slack_metric { args } {
 
 define_cmd_args "report_worst_negative_slack_metric" {[-setup]|[-hold]}
 proc report_worst_negative_slack_metric { args } {
-  global sta_report_default_digits
   parse_key_args "report_worst_negative_slack_metric" args keys {} flags {-setup -hold}
 
   set min_max "-max"
@@ -68,6 +66,51 @@ proc report_worst_negative_slack_metric { args } {
   utl::metric_float $metric_name [worst_negative_slack $min_max]
 }
 
+define_cmd_args "report_fmax_metric" {}
+proc report_fmax_metric { args } {
+  parse_key_args "report_fmax_metric" args keys {} flags {}
+
+  # Taken from: https://github.com/siliconcompiler/siliconcompiler/blob/e46c702df218c93483b951533fe00bcf01cf772d/siliconcompiler/tools/openroad/scripts/common/reports.tcl#L98
+  # Modeled on: https://github.com/The-OpenROAD-Project/OpenSTA/blob/f913c3ddbb3e7b4364ed4437c65ac78c4da9174b/tcl/Search.tcl#L1078
+  set fmax_metric 0
+  foreach clk [sta::sort_by_name [all_clocks]] {
+    set clk_name [get_name $clk]
+    set min_period [sta::find_clk_min_period $clk 1]
+    if { $min_period == 0.0 } {
+      continue
+    }
+    set fmax [expr { 1.0 / $min_period }]
+    utl::metric_float "timing__fmax__clock:${clk_name}" $fmax
+    puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
+    set fmax_metric [expr { max($fmax_metric, $fmax) }]
+  }
+  if { $fmax_metric == 0 } {
+    # attempt to compute based on combinatorial path
+    set fmax_valid true
+    set max_path [find_timing_paths -unconstrained -path_delay max]
+    if { $max_path == "" } {
+      set fmax_valid false
+    } else {
+      set max_path_delay [$max_path data_arrival_time]
+    }
+    set min_path [find_timing_paths -unconstrained -path_delay min]
+    if { $min_path == "" } {
+      set fmax_valid false
+    } else {
+      set min_path_delay [$min_path data_arrival_time]
+    }
+    if { $fmax_valid } {
+      set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
+      if { $path_delay > 0 } {
+        set fmax_metric [expr { 1.0 / $path_delay }]
+      }
+    }
+  }
+  if { $fmax_metric > 0 } {
+    utl::metric_float "timing__fmax" $fmax_metric
+  }
+}
+
 # From https://wiki.tcl-lang.org/page/Inf
 proc ::tcl::mathfunc::finite { x } {
   expr { [string is double -strict $x] && $x == $x && $x + 1 != $x }

src/ant/src/AntennaChecker.cc

@@ -205,6 +205,9 @@ void AntennaChecker::saveGates(odb::dbNet* db_net,
 {
   std::map<PinType, std::vector<int>, PinTypeCmp> pin_nbrs;
   std::vector<int> ids;
+  // struct to save pin polygons
+  using LayerAndPin = std::pair<int, PinType>;
+  std::vector<LayerAndPin> pin_polys;
   // iterate all instance pins
   for (odb::dbITerm* iterm : db_net->getITerms()) {
     odb::dbMTerm* mterm = iterm->getMTerm();
@@ -229,6 +232,8 @@ void AntennaChecker::saveGates(odb::dbNet* db_net,
         transform.apply(pin_rect);
         // convert rect -> polygon
         Polygon pin_pol = rectToPolygon(pin_rect);
+        // Save polygon to add on DSU
+        pin_polys.emplace_back(tech_layer->getRoutingLevel(), pin);
         // if has wire on same layer connect to pin
         ids = findNodesWithIntersection(node_by_layer_map[tech_layer], pin_pol);
         for (const int& index : ids) {
@@ -253,6 +258,13 @@ void AntennaChecker::saveGates(odb::dbNet* db_net,
       }
     }
   }
+  // Sort pin polygon based by layer level (greatest first)
+  std::sort(pin_polys.begin(),
+            pin_polys.end(),
+            [](const LayerAndPin& a, const LayerAndPin& b) {
+              return a.first > b.first;
+            });
+
   // run DSU from min_layer to max_layer
   std::vector<int> dsu_parent(node_count);
   std::vector<int> dsu_size(node_count);
@@ -267,12 +279,30 @@ void AntennaChecker::saveGates(odb::dbNet* db_net,
   odb::dbTechLayer* iter = tech->findRoutingLayer(1);
   odb::dbTechLayer* lower_layer;
   while (iter) {
-    // iterate each node of this layer to union set
-    for (auto& node_it : node_by_layer_map[iter]) {
-      int id_u = node_it->id;
-      // if has lower layer
-      lower_layer = iter->getLowerLayer();
-      if (lower_layer) {
+    // Get lower layer
+    lower_layer = iter->getLowerLayer();
+    if (lower_layer) {
+      // Check only vias layer to add pin connections
+      if (lower_layer->getRoutingLevel() != 0) {
+        int layer_level = lower_layer->getRoutingLevel();
+        // only include pin on layer below to the current
+        while (!pin_polys.empty() && layer_level >= pin_polys.back().first) {
+          PinType pin = pin_polys.back().second;
+          int last_id = -1;
+          pin_polys.pop_back();
+          // Set union of all wires connected to pin
+          for (const int& nbr_id : pin_nbrs[pin]) {
+            if (last_id != -1
+                && dsu.find_set(last_id) != dsu.find_set(nbr_id)) {
+              dsu.union_set(last_id, nbr_id);
+            }
+            last_id = nbr_id;
+          }
+        }
+      }
+      // iterate each node of this layer to union set
+      for (auto& node_it : node_by_layer_map[iter]) {
+        int id_u = node_it->id;
         // get lower neighbors and union
         for (const int& lower_it : node_it->low_adj) {
           int id_v = node_by_layer_map[lower_layer][lower_it]->id;

src/cts/src/TritonCTS.cpp

@@ -1238,9 +1238,20 @@ bool TritonCTS::separateMacroRegSinks(
     }
 
     if (iterm->isInputSignal() && inst->isPlaced()) {
+      // Cells with insertion delay, macros, clock gaters and inverters that
+      // drive macros are put in the macro sinks.
       odb::dbMTerm* mterm = iterm->getMTerm();
-      // Treat clock gaters like macro sink
-      if (hasInsertionDelay(inst, mterm) || !isSink(iterm) || inst->isBlock()) {
+
+      bool nonSinkMacro = !isSink(iterm);
+      sta::Cell* masterCell = network_->dbToSta(mterm->getMaster());
+      sta::LibertyCell* libertyCell = network_->libertyCell(masterCell);
+      if (libertyCell && libertyCell->isInverter()) {
+        odb::dbITerm* invertedTerm
+            = inst->getFirstOutput()->getNet()->get1stSignalInput(false);
+        nonSinkMacro &= invertedTerm->getInst()->isBlock();
+      }
+
+      if (hasInsertionDelay(inst, mterm) || nonSinkMacro || inst->isBlock()) {
         macroSinks.emplace_back(inst, mterm);
       } else {
         registerSinks.emplace_back(inst, mterm);

src/cts/test/CMakeLists.txt

@@ -27,6 +27,7 @@ or_integration_tests(
     find_clock_pad
     hier_insertion_delay
     insertion_delay
+    inverters
     lvt_lib
     max_cap
     no_clocks