Merge pull request #8322 from The-OpenROAD-Project-staging/secure-fix-remove-cells

Added all LibertyCells into dbNetwork::concrete_cells_

Author: maliberty

src/dbSta/include/db_sta/dbNetwork.hh

@@ -267,7 +267,8 @@ class dbNetwork : public ConcreteNetwork
                     const std::string& value) override;
 
   bool isConcreteCell(const Cell*) const;
-  void registerConcreteCell(const Cell*);
+  void registerHierModule(const Cell* cell);
+  void unregisterHierModule(const Cell* cell);
 
   ////////////////////////////////////////////////////////////////
   // Port functions
@@ -425,7 +426,7 @@ class dbNetwork : public ConcreteNetwork
 
  private:
   bool hierarchy_ = false;
-  std::set<const Cell*> concrete_cells_;
+  std::set<const Cell*> hier_modules_;
   std::set<const Port*> concrete_ports_;
   std::unique_ptr<dbEditHierarchy> hierarchy_editor_;
 };

src/dbSta/include/db_sta/dbReadVerilog.hh

@@ -41,6 +41,7 @@ class dbVerilogNetwork : public ConcreteNetwork
   Cell* findAnyCell(const char* name) override;
   void init(dbNetwork* db_network);
   bool isBlackBox(ConcreteCell* cell);
+  dbNetwork* getDbNetwork() { return static_cast<dbNetwork*>(db_network_); }
 
  private:
   NetworkReader* db_network_ = nullptr;

src/dbSta/src/dbNetwork.cc

@@ -2038,6 +2038,14 @@ void dbNetwork::readDbAfter(odb::dbDatabase* db)
     for (dbLib* lib : db_->getLibs()) {
       makeLibrary(lib);
     }
+
+    for (dbModule* module : block_->getModules()) {
+      // top_module is not a hierarchical module in this context.
+      if (module != block_->getTopModule()) {
+        registerHierModule(dbToSta(module));
+      }
+    }
+
     readDbNetlistAfter();
   }
 
@@ -2062,7 +2070,6 @@ void dbNetwork::makeCell(Library* library, dbMaster* master)
   master->staSetCell(reinterpret_cast<void*>(cell));
   // keep track of db leaf cells. These are cells for which we
   // use the concrete network.
-  registerConcreteCell(cell);
   ConcreteCell* ccell = reinterpret_cast<ConcreteCell*>(cell);
   ccell->setExtCell(reinterpret_cast<void*>(master));
 
@@ -2308,7 +2315,6 @@ Instance* dbNetwork::makeInstance(LibertyCell* cell,
       // to get timing characteristics, so they have to be
       // concrete
       Cell* inst_cell = dbToSta(master);
-      registerConcreteCell(inst_cell);
       std::unique_ptr<sta::CellPortIterator> port_iter{portIterator(inst_cell)};
       while (port_iter->hasNext()) {
         Port* cur_port = port_iter->next();
@@ -2326,13 +2332,12 @@ Instance* dbNetwork::makeInstance(LibertyCell* cell,
       dbInst* inst = dbInst::create(block_, master, name, false, parent);
       Cell* inst_cell = dbToSta(master);
       //
-      // Register all liberty cells as being concrete
+      // Register all ports of liberty cells as being concrete
       // Sometimes this method is called by the sta
       // to build "test circuits" eg to find the max wire length
       // And those cells need to use the external api
       // to get timing characteristics, so they have to be
       // concrete
-      registerConcreteCell(inst_cell);
       std::unique_ptr<sta::CellPortIterator> port_iter{portIterator(inst_cell)};
       while (port_iter->hasNext()) {
         Port* cur_port = port_iter->next();
@@ -3193,6 +3198,16 @@ LibertyPort* dbNetwork::libertyPort(const Pin* pin) const
   return nullptr;
 }
 
+void dbNetwork::registerHierModule(const Cell* cell)
+{
+  hier_modules_.insert(cell);
+}
+
+void dbNetwork::unregisterHierModule(const Cell* cell)
+{
+  hier_modules_.erase(cell);
+}
+
 /*
 We keep a registry of the concrete cells.
 For these we know to use the concrete network interface.
@@ -3201,18 +3216,17 @@ The concrete cells are created outside of the odb world
 So we simply note them and then when we inspect a cell
 we can decide whether or not to use the ConcreteNetwork api.
 */
-
-void dbNetwork::registerConcreteCell(const Cell* cell)
-{
-  concrete_cells_.insert(cell);
-}
-
 bool dbNetwork::isConcreteCell(const Cell* cell) const
 {
   if (!hierarchy_) {
     return true;
   }
-  return (concrete_cells_.find(cell) != concrete_cells_.end());
+
+  if (cell == top_cell_) {
+    return false;
+  }
+
+  return (hier_modules_.find(cell) == hier_modules_.end());
 }
 
 void dbNetwork::registerConcretePort(const Port* port)

src/dbSta/src/dbReadVerilog.cc

@@ -170,6 +170,7 @@ class Verilog2db
   void makeChildInsts(Instance* inst, dbModule* module, InstPairs& inst_pairs);
   void makeModBTerms(Cell* cell, dbModule* module);
   void makeModITerms(Instance* inst, dbModInst* modinst);
+  void registerHierModule(dbModule* module);
   dbIoType staToDb(PortDirection* dir);
   bool staToDb(dbModule* module,
                const Pin* pin,
@@ -390,6 +391,8 @@ void Verilog2db::makeDbModule(
     module = dbModule::makeUniqueDbModule(
         network_->name(cell), network_->name(inst), block_);
 
+    registerHierModule(module);
+
     std::string module_inst_name = network_->name(inst);
 
     dbModInst* modinst
@@ -433,6 +436,14 @@ void Verilog2db::makeDbModule(
   makeChildInsts(inst, module, inst_pairs);
 }
 
+void Verilog2db::registerHierModule(dbModule* module)
+{
+  // Register the module as a hierarchical module in the dbNetwork.
+  dbNetwork* db_network
+      = static_cast<dbVerilogNetwork*>(network_)->getDbNetwork();
+  db_network->registerHierModule(db_network->dbToSta(module));
+}
+
 void Verilog2db::makeModBTerms(Cell* cell, dbModule* module)
 {
   dbBusPort* dbbusport = nullptr;

src/dbSta/src/dbSta.cc

@@ -156,6 +156,8 @@ class dbStaCbk : public dbBlockCallBackObj
   void setNetwork(dbNetwork* network);
   void inDbInstCreate(dbInst* inst) override;
   void inDbInstDestroy(dbInst* inst) override;
+  void inDbModuleCreate(dbModule* module) override;
+  void inDbModuleDestroy(dbModule* module) override;
   void inDbInstSwapMasterBefore(dbInst* inst, dbMaster* master) override;
   void inDbInstSwapMasterAfter(dbInst* inst) override;
   void inDbNetDestroy(dbNet* net) override;
@@ -928,6 +930,16 @@ void dbStaCbk::inDbInstDestroy(dbInst* inst)
   sta_->deleteLeafInstanceBefore(network_->dbToSta(inst));
 }
 
+void dbStaCbk::inDbModuleCreate(dbModule* module)
+{
+  network_->registerHierModule(network_->dbToSta(module));
+}
+
+void dbStaCbk::inDbModuleDestroy(dbModule* module)
+{
+  network_->unregisterHierModule(network_->dbToSta(module));
+}
+
 void dbStaCbk::inDbInstSwapMasterBefore(dbInst* inst, dbMaster* master)
 {
   LibertyCell* to_lib_cell = network_->libertyCell(network_->dbToSta(master));

src/dbSta/test/BUILD

@@ -58,6 +58,8 @@ COMPULSORY_TESTS = [
     "write_verilog6",
     "write_verilog7",
     "write_verilog8",
+    "write_verilog9",
+    "write_verilog9_hier",
 ]
 
 ALL_TESTS = COMPULSORY_TESTS
@@ -134,6 +136,7 @@ filegroup(
         "reg5.v",
         "reg6.def",
         "report_cell_usage_no_taps.def",
+        "write_verilog9.v",
     ],
 )
 

src/dbSta/test/CMakeLists.txt

@@ -55,6 +55,8 @@ or_integration_tests(
     write_verilog6
     write_verilog7
     write_verilog8
+    write_verilog9
+    write_verilog9_hier
 )
 
 if(ENABLE_TESTS)

src/dbSta/test/write_verilog9.ok

@@ -0,0 +1,8 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+module top (in1,
+    out1);
+ input in1;
+ output out1;
+
+
+endmodule

src/dbSta/test/write_verilog9.tcl

@@ -0,0 +1,10 @@
+# Test write_verilog -remove_cells in a flat flow
+source "helpers.tcl"
+read_lef Nangate45/Nangate45.lef
+read_liberty Nangate45/Nangate45_typ.lib
+read_verilog write_verilog9.v
+link_design top
+
+set verilog_file [make_result_file write_verilog9.v]
+write_verilog -remove_cells BUF* $verilog_file
+report_file $verilog_file

src/dbSta/test/write_verilog9.v

@@ -0,0 +1,9 @@
+module top (in1,
+    out1);
+ input in1;
+ output out1;
+
+
+ BUF_X1 u1 (.A(in1),
+    .Z(out1));
+endmodule