added missing SDC flie for one test

Signed-off-by: Cho Moon <[email protected]>

Author: precisionmoon

src/rsz/test/gcd.sdc

@@ -0,0 +1,15 @@
+current_design gcd
+
+set clk_name core_clock
+set clk_port_name clk
+set clk_period 220
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]