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Merge pull request #8306 from The-OpenROAD-Project-staging/cts-enable-ndr-default
cts: enable NDR for clock nets by default
2 parents 33d94a4 + 2ef3d3a commit a64d3a6

11 files changed

+124
-83
lines changed

‎src/cts/src/CtsOptions.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -350,7 +350,7 @@ class CtsOptions : public odb::dbBlockCallBackObj
350350
std::string dummyload_prefix_ = "clkload";
351351
MasterCount dummy_count_;
352352
bool repairClockNets_ = false;
353-
NdrStrategy ndrStrategy_ = NdrStrategy::NONE;
353+
NdrStrategy ndrStrategy_ = NdrStrategy::HALF;
354354
};
355355

356356
} // namespace cts

‎src/cts/src/TritonCTS.cpp‎

Lines changed: 22 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1582,7 +1582,7 @@ std::vector<int> TritonCTS::getAllClockTreeLevels(Clock& clockNet)
15821582
std::set<int> uniqueLevels;
15831583

15841584
clockNet.forEachSubNet([&](ClockSubNet& subNet) {
1585-
if (!subNet.isLeafLevel()) {
1585+
if (!subNet.isLeafLevel() && subNet.getTreeLevel() != -1) {
15861586
uniqueLevels.insert(subNet.getTreeLevel());
15871587
}
15881588
});
@@ -1704,13 +1704,19 @@ void TritonCTS::writeClockNDRsToDb(TreeBuilder* builder)
17041704
int defaultWidth = layer->getWidth();
17051705
layerRule->setSpacing(defaultSpace * 2);
17061706
layerRule->setWidth(defaultWidth);
1707-
// clang-format off
1708-
debugPrint(logger_, CTS, "clustering", 1, " NDR rule set to layer {} {} as "
1709-
"space={} width={} vs. default space={} width={}",
1710-
i, layer->getName(),
1711-
layerRule->getSpacing(), layerRule->getWidth(),
1712-
defaultSpace, defaultWidth);
1713-
// clang-format on
1707+
1708+
debugPrint(logger_,
1709+
CTS,
1710+
"clustering",
1711+
1,
1712+
" NDR rule set to layer {} {} as space={} width={} vs. default "
1713+
"space={} width={}",
1714+
i,
1715+
layer->getName(),
1716+
layerRule->getSpacing(),
1717+
layerRule->getWidth(),
1718+
defaultSpace,
1719+
defaultWidth);
17141720
}
17151721

17161722
int clkNets = 0;
@@ -1732,12 +1738,14 @@ void TritonCTS::writeClockNDRsToDb(TreeBuilder* builder)
17321738
break;
17331739
}
17341740

1735-
logger_->info(CTS,
1736-
202,
1737-
"Non-default rule {} for double spacing has been applied to {} "
1738-
"clock nets",
1739-
ruleName,
1740-
clkNets);
1741+
debugPrint(logger_,
1742+
CTS,
1743+
"clustering",
1744+
1,
1745+
"Non-default rule {} for double spacing has been applied to {} "
1746+
"clock nets",
1747+
ruleName,
1748+
clkNets);
17411749
}
17421750

17431751
std::pair<int, int> TritonCTS::branchBufferCount(ClockInst* inst,

‎src/cts/test/balance_levels.defok‎

Lines changed: 44 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,44 @@ BUSBITCHARS "[]" ;
44
DESIGN multi_sink ;
55
UNITS DISTANCE MICRONS 2000 ;
66
DIEAREA ( 0 0 ) ( 200000 200000 ) ;
7+
NONDEFAULTRULES 3 ;
8+
- CTS_NDR_0
9+
+ LAYER metal1 WIDTH 140 SPACING 260
10+
+ LAYER metal2 WIDTH 140 SPACING 280
11+
+ LAYER metal3 WIDTH 140 SPACING 280
12+
+ LAYER metal4 WIDTH 280 SPACING 560
13+
+ LAYER metal5 WIDTH 280 SPACING 560
14+
+ LAYER metal6 WIDTH 280 SPACING 560
15+
+ LAYER metal7 WIDTH 800 SPACING 1600
16+
+ LAYER metal8 WIDTH 800 SPACING 1600
17+
+ LAYER metal9 WIDTH 1600 SPACING 3200
18+
+ LAYER metal10 WIDTH 1600 SPACING 3200
19+
;
20+
- CTS_NDR_1
21+
+ LAYER metal1 WIDTH 140 SPACING 260
22+
+ LAYER metal2 WIDTH 140 SPACING 280
23+
+ LAYER metal3 WIDTH 140 SPACING 280
24+
+ LAYER metal4 WIDTH 280 SPACING 560
25+
+ LAYER metal5 WIDTH 280 SPACING 560
26+
+ LAYER metal6 WIDTH 280 SPACING 560
27+
+ LAYER metal7 WIDTH 800 SPACING 1600
28+
+ LAYER metal8 WIDTH 800 SPACING 1600
29+
+ LAYER metal9 WIDTH 1600 SPACING 3200
30+
+ LAYER metal10 WIDTH 1600 SPACING 3200
31+
;
32+
- CTS_NDR_2
33+
+ LAYER metal1 WIDTH 140 SPACING 260
34+
+ LAYER metal2 WIDTH 140 SPACING 280
35+
+ LAYER metal3 WIDTH 140 SPACING 280
36+
+ LAYER metal4 WIDTH 280 SPACING 560
37+
+ LAYER metal5 WIDTH 280 SPACING 560
38+
+ LAYER metal6 WIDTH 280 SPACING 560
39+
+ LAYER metal7 WIDTH 800 SPACING 1600
40+
+ LAYER metal8 WIDTH 800 SPACING 1600
41+
+ LAYER metal9 WIDTH 1600 SPACING 3200
42+
+ LAYER metal10 WIDTH 1600 SPACING 3200
43+
;
44+
END NONDEFAULTRULES
745
COMPONENTS 368 ;
846
- CELL/CKGATE BUF_X1 + PLACED ( 100000 100000 ) N ;
947
- clkbuf_0_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 140117 ) N ;
@@ -381,16 +419,16 @@ PINS 1 ;
381419
+ FIXED ( 100000 199860 ) N ;
382420
END PINS
383421
NETS 39 ;
384-
- CELL/clk2 ( clkbuf_0_CELL\/clk2 A ) ( CELL/CKGATE Z ) + USE CLOCK ;
385-
- clk ( PIN clk ) ( clkbuf_regs_0_clk A ) ( clkbuf_0_clk A ) + USE CLOCK ;
386-
- clk_regs ( clkbuf_regs_0_clk Z ) ( clkbuf_0_clk_regs A ) + USE CLOCK ;
422+
- CELL/clk2 ( clkbuf_0_CELL\/clk2 A ) ( CELL/CKGATE Z ) + USE CLOCK + NONDEFAULTRULE CTS_NDR_2 ;
423+
- clk ( PIN clk ) ( clkbuf_regs_0_clk A ) ( clkbuf_0_clk A ) + USE CLOCK + NONDEFAULTRULE CTS_NDR_0 ;
424+
- clk_regs ( clkbuf_regs_0_clk Z ) ( clkbuf_0_clk_regs A ) + USE CLOCK + NONDEFAULTRULE CTS_NDR_1 ;
387425
- clknet_0_CELL\/clk2 ( clkbuf_4_15__f_CELL\/clk2 A ) ( clkbuf_4_14__f_CELL\/clk2 A ) ( clkbuf_4_13__f_CELL\/clk2 A ) ( clkbuf_4_12__f_CELL\/clk2 A ) ( clkbuf_4_11__f_CELL\/clk2 A ) ( clkbuf_4_10__f_CELL\/clk2 A ) ( clkbuf_4_9__f_CELL\/clk2 A )
388426
( clkbuf_4_8__f_CELL\/clk2 A ) ( clkbuf_4_7__f_CELL\/clk2 A ) ( clkbuf_4_6__f_CELL\/clk2 A ) ( clkbuf_4_5__f_CELL\/clk2 A ) ( clkbuf_4_4__f_CELL\/clk2 A ) ( clkbuf_4_3__f_CELL\/clk2 A ) ( clkbuf_4_2__f_CELL\/clk2 A ) ( clkbuf_4_1__f_CELL\/clk2 A )
389-
( clkbuf_4_0__f_CELL\/clk2 A ) ( clkbuf_0_CELL\/clk2 Z ) + USE CLOCK ;
390-
- clknet_0_clk ( clkbuf_1_0__f_clk A ) ( clkbuf_0_clk Z ) + USE CLOCK ;
427+
( clkbuf_4_0__f_CELL\/clk2 A ) ( clkbuf_0_CELL\/clk2 Z ) + USE CLOCK + NONDEFAULTRULE CTS_NDR_2 ;
428+
- clknet_0_clk ( clkbuf_1_0__f_clk A ) ( clkbuf_0_clk Z ) + USE CLOCK + NONDEFAULTRULE CTS_NDR_0 ;
391429
- clknet_0_clk_regs ( clkbuf_4_15__f_clk_regs A ) ( clkbuf_4_14__f_clk_regs A ) ( clkbuf_4_13__f_clk_regs A ) ( clkbuf_4_12__f_clk_regs A ) ( clkbuf_4_11__f_clk_regs A ) ( clkbuf_4_10__f_clk_regs A ) ( clkbuf_4_9__f_clk_regs A )
392430
( clkbuf_4_8__f_clk_regs A ) ( clkbuf_4_7__f_clk_regs A ) ( clkbuf_4_6__f_clk_regs A ) ( clkbuf_4_5__f_clk_regs A ) ( clkbuf_4_4__f_clk_regs A ) ( clkbuf_4_3__f_clk_regs A ) ( clkbuf_4_2__f_clk_regs A ) ( clkbuf_4_1__f_clk_regs A )
393-
( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK ;
431+
( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK + NONDEFAULTRULE CTS_NDR_1 ;
394432
- clknet_1_0__leaf_clk ( CELL/CKGATE A ) ( clkbuf_1_0__f_clk Z ) + USE CLOCK ;
395433
- clknet_4_0__leaf_CELL\/clk2 ( clkload15 A ) ( ff162 CK ) ( ff163 CK ) ( ff164 CK ) ( ff165 CK ) ( ff180 CK ) ( ff181 CK )
396434
( ff182 CK ) ( ff183 CK ) ( ff184 CK ) ( clkbuf_4_0__f_CELL\/clk2 Z ) + USE CLOCK ;

‎src/cts/test/simple_test.ok‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,6 @@
3434
[INFO CTS-0015] Created 3 clock nets.
3535
[INFO CTS-0016] Fanout distribution for the current clock = 8:2..
3636
[INFO CTS-0017] Max level of the clock tree: 1.
37-
[INFO CTS-0202] Non-default rule CTS_NDR_0 for double spacing has been applied to 2 clock nets
3837
[INFO CTS-0098] Clock net "clk"
3938
[INFO CTS-0099] Sinks 16
4039
[INFO CTS-0100] Leaf buffers 0

‎src/cts/test/simple_test_hier.ok‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,6 @@ delta HPWL 0 %
7373
[INFO CTS-0015] Created 3 clock nets.
7474
[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 9:1..
7575
[INFO CTS-0017] Max level of the clock tree: 1.
76-
[INFO CTS-0202] Non-default rule CTS_NDR_0 for double spacing has been applied to 2 clock nets
7776
[INFO CTS-0098] Clock net "clk"
7877
[INFO CTS-0099] Sinks 17
7978
[INFO CTS-0100] Leaf buffers 0

‎src/cts/test/twice.ok‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,6 @@
3434
[INFO CTS-0015] Created 3 clock nets.
3535
[INFO CTS-0016] Fanout distribution for the current clock = 8:2..
3636
[INFO CTS-0017] Max level of the clock tree: 1.
37-
[INFO CTS-0202] Non-default rule CTS_NDR_0 for double spacing has been applied to 2 clock nets
3837
[INFO CTS-0098] Clock net "clk"
3938
[INFO CTS-0099] Sinks 16
4039
[INFO CTS-0100] Leaf buffers 0

‎test/aes_nangate45.metrics_limits‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,23 @@
11
{
22
"IFP::instance_count" : "20110.8"
3-
,"DPL::design_area" : "30655.199999999997"
3+
,"DPL::design_area" : "30645.6"
44
,"DPL::utilization" : "3.36"
55
,"RSZ::repair_design_buffer_count" : "898"
66
,"RSZ::max_slew_slack" : "0"
77
,"RSZ::max_capacitance_slack" : "0"
88
,"RSZ::max_fanout_slack" : "0"
99
,"RSZ::worst_slack_min" : "-0.08100986965093143"
1010
,"RSZ::worst_slack_max" : "-0.2648922008839818"
11-
,"RSZ::tns_max" : "-157.20595070281772"
11+
,"RSZ::tns_max" : "-157.0916297024712"
1212
,"RSZ::hold_buffer_count" : "177"
1313
,"GRT::ANT::errors" : "0"
1414
,"DRT::drv" : "0"
15-
,"DRT::worst_slack_min" : "-0.10595330656178463"
16-
,"DRT::worst_slack_max" : "-0.3149059732009918"
17-
,"DRT::tns_max" : "-165.2482732938918"
18-
,"DRT::clock_skew" : "0.04566460672180108"
15+
,"DRT::worst_slack_min" : "-0.08915224554381444"
16+
,"DRT::worst_slack_max" : "-0.3520846788119148"
17+
,"DRT::tns_max" : "-166.57869887902655"
18+
,"DRT::clock_skew" : "0.037484716391855"
1919
,"DRT::max_slew_slack" : "0"
20-
,"DRT::max_capacitance_slack" : "-6.55280317656916"
20+
,"DRT::max_capacitance_slack" : "-18.37097475785969"
2121
,"DRT::max_fanout_slack" : "0"
2222
,"DRT::clock_period" : "0.8109"
2323
,"DRT::ANT::errors" : "0"

‎test/aes_sky130hs.metrics_limits‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -12,12 +12,12 @@
1212
,"RSZ::hold_buffer_count" : "631"
1313
,"GRT::ANT::errors" : "0"
1414
,"DRT::drv" : "0"
15-
,"DRT::worst_slack_min" : "-0.34456301441768966"
16-
,"DRT::worst_slack_max" : "-1.458594801658096"
17-
,"DRT::tns_max" : "-603.0098213818037"
18-
,"DRT::clock_skew" : "0.5057897577260145"
19-
,"DRT::max_slew_slack" : "-14.647869765758514"
20-
,"DRT::max_capacitance_slack" : "-17.234991298284676"
15+
,"DRT::worst_slack_min" : "-0.33816268952201456"
16+
,"DRT::worst_slack_max" : "-1.514588679444076"
17+
,"DRT::tns_max" : "-602.720715745301"
18+
,"DRT::clock_skew" : "0.5050632721670744"
19+
,"DRT::max_slew_slack" : "-18.907275795936584"
20+
,"DRT::max_capacitance_slack" : "-21.363397571361123"
2121
,"DRT::max_fanout_slack" : "0"
2222
,"DRT::clock_period" : "2.811"
2323
,"DRT::ANT::errors" : "0"

‎test/gcd_nangate45.metrics‎

Lines changed: 27 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -15,40 +15,38 @@
1515
"design__instance__displacement__mean": 0.0175,
1616
"design__instance__displacement__max": 0.95,
1717
"route__wirelength__estimated": 4382.26,
18-
"design__instance__count__setup_buffer": 31,
18+
"design__instance__count__setup_buffer": 30,
1919
"design__instance__count__hold_buffer": 0,
2020
"RSZ::worst_slack_min": "0.050029863612428234",
21-
"RSZ::worst_slack_max": "-0.03363373563746066",
22-
"RSZ::tns_max": "-0.32014791723820024",
21+
"RSZ::worst_slack_max": "-0.03342237692317001",
22+
"RSZ::tns_max": "-0.24580527198299937",
2323
"RSZ::hold_buffer_count": "0",
24-
"design__instance__displacement__total": 64.367,
25-
"design__instance__displacement__mean": 0.128,
24+
"design__instance__displacement__total": 66.042,
25+
"design__instance__displacement__mean": 0.1315,
2626
"design__instance__displacement__max": 3.2375,
27-
"route__wirelength__estimated": 4758.62,
27+
"route__wirelength__estimated": 4756.99,
2828
"DPL::utilization": "9.2",
29-
"DPL::design_area": "589",
30-
"route__net": 456,
29+
"DPL::design_area": "591",
30+
"route__net": 455,
3131
"route__net__special": 2,
32-
"global_route__vias": 2790,
33-
"global_route__wirelength": 7669,
32+
"global_route__vias": 2984,
33+
"global_route__wirelength": 8752,
3434
"grt__antenna_diodes_count": 0,
3535
"grt__antenna__violating__nets": 0,
3636
"grt__antenna__violating__pins": 0,
3737
"GRT::ANT::errors": "0",
38-
"route__net": 456,
38+
"route__net": 455,
3939
"route__net__special": 2,
40-
"route__drc_errors__iter:0": 32,
41-
"route__wirelength__iter:0": 5523,
42-
"route__drc_errors__iter:1": 6,
43-
"route__wirelength__iter:1": 5487,
44-
"route__drc_errors__iter:2": 1,
45-
"route__wirelength__iter:2": 5486,
46-
"route__drc_errors__iter:3": 0,
47-
"route__wirelength__iter:3": 5487,
40+
"route__drc_errors__iter:0": 34,
41+
"route__wirelength__iter:0": 6084,
42+
"route__drc_errors__iter:1": 2,
43+
"route__wirelength__iter:1": 5969,
44+
"route__drc_errors__iter:2": 0,
45+
"route__wirelength__iter:2": 5967,
4846
"route__drc_errors": 0,
49-
"route__wirelength": 5487,
50-
"route__vias": 2302,
51-
"route__vias__singlecut": 2302,
47+
"route__wirelength": 5967,
48+
"route__vias": 2373,
49+
"route__vias__singlecut": 2373,
5250
"route__vias__multicut": 0,
5351
"DRT::drv": "0",
5452
"drt__repair_antennas__pre_repair__antenna__violating__nets": 0,
@@ -59,14 +57,14 @@
5957
"design__violations": 0,
6058
"timing__drv__floating__nets": 0,
6159
"timing__drv__floating__pins": 0,
62-
"DRT::worst_slack_min": "0.04907561995688116",
63-
"DRT::worst_slack_max": "-0.035494636012815974",
64-
"DRT::tns_max": "-0.4040689008869461",
65-
"DRT::clock_skew": "0.002338202614375457",
66-
"DRT::max_slew_slack": "48.01817215920972",
60+
"DRT::worst_slack_min": "0.04871859303874601",
61+
"DRT::worst_slack_max": "-0.04067096774480058",
62+
"DRT::tns_max": "-0.5675516883772636",
63+
"DRT::clock_skew": "0.003170980928699366",
64+
"DRT::max_slew_slack": "48.6398050716263",
6765
"DRT::max_fanout_slack": "100.0",
68-
"DRT::max_capacitance_slack": "33.13695490217507",
66+
"DRT::max_capacitance_slack": "30.17115702060213",
6967
"DRT::clock_period": "0.485000",
70-
"flow__warnings__count": 8,
68+
"flow__warnings__count": 10,
7169
"flow__errors__count": 0
7270
}

‎test/gcd_nangate45.metrics_limits‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,21 @@
11
{
22
"IFP::instance_count" : "435.59999999999997"
3-
,"DPL::design_area" : "706.8"
3+
,"DPL::design_area" : "709.1999999999999"
44
,"DPL::utilization" : "11.04"
55
,"RSZ::repair_design_buffer_count" : "2"
66
,"RSZ::max_slew_slack" : "0"
77
,"RSZ::max_capacitance_slack" : "0"
88
,"RSZ::max_fanout_slack" : "0"
99
,"RSZ::worst_slack_min" : "0.0015298636124282325"
10-
,"RSZ::worst_slack_max" : "-0.08213373563746065"
11-
,"RSZ::tns_max" : "-2.0806979172382003"
10+
,"RSZ::worst_slack_max" : "-0.08192237692317"
11+
,"RSZ::tns_max" : "-2.0063552719829993"
1212
,"RSZ::hold_buffer_count" : "0"
1313
,"GRT::ANT::errors" : "0"
1414
,"DRT::drv" : "0"
15-
,"DRT::worst_slack_min" : "0.0005756199568811571"
16-
,"DRT::worst_slack_max" : "-0.08399463601281598"
17-
,"DRT::tns_max" : "-2.1646189008869463"
18-
,"DRT::clock_skew" : "0.0028058431372505483"
15+
,"DRT::worst_slack_min" : "0.00021859303874600944"
16+
,"DRT::worst_slack_max" : "-0.08917096774480057"
17+
,"DRT::tns_max" : "-2.328101688377264"
18+
,"DRT::clock_skew" : "0.003805177114439239"
1919
,"DRT::max_slew_slack" : "0"
2020
,"DRT::max_capacitance_slack" : "0"
2121
,"DRT::max_fanout_slack" : "0"

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