Add AES asap7 test.

mguthaus · mguthaus · commit ab63b7bdef1c · 2025-10-23T07:54:20.000-07:00
Signed-off-by: Matthew Guthaus &lt;mrg@ucsc.edu&gt;
diff --git a/test/BUILD b/test/BUILD
@@ -94,6 +94,7 @@ BIG_TESTS = [
     "gcd_sky130hd",
     "gcd_sky130hs",
     "gcd_asap7",
+    "aes_asap7",
     "ibex_sky130hd",
     "ibex_sky130hs",
     "jpeg_sky130hd",
diff --git a/test/aes_asap7.sdc b/test/aes_asap7.sdc
@@ -0,0 +1,2 @@
+create_clock [get_ports clk] -name core_clock -period 400
+set_all_input_output_delays
diff --git a/test/aes_asap7.tcl b/test/aes_asap7.tcl
@@ -0,0 +1,13 @@
+# gcd flow pipe cleaner
+source "helpers.tcl"
+source "flow_helpers.tcl"
+source "asap7/asap7.vars"
+
+set design "aes"
+set top_module "aes_cipher_top"
+set synth_verilog "aes_asap7.v"
+set sdc_file "aes_asap7.sdc"
+set die_area {0.0 0.0 68.746 68.746}
+set core_area {2.052 2.160 66.744 66.690}
+
+include -echo "flow.tcl"
diff --git a/test/regression_tests.tcl b/test/regression_tests.tcl
@@ -12,6 +12,7 @@ record_flow_tests {
   aes_nangate45
   aes_sky130hd
   aes_sky130hs
+  aes_asap7
 
   tinyRocket_nangate45
 

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+create_clock [get_ports clk] -name core_clock -period 400`
	`2`	`+set_all_input_output_delays`