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grt: add ok file
Signed-off-by: Eder Monteiro <[email protected]>
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3 files changed

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lines changed

3 files changed

+40
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src/grt/test/BUILD

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@@ -3,6 +3,7 @@ load("//test:regression.bzl", "regression_test")
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TESTS = [
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"bus_route",
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"clock_route",
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"clock_route_cugr",
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"clock_route_alpha",
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"clock_route_error1",
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"clock_route_error2",

src/grt/test/CMakeLists.txt

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@@ -3,6 +3,7 @@ or_integration_tests(
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TESTS
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bus_route
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clock_route
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clock_route_cugr
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clock_route_alpha
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clock_route_error1
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clock_route_error2

src/grt/test/clock_route_cugr.ok

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[INFO ODB-0227] LEF file: sky130hs/sky130hs.tlef, created 13 layers, 25 vias
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[INFO ODB-0227] LEF file: sky130hs/sky130hs_std_cell.lef, created 390 library cells
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[INFO ODB-0128] Design: gcd
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[INFO ODB-0130] Created 1 pins.
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[INFO ODB-0131] Created 170 components and 1258 component-terminals.
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[INFO ODB-0133] Created 15 nets and 72 connections.
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[INFO GRT-0020] Min routing layer: met1
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[INFO GRT-0021] Max routing layer: met5
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[INFO GRT-0022] Global adjustment: 50%
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[INFO GRT-0023] Grid origin: (0, 0)
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[INFO GRT-0088] Layer li1 Track-Pitch = 0.4800 line-2-Via Pitch: 0.3400
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[INFO GRT-0088] Layer met1 Track-Pitch = 0.3700 line-2-Via Pitch: 0.3400
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[INFO GRT-0088] Layer met2 Track-Pitch = 0.4800 line-2-Via Pitch: 0.3500
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[INFO GRT-0088] Layer met3 Track-Pitch = 0.7400 line-2-Via Pitch: 0.6150
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[INFO GRT-0088] Layer met4 Track-Pitch = 0.9600 line-2-Via Pitch: 1.0400
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[INFO GRT-0088] Layer met5 Track-Pitch = 3.3300 line-2-Via Pitch: 3.1100
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[INFO GRT-0003] Macros: 0
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[INFO GRT-0004] Blockages: 13
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[INFO GRT-0019] Found 6 clock nets.
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[INFO GRT-0001] Minimum degree: 2
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[INFO GRT-0002] Maximum degree: 12
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design statistics
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lib DBU: 1000
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die region (in DBU): [x: (0, 279960), y: (0, 280130)]
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num of nets : 15
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num of special nets: 0
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gcell grid: 38 x 38 x 6
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stage 1: pattern routing
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0 / 15 gr_nets_ have overflows.
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routing statistics
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wire length (metric): 2918
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total via count: 169
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total wire overflow: 0
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min resource: 2
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bottleneck: (5, 0, 0)
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[INFO GRT-0018] Total wirelength: 1656 um
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[INFO GRT-0014] Routed nets: 15
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