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power: test vcd power with estimated and actual parasitics
Signed-off-by: Øyvind Harboe <[email protected]>
1 parent 53577be commit afa16bf

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1 file changed

+106
-71
lines changed
  • test/orfs/mock-array

1 file changed

+106
-71
lines changed

test/orfs/mock-array/BUILD

Lines changed: 106 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,19 @@ load("@rules_shell//shell:sh_test.bzl", "sh_test")
77
load("@rules_verilator//verilator:defs.bzl", "verilator_cc_library")
88
load("@rules_verilator//verilog:defs.bzl", "verilog_library")
99

10-
POWER_STAGE_NAME = "cts"
10+
POWER_STAGES = {
11+
"cts": {
12+
"stage": "4",
13+
},
14+
"final": {
15+
"stage": "6",
16+
},
17+
}
1118

1219
POWER_STAGE_STEM = {
13-
"cts": "4",
14-
"final": "6",
15-
}[POWER_STAGE_NAME] + "_" + POWER_STAGE_NAME
20+
stage: POWER_STAGES[stage]["stage"] + "_" + stage
21+
for stage in POWER_STAGES
22+
}
1623

1724
# single source of truth for defaults.
1825
# each number is a unit
@@ -172,7 +179,6 @@ filegroup(
172179

173180
orfs_flow(
174181
name = "Element",
175-
abstract_stage = POWER_STAGE_NAME,
176182
arguments = {
177183
"CORE_AREA": "{} {} {} {}".format(
178184
ce_margin_x,
@@ -274,24 +280,25 @@ MACROS = [
274280
name = "{macro}_parasitics".format(macro = macro),
275281
src = ":{macro}_{stage}".format(
276282
macro = macro,
277-
stage = POWER_STAGE_NAME,
283+
stage = stage,
278284
),
279285
outs = [
280286
"results/asap7/{macro}/base/{stem}.spef".format(
281287
macro = macro,
282-
stem = POWER_STAGE_STEM,
288+
stem = POWER_STAGE_STEM[stage],
283289
),
284290
"results/asap7/{macro}/base/{stem}.v".format(
285291
macro = macro,
286-
stem = POWER_STAGE_STEM,
292+
stem = POWER_STAGE_STEM[stage],
287293
),
288294
],
289295
script = ":parasitics.tcl",
290296
tags = ["manual"],
291297
visibility = ["//visibility:public"],
292298
)
293299
for macro in MACROS
294-
if POWER_STAGE_NAME != "final"
300+
for stage in POWER_STAGES
301+
if stage != "final"
295302
]
296303

297304
[
@@ -300,22 +307,23 @@ MACROS = [
300307
srcs = [
301308
":{macro}_{stage}".format(
302309
macro = macro,
303-
stage = POWER_STAGE_NAME,
310+
stage = stage,
304311
),
305312
],
306-
output_group = POWER_STAGE_STEM + ".v",
313+
output_group = POWER_STAGE_STEM[stage] + ".v",
307314
)
308315
for macro in MACROS
309-
if POWER_STAGE_NAME == "final"
316+
for stage in POWER_STAGES
317+
if stage == "final"
310318
]
311319

312-
verilog_library(
313-
name = "array",
320+
[verilog_library(
321+
name = "array_{stage}".format(stage = stage),
314322
srcs = [
315323
("results/asap7/{macro}/base/{stem}.v".format(
316324
macro = macro,
317-
stem = POWER_STAGE_STEM,
318-
) if POWER_STAGE_NAME != "final" else "{macro}_netlist".format(macro = macro))
325+
stem = POWER_STAGE_STEM[stage],
326+
) if stage != "final" else "{macro}_netlist".format(macro = macro))
319327
for macro in MACROS
320328
] + [
321329
"@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v",
@@ -325,15 +333,15 @@ verilog_library(
325333
"@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/empty.v",
326334
],
327335
tags = ["manual"],
328-
)
336+
) for stage in POWER_STAGES]
329337

330-
verilator_cc_library(
331-
name = "array_verilator",
338+
[verilator_cc_library(
339+
name = "array_verilator_{stage}".format(stage = stage),
332340
copts = [
333341
# Don't care about warnings from Verilator generated C++
334342
"-Wno-unused-variable",
335343
],
336-
module = ":array",
344+
module = ":array_{stage}".format(stage = stage),
337345
module_top = "MockArray",
338346
tags = ["manual"],
339347
trace = True,
@@ -349,10 +357,10 @@ verilator_cc_library(
349357
# No-op option to retrigger a build
350358
# "-Wfuture-blah",
351359
],
352-
)
360+
) for stage in POWER_STAGES]
353361

354-
cc_binary(
355-
name = "simulator",
362+
[cc_binary(
363+
name = "simulator_{stage}".format(stage = stage),
356364
srcs = [
357365
"simulate.cpp",
358366
],
@@ -361,22 +369,22 @@ cc_binary(
361369
],
362370
tags = ["manual"],
363371
deps = [
364-
":array_verilator",
372+
":array_verilator_{stage}".format(stage = stage),
365373
],
366-
)
374+
) for stage in POWER_STAGES]
367375

368-
genrule(
369-
name = "vcd",
376+
[genrule(
377+
name = "vcd_{stage}".format(stage = stage),
370378
srcs = [
371379
# FIXME move to tools, using target configuration for now to avoid rebuilds
372-
":simulator",
380+
":simulator_{stage}".format(stage = stage),
373381
],
374-
outs = ["MockArrayTestbench.vcd"],
375-
cmd = "$(execpath :simulator) $(location :MockArrayTestbench.vcd)",
382+
outs = ["MockArrayTestbench_{stage}.vcd".format(stage = stage)],
383+
cmd = "$(execpath :simulator_{stage}) $(location :MockArrayTestbench_{stage}.vcd)".format(stage = stage),
376384
tags = ["manual"],
377385
tools = [
378386
],
379-
)
387+
) for stage in POWER_STAGES]
380388

381389
# If we want to measure power after final, instead of with estimated parasitics,
382390
# we'll need this.
@@ -385,60 +393,87 @@ SPEFS_AND_NETLISTS = [
385393
":results/asap7/{macro}/{stem}.{ext}".format(
386394
ext = ext,
387395
macro = macro,
388-
stem = POWER_STAGE_STEM,
396+
stem = POWER_STAGE_STEM[stage],
389397
)
390398
for macro in MACROS
391399
for ext in [
392400
"spef",
393401
"v",
394402
]
403+
for stage in POWER_STAGES
395404
]
396405

397406
POWER_TESTS = [
398407
"power",
399408
"power_instances",
400409
]
401410

402-
[orfs_run(
403-
name = "MockArray_{name}".format(name = name),
404-
src = ":MockArray_{stage}".format(stage = POWER_STAGE_NAME),
405-
outs = [
406-
"{name}.txt".format(name = name),
407-
],
408-
arguments = {
409-
"LOAD_POWER_TCL": "$(location :load_power.tcl)",
410-
"OPENROAD_EXE": "$(location //src/sta:opensta)",
411-
"OUTPUT": "$(location :{name}.txt)".format(name = name),
412-
"POWER_STAGE_NAME": POWER_STAGE_NAME,
413-
"POWER_STAGE_STEM": POWER_STAGE_STEM,
414-
"VCD_STIMULI": "$(location :vcd)",
415-
},
416-
data = [
417-
# FIXME this is a workaround to ensure that the OpenSTA runfiles are available
418-
":opensta_runfiles",
419-
":vcd",
420-
":load_power.tcl",
421-
] + ["{macro}_{stage}".format(
422-
macro = macro,
423-
stage = POWER_STAGE_NAME,
424-
) for macro in MACROS] +
425-
(["{macro}_parasitics".format(macro = macro) for macro in MACROS] if POWER_STAGE_NAME != "final" else []),
426-
script = ":{name}.tcl".format(name = name),
427-
tags = ["manual"],
428-
tools = ["//src/sta:opensta"],
429-
visibility = ["//visibility:public"],
430-
) for name in POWER_TESTS]
411+
[
412+
orfs_run(
413+
name = "MockArray_{stage}_{name}".format(
414+
name = name,
415+
stage = stage,
416+
),
417+
src = ":MockArray_{stage}".format(stage = stage),
418+
outs = [
419+
"{name}_{stage}.txt".format(
420+
name = name,
421+
stage = stage,
422+
),
423+
],
424+
arguments = {
425+
"LOAD_POWER_TCL": "$(location :load_power.tcl)",
426+
"OPENROAD_EXE": "$(location //src/sta:opensta)",
427+
"OUTPUT": "$(location :{name}_{stage}.txt)".format(
428+
name = name,
429+
stage = stage,
430+
),
431+
"POWER_STAGE_NAME": stage,
432+
"POWER_STAGE_STEM": POWER_STAGE_STEM[stage],
433+
"VCD_STIMULI": "$(location :vcd_{stage})".format(stage = stage),
434+
},
435+
data = [
436+
# FIXME this is a workaround to ensure that the OpenSTA runfiles are available
437+
":opensta_runfiles",
438+
":vcd_{stage}".format(stage = stage),
439+
":load_power.tcl",
440+
] + ["{macro}_{stage}".format(
441+
macro = macro,
442+
stage = stage,
443+
) for macro in MACROS] +
444+
(["{macro}_parasitics".format(macro = macro) for macro in MACROS] if stage != "final" else []),
445+
script = ":{name}.tcl".format(name = name),
446+
tags = ["manual"],
447+
tools = ["//src/sta:opensta"],
448+
visibility = ["//visibility:public"],
449+
)
450+
for name in POWER_TESTS
451+
for stage in POWER_STAGES
452+
]
431453

432-
[sh_test(
433-
name = "MockArray_{name}_test".format(name = name),
434-
srcs = ["ok.sh"],
435-
args = [
436-
"$(location :MockArray_{name})".format(name = name),
437-
],
438-
data = [
439-
":MockArray_{name}".format(name = name),
440-
],
441-
) for name in POWER_TESTS]
454+
[
455+
sh_test(
456+
name = "MockArray_{name}_{stage}_test".format(
457+
name = name,
458+
stage = stage,
459+
),
460+
srcs = ["ok.sh"],
461+
args = [
462+
"$(location :MockArray_{stage}_{name})".format(
463+
name = name,
464+
stage = stage,
465+
),
466+
],
467+
data = [
468+
":MockArray_{stage}_{name}".format(
469+
name = name,
470+
stage = stage,
471+
),
472+
],
473+
)
474+
for name in POWER_TESTS
475+
for stage in POWER_STAGES
476+
]
442477

443478
# FIXME why is this needed to ensure that cfg=exec of OpenSTA has runfiles?
444479
genrule(

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