Commit b03c7ec
committed
fix the sta submodule which was mistakenly reset backwards
Signed-off-by: Matt Liberty <[email protected]>1 parent 3daea17 commit b03c7ec
1 file changed
+1
-1
lines changed- .github/workflows/buildifier.yaml+44
- BUILD+5-2
- CMakeLists.txt+9-2
- dcalc/DmpCeff.cc+13-24
- dcalc/GraphDelayCalc.cc+6-6
- doc/CodingGuidelines.txt+17-3
- doc/OpenSTA.fodt+1.5k-1.4k
- doc/OpenSTA.pdf
- graph/Graph.cc+16-4
- include/sta/Delay.hh+2
- include/sta/ExceptionPath.hh+5-1
- include/sta/Graph.hh+2-1
- include/sta/GraphDelayCalc.hh-1
- include/sta/MinMaxValues.hh+28-2
- include/sta/Path.hh+2-2
- include/sta/PathEnd.hh+2
- include/sta/Property.hh+7-4
- include/sta/Search.hh+40-40
- liberty/Liberty.cc+5-2
- liberty/LibertyReader.cc+2
- power/Power.cc+33-20
- power/Power.tcl+1-1
- power/VcdParse.cc+15-9
- power/VcdParse.hh+2-1
- power/VcdReader.cc+21-8
- sdc/ExceptionPath.cc+33-27
- sdc/Sdc.cc+4-2
- search/Bfs.cc+4-2
- search/CheckMinPulseWidths.cc+13-13
- search/ClkInfo.cc+82-61
- search/ClkInfo.hh+13-12
- search/ClkLatency.cc+1-1
- search/Crpr.cc+13-10
- search/Crpr.hh+1-1
- search/Genclks.cc+22-14
- search/Genclks.hh+1
- search/Latches.cc+21-5
- search/Levelize.cc+1-3
- search/Levelize.hh-1
- search/Path.cc+15-16
- search/PathEnd.cc+23-5
- search/PathEnum.cc+65-36
- search/PathGroup.cc+1-3
- search/Property.cc+15-2
- search/ReportPath.cc+74-77
- search/ReportPath.hh+9-5
- search/Search.cc+106-85
- search/Search.i+4-3
- search/Search.tcl+2-2
- search/Sta.cc+2-1
- search/Tag.cc+82-118
- search/Tag.hh+45-38
- search/TagGroup.cc+27-12
- search/TagGroup.hh+12-3
- search/VisitPathEnds.cc+1-7
- search/VisitPathGroupVertices.cc+1-1
- test/package_require.ok
- test/package_require.tcl+3
- test/regression_vars.tcl+3
- test/report_checks_sorted.ok+87
- test/report_checks_sorted.tcl+12
- test/report_checks_sorted.v+15
- test/report_json1.ok+4-2
- test/verilog_specify.ok
- test/verilog_specify.tcl+2
- test/verilog_specify.v+20
- util/DispatchQueue.cc+2-2
- util/PatternMatch.cc+2
- util/StaConfig.hh.cmake+2
- util/gzstream.hh+1-1
- verilog/VerilogLex.ll+3
- verilog/VerilogParse.yy+23
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