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Merge pull request #279 from The-OpenROAD-Project/tests_use_nangate45
Tests use nangate45
2 parents d378e53 + 3d6f286 commit c1b6dfb

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src/init_fp/test/Nangate45

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../../../test/Nangate45

src/init_fp/test/init_floorplan1.defok

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1-
Notice 0: Reading LEF file: liberty1.lef
2-
Notice 0: Created 2 technology layers
3-
Notice 0: Created 7 library cells
4-
Notice 0: Finished LEF file: liberty1.lef
1+
Notice 0: Reading LEF file: Nangate45/Nangate45.lef
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Notice 0: Created 22 technology layers
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Notice 0: Created 27 technology vias
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Notice 0: Created 134 library cells
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Notice 0: Finished LEF file: Nangate45/Nangate45.lef
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Notice 0:
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Reading DEF file: reg1.def
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Notice 0: Design: top
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Notice 0: Created 6 pins.
9-
Notice 0: Created 5 components and 24 component-terminals.
10+
Notice 0: Created 5 components and 27 component-terminals.
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Notice 0: Created 2 special nets and 10 connections.
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Notice 0: Created 10 nets and 14 connections.
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Notice 0: Finished DEF file: reg1.def
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Info: Added 40 rows of 16 sites.
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Info: Added 571 rows of 4210 sites.
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No differences found.

src/init_fp/test/init_floorplan1.tcl

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@@ -1,12 +1,12 @@
11
# init_floorplan
2-
source "../../../test/helpers.tcl"
3-
read_lef liberty1.lef
2+
source "helpers.tcl"
3+
read_lef Nangate45/Nangate45.lef
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read_liberty Nangate45/Nangate45_typ.lib
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read_def reg1.def
5-
read_liberty liberty1.lib
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initialize_floorplan -die_area "0 0 1000 1000" \
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-core_area "100 100 900 900" \
8-
-site site1
9-
auto_place_pins M1
8+
-site FreePDK45_38x28_10R_NP_162NW_34O
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auto_place_pins metal1
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set def_file [make_result_file init_floorplan1.def]
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write_def $def_file

src/init_fp/test/init_floorplan2.defok

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Notice 0: Reading LEF file: liberty1.lef
2-
Notice 0: Created 2 technology layers
3-
Notice 0: Created 7 library cells
4-
Notice 0: Finished LEF file: liberty1.lef
1+
Notice 0: Reading LEF file: Nangate45/Nangate45.lef
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Notice 0: Created 22 technology layers
3+
Notice 0: Created 27 technology vias
4+
Notice 0: Created 134 library cells
5+
Notice 0: Finished LEF file: Nangate45/Nangate45.lef
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Notice 0:
67
Reading DEF file: reg1.def
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Notice 0: Design: top
89
Notice 0: Created 6 pins.
9-
Notice 0: Created 5 components and 24 component-terminals.
10+
Notice 0: Created 5 components and 27 component-terminals.
1011
Notice 0: Created 2 special nets and 10 connections.
1112
Notice 0: Created 10 nets and 14 connections.
1213
Notice 0: Finished DEF file: reg1.def
13-
Info: Added 40 rows of 16 sites.
14+
Info: Added 571 rows of 4210 sites.
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No differences found.

src/init_fp/test/init_floorplan2.tcl

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Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
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# init_floorplan -tracks
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source "helpers.tcl"
3-
read_lef liberty1.lef
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read_lef Nangate45/Nangate45.lef
4+
read_liberty Nangate45/Nangate45_typ.lib
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read_def reg1.def
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read_liberty liberty1.lib
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initialize_floorplan -die_area "0 0 1000 1000" \
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-core_area "100 100 900 900" \
8-
-site site1 \
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-site FreePDK45_38x28_10R_NP_162NW_34O \
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-tracks init_floorplan2.tracks
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auto_place_pins M1
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auto_place_pins metal1
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set def_file [make_result_file init_floorplan2.def]
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write_def $def_file
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@@ -1,4 +1,4 @@
1-
M1 X 0.1 0.2
2-
M1 Y 0.1 0.2
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M2 X 0.1 0.2
4-
M2 Y 0.1 0.2
1+
metal1 X 0.1 0.2
2+
metal1 Y 0.1 0.2
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metal2 X 0.1 0.2
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metal2 Y 0.1 0.2

src/init_fp/test/init_floorplan3.defok

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -4,29 +4,29 @@ DIVIDERCHAR "/" ;
44
BUSBITCHARS "[]" ;
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DESIGN top ;
66
UNITS DISTANCE MICRONS 1000 ;
7-
DIEAREA ( 0 0 ) ( 186600 95300 ) ;
8-
ROW ROW_0 site1 0 0 FS DO 3 BY 1 STEP 50000 0 ;
9-
ROW ROW_1 site1 0 20000 N DO 3 BY 1 STEP 50000 0 ;
10-
ROW ROW_2 site1 0 40000 FS DO 3 BY 1 STEP 50000 0 ;
11-
ROW ROW_3 site1 0 60000 N DO 3 BY 1 STEP 50000 0 ;
12-
TRACKS X 100 DO 933 STEP 200 LAYER M1 ;
13-
TRACKS Y 100 DO 477 STEP 200 LAYER M1 ;
14-
TRACKS X 100 DO 933 STEP 200 LAYER M2 ;
15-
TRACKS Y 100 DO 477 STEP 200 LAYER M2 ;
7+
DIEAREA ( 0 0 ) ( 14140 9070 ) ;
8+
ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 1900 1400 FS DO 53 BY 1 STEP 190 0 ;
9+
ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 1900 2800 N DO 53 BY 1 STEP 190 0 ;
10+
ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 1900 4200 FS DO 53 BY 1 STEP 190 0 ;
11+
ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 1900 5600 N DO 53 BY 1 STEP 190 0 ;
12+
TRACKS X 100 DO 71 STEP 200 LAYER metal1 ;
13+
TRACKS Y 100 DO 45 STEP 200 LAYER metal1 ;
14+
TRACKS X 100 DO 71 STEP 200 LAYER metal2 ;
15+
TRACKS Y 100 DO 45 STEP 200 LAYER metal2 ;
1616
COMPONENTS 5 ;
17-
- r1 snl_ffqx1 ;
18-
- r2 snl_ffqx1 ;
19-
- r3 snl_ffqx1 ;
20-
- u1 snl_bufx1 ;
21-
- u2 snl_and02x1 ;
17+
- r1 DFF_X1 ;
18+
- r2 DFF_X1 ;
19+
- r3 DFF_X1 ;
20+
- u1 BUF_X1 ;
21+
- u2 AND2_X1 ;
2222
END COMPONENTS
2323
PINS 6 ;
24-
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 0 ) N + LAYER M1 ( 0 0 ) ( 0 0 ) ;
25-
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL + FIXED ( 76666 0 ) N + LAYER M1 ( 0 0 ) ( 0 0 ) ;
26-
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 150000 3332 ) N + LAYER M1 ( 0 0 ) ( 0 0 ) ;
27-
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL + FIXED ( 150000 79998 ) N + LAYER M1 ( 0 0 ) ( 0 0 ) ;
28-
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL + FIXED ( 73336 80000 ) N + LAYER M1 ( 0 0 ) ( 0 0 ) ;
29-
- out + NET out + DIRECTION OUTPUT + USE SIGNAL + FIXED ( 0 76670 ) N + LAYER M1 ( 0 0 ) ( 0 0 ) ;
24+
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 1900 1400 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
25+
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL + FIXED ( 7123 1400 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
26+
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 11970 1776 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
27+
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL + FIXED ( 11970 6999 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
28+
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL + FIXED ( 6748 7000 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
29+
- out + NET out + DIRECTION OUTPUT + USE SIGNAL + FIXED ( 1900 6625 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
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END PINS
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SPECIALNETS 2 ;
3232
- VSS ( * VSS ) + USE GROUND ;
@@ -35,13 +35,13 @@ END SPECIALNETS
3535
NETS 10 ;
3636
- in1 ( PIN in1 ) ( r1 D ) + USE SIGNAL ;
3737
- in2 ( PIN in2 ) ( r2 D ) + USE SIGNAL ;
38-
- clk1 ( PIN clk1 ) ( r1 CP ) + USE SIGNAL ;
39-
- clk2 ( PIN clk2 ) ( r2 CP ) + USE SIGNAL ;
40-
- clk3 ( PIN clk3 ) ( r3 CP ) + USE SIGNAL ;
38+
- clk1 ( PIN clk1 ) ( r1 CK ) + USE SIGNAL ;
39+
- clk2 ( PIN clk2 ) ( r2 CK ) + USE SIGNAL ;
40+
- clk3 ( PIN clk3 ) ( r3 CK ) + USE SIGNAL ;
4141
- out ( PIN out ) ( r3 Q ) + USE SIGNAL ;
42-
- r1q ( r1 Q ) ( u2 A ) + USE SIGNAL ;
42+
- r1q ( r1 Q ) ( u2 A1 ) + USE SIGNAL ;
4343
- r2q ( r2 Q ) ( u1 A ) + USE SIGNAL ;
44-
- u1z ( u1 Z ) ( u2 B ) + USE SIGNAL ;
45-
- u2z ( u2 Z ) ( r3 D ) + USE SIGNAL ;
44+
- u1z ( u1 Z ) ( u2 A2 ) + USE SIGNAL ;
45+
- u2z ( u2 ZN ) ( r3 D ) + USE SIGNAL ;
4646
END NETS
4747
END DESIGN
Lines changed: 7 additions & 6 deletions
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1-
Notice 0: Reading LEF file: liberty1.lef
2-
Notice 0: Created 2 technology layers
3-
Notice 0: Created 7 library cells
4-
Notice 0: Finished LEF file: liberty1.lef
1+
Notice 0: Reading LEF file: Nangate45/Nangate45.lef
2+
Notice 0: Created 22 technology layers
3+
Notice 0: Created 27 technology vias
4+
Notice 0: Created 134 library cells
5+
Notice 0: Finished LEF file: Nangate45/Nangate45.lef
56
Notice 0:
67
Reading DEF file: reg1.def
78
Notice 0: Design: top
89
Notice 0: Created 6 pins.
9-
Notice 0: Created 5 components and 24 component-terminals.
10+
Notice 0: Created 5 components and 27 component-terminals.
1011
Notice 0: Created 2 special nets and 10 connections.
1112
Notice 0: Created 10 nets and 14 connections.
1213
Notice 0: Finished DEF file: reg1.def
13-
Info: Added 4 rows of 3 sites.
14+
Info: Added 4 rows of 53 sites.
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No differences found.

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