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malibertymaliberty
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Merge pull request #8862 from arthurjolo/cts_fix_dummy_loads_report
Cts fix dummy loads report
2 parents ce2ab8f + c582104 commit c1d5d3b

40 files changed

+86
-78
lines changed

‎src/cts/include/cts/TritonCTS.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -188,8 +188,8 @@ class TritonCTS
188188
double computeInsertionDelay(const std::string& name,
189189
odb::dbInst* inst,
190190
odb::dbMTerm* mterm);
191-
void writeDummyLoadsToDb(Clock& clockNet,
192-
std::unordered_set<odb::dbInst*>& dummies);
191+
int writeDummyLoadsToDb(Clock& clockNet,
192+
std::unordered_set<odb::dbInst*>& dummies);
193193
bool computeIdealOutputCaps(Clock& clockNet);
194194
void findCandidateDummyCells(std::vector<sta::LibertyCell*>& dummyCandidates);
195195
odb::dbInst* insertDummyCell(

‎src/cts/src/TreeBuilder.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -221,6 +221,8 @@ class TreeBuilder
221221

222222
float getAveSinkArrival() const { return aveArrival_; }
223223
void setAveSinkArrival(float arrival) { aveArrival_ = arrival; }
224+
float getNDummies() const { return nDummies_; }
225+
void setNDummies(float nDummies) { nDummies_ = nDummies; }
224226
odb::dbInst* getTopBuffer() const { return topBuffer_; }
225227
void setTopBuffer(odb::dbInst* inst) { topBuffer_ = inst; }
226228
std::string getTopBufferName() const { return topBufferName_; }
@@ -256,6 +258,7 @@ class TreeBuilder
256258
insertionDelays_;
257259
TreeType type_ = TreeType::RegularTree;
258260
float aveArrival_ = 0.0;
261+
int nDummies_ = 0;
259262
odb::dbInst* topBuffer_ = nullptr;
260263
std::string topBufferName_;
261264
odb::dbNet* drivingNet_ = nullptr;

‎src/cts/src/TritonCTS.cpp‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -494,7 +494,8 @@ void TritonCTS::writeDataToDb()
494494
writeClockNDRsToDb(builder.get());
495495
}
496496
if (options_->dummyLoadEnabled()) {
497-
writeDummyLoadsToDb(builder->getClock(), clkDummies);
497+
int nDummies = writeDummyLoadsToDb(builder->getClock(), clkDummies);
498+
builder->setNDummies(nDummies);
498499
}
499500
}
500501

@@ -538,7 +539,8 @@ void TritonCTS::writeDataToDb()
538539
}
539540
logger_->info(CTS, 102, " Path depth {} - {}", minDepth, maxDepth);
540541
if (options_->dummyLoadEnabled()) {
541-
logger_->info(CTS, 207, " Leaf load cells {}", dummyLoadIndex_);
542+
logger_->info(
543+
CTS, 207, " Dummy loads inserted {}", builder->getNDummies());
542544
}
543545
}
544546
}
@@ -2122,20 +2124,21 @@ sta::LibertyCell* findBestDummyCell(
21222124
return bestCell;
21232125
}
21242126

2125-
void TritonCTS::writeDummyLoadsToDb(Clock& clockNet,
2126-
std::unordered_set<odb::dbInst*>& dummies)
2127+
int TritonCTS::writeDummyLoadsToDb(Clock& clockNet,
2128+
std::unordered_set<odb::dbInst*>& dummies)
21272129
{
21282130
// Traverse clock tree and compute ideal output caps for clock
21292131
// buffers in the same level
21302132
if (!computeIdealOutputCaps(clockNet)) {
21312133
// No cap adjustment is needed
2132-
return;
2134+
return 0;
21332135
}
21342136

21352137
// Find suitable candidate cells for dummy loads
21362138
std::vector<sta::LibertyCell*> dummyCandidates;
21372139
findCandidateDummyCells(dummyCandidates);
21382140

2141+
int nDummies = 0;
21392142
clockNet.forEachSubNet([&](ClockSubNet& subNet) {
21402143
subNet.forEachSink([&](ClockInst* inst) {
21412144
if (inst->isClockBuffer()
@@ -2145,6 +2148,7 @@ void TritonCTS::writeDummyLoadsToDb(Clock& clockNet,
21452148
= insertDummyCell(clockNet, inst, dummyCandidates);
21462149
if (dummyInst != nullptr) {
21472150
dummies.insert(dummyInst);
2151+
nDummies++;
21482152
}
21492153
}
21502154
});
@@ -2153,6 +2157,7 @@ void TritonCTS::writeDummyLoadsToDb(Clock& clockNet,
21532157
if (logger_->debugCheck(utl::CTS, "dummy load", 1)) {
21542158
printClockNetwork(clockNet);
21552159
}
2160+
return nDummies;
21562161
}
21572162

21582163
// Return true if any clock buffers need cap adjustment; false otherwise

‎src/cts/test/array.ok‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -103,13 +103,13 @@
103103
[INFO CTS-0100] Leaf buffers 103
104104
[INFO CTS-0101] Average sink wire length 9313.40 um
105105
[INFO CTS-0102] Path depth 16 - 17
106-
[INFO CTS-0207] Leaf load cells 4
106+
[INFO CTS-0207] Dummy loads inserted 0
107107
[INFO CTS-0098] Clock net "clk_regs"
108108
[INFO CTS-0099] Sinks 2254
109109
[INFO CTS-0100] Leaf buffers 227
110110
[INFO CTS-0101] Average sink wire length 4121.94 um
111111
[INFO CTS-0102] Path depth 17 - 17
112-
[INFO CTS-0207] Leaf load cells 4
112+
[INFO CTS-0207] Dummy loads inserted 4
113113
[INFO CTS-0033] Balancing latency for clock clk
114114
[INFO CTS-0036] inserted 3 delay buffers
115115
[INFO CTS-0037] Total number of delay buffers: 3

‎src/cts/test/array_ins_delay.ok‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -103,13 +103,13 @@
103103
[INFO CTS-0100] Leaf buffers 103
104104
[INFO CTS-0101] Average sink wire length 9313.40 um
105105
[INFO CTS-0102] Path depth 16 - 17
106-
[INFO CTS-0207] Leaf load cells 4
106+
[INFO CTS-0207] Dummy loads inserted 0
107107
[INFO CTS-0098] Clock net "clk_regs"
108108
[INFO CTS-0099] Sinks 2254
109109
[INFO CTS-0100] Leaf buffers 227
110110
[INFO CTS-0101] Average sink wire length 4121.94 um
111111
[INFO CTS-0102] Path depth 17 - 17
112-
[INFO CTS-0207] Leaf load cells 4
112+
[INFO CTS-0207] Dummy loads inserted 4
113113
[INFO CTS-0033] Balancing latency for clock clk
114114
[INFO CTS-0036] inserted 3 delay buffers
115115
[INFO CTS-0037] Total number of delay buffers: 3

‎src/cts/test/array_no_blockages.ok‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -102,13 +102,13 @@
102102
[INFO CTS-0100] Leaf buffers 103
103103
[INFO CTS-0101] Average sink wire length 9415.86 um
104104
[INFO CTS-0102] Path depth 16 - 17
105-
[INFO CTS-0207] Leaf load cells 4
105+
[INFO CTS-0207] Dummy loads inserted 0
106106
[INFO CTS-0098] Clock net "clk_regs"
107107
[INFO CTS-0099] Sinks 2254
108108
[INFO CTS-0100] Leaf buffers 227
109109
[INFO CTS-0101] Average sink wire length 4117.74 um
110110
[INFO CTS-0102] Path depth 17 - 17
111-
[INFO CTS-0207] Leaf load cells 4
111+
[INFO CTS-0207] Dummy loads inserted 4
112112
[INFO CTS-0033] Balancing latency for clock clk
113113
[INFO CTS-0036] inserted 4 delay buffers
114114
[INFO CTS-0037] Total number of delay buffers: 4

‎src/cts/test/array_repair_clock_nets.ok‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -103,13 +103,13 @@
103103
[INFO CTS-0100] Leaf buffers 103
104104
[INFO CTS-0101] Average sink wire length 9313.40 um
105105
[INFO CTS-0102] Path depth 16 - 17
106-
[INFO CTS-0207] Leaf load cells 4
106+
[INFO CTS-0207] Dummy loads inserted 0
107107
[INFO CTS-0098] Clock net "clk_regs"
108108
[INFO CTS-0099] Sinks 2254
109109
[INFO CTS-0100] Leaf buffers 227
110110
[INFO CTS-0101] Average sink wire length 4121.94 um
111111
[INFO CTS-0102] Path depth 17 - 17
112-
[INFO CTS-0207] Leaf load cells 4
112+
[INFO CTS-0207] Dummy loads inserted 4
113113
[INFO RSZ-0047] Found 38 long wires.
114114
[INFO RSZ-0048] Inserted 160 buffers in 38 nets.
115115
[INFO CTS-0033] Balancing latency for clock clk

‎src/cts/test/check_buffer_inference1.ok‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,5 +60,5 @@
6060
[INFO CTS-0100] Leaf buffers 29
6161
[INFO CTS-0101] Average sink wire length 129.19 um
6262
[INFO CTS-0102] Path depth 2 - 3
63-
[INFO CTS-0207] Leaf load cells 4
63+
[INFO CTS-0207] Dummy loads inserted 4
6464
Found 0 unconnected buffers.

‎src/cts/test/check_buffer_inference2.ok‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,5 +60,5 @@
6060
[INFO CTS-0100] Leaf buffers 29
6161
[INFO CTS-0101] Average sink wire length 129.19 um
6262
[INFO CTS-0102] Path depth 2 - 3
63-
[INFO CTS-0207] Leaf load cells 4
63+
[INFO CTS-0207] Dummy loads inserted 4
6464
Found 0 unconnected buffers.

‎src/cts/test/check_buffer_inference3.ok‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,5 +60,5 @@
6060
[INFO CTS-0100] Leaf buffers 29
6161
[INFO CTS-0101] Average sink wire length 129.19 um
6262
[INFO CTS-0102] Path depth 2 - 3
63-
[INFO CTS-0207] Leaf load cells 4
63+
[INFO CTS-0207] Dummy loads inserted 4
6464
Found 0 unconnected buffers.

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