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Merge pull request #8870 from The-OpenROAD-Project-staging/secure-new-slew-fix
Enhanced max slew fixing to remove large unfixed violations
2 parents ac5b1e0 + 9bccbcd commit c271c6f

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50 files changed

+2799
-2399
lines changed

‎src/cts/test/array.ok‎

Lines changed: 75 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -125,22 +125,22 @@ Dummys used:
125125
INV_X4: 1
126126
[INFO RSZ-0058] Using max wire length 693um.
127127
[INFO RSZ-0047] Found 41 long wires.
128-
[INFO RSZ-0048] Inserted 117 buffers in 41 nets.
128+
[INFO RSZ-0048] Inserted 165 buffers in 41 nets.
129129
Placement Analysis
130130
---------------------------------
131-
total displacement 4255.5 u
131+
total displacement 4186.7 u
132132
average displacement 1.3 u
133133
max displacement 143.4 u
134-
original HPWL 192636.5 u
135-
legalized HPWL 193564.6 u
134+
original HPWL 192698.4 u
135+
legalized HPWL 193625.0 u
136136
delta HPWL 0 %
137137

138138
Clock clk
139-
1.06 source latency inst_5_7/clk ^
140-
-1.20 target latency inst_6_7/clk ^
139+
1.03 source latency inst_5_4/clk ^
140+
-1.18 target latency inst_6_4/clk ^
141141
0.00 CRPR
142142
--------------
143-
-0.14 setup skew
143+
-0.15 setup skew
144144

145145
Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk)
146146
Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)
@@ -152,76 +152,76 @@ Path Type: max
152152
0.00 0.00 clock clk (rise edge)
153153
0.00 0.00 clock source latency
154154
0.00 0.00 ^ clk (in)
155-
0.04 0.04 ^ wire8/Z (BUF_X8)
156-
0.03 0.07 ^ wire7/Z (BUF_X16)
157-
0.06 0.13 ^ load_slew6/Z (BUF_X8)
158-
0.06 0.18 ^ wire5/Z (BUF_X16)
155+
0.04 0.04 ^ wire9/Z (BUF_X8)
156+
0.03 0.07 ^ wire8/Z (BUF_X16)
157+
0.06 0.13 ^ wire6/Z (BUF_X8)
158+
0.05 0.18 ^ wire5/Z (BUF_X16)
159159
0.05 0.23 ^ wire4/Z (BUF_X16)
160160
0.06 0.29 ^ wire3/Z (BUF_X32)
161161
0.06 0.34 ^ wire2/Z (BUF_X32)
162162
0.04 0.39 ^ wire1/Z (BUF_X32)
163163
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
164164
0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
165165
0.04 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
166-
0.04 0.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
166+
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
167167
0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
168168
0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
169169
0.03 0.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
170170
0.03 0.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
171171
0.03 0.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
172-
0.03 0.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
173-
0.04 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
172+
0.03 0.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
173+
0.04 0.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
174174
0.03 0.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
175175
0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
176176
0.03 0.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
177-
0.04 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
178-
0.05 1.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
179-
0.04 1.05 ^ wire10/Z (BUF_X8)
180-
0.04 1.10 ^ wire9/Z (BUF_X8)
181-
0.05 1.15 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
182-
0.00 1.15 ^ inst_1_1/clk (array_tile)
183-
0.21 1.36 ^ inst_1_1/e_out (array_tile)
184-
0.00 1.36 ^ inst_2_1/w_in (array_tile)
185-
1.36 data arrival time
177+
0.04 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
178+
0.05 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
179+
0.04 1.05 ^ wire14/Z (BUF_X8)
180+
0.05 1.10 ^ load_slew11/Z (BUF_X1)
181+
0.03 1.13 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
182+
0.00 1.13 ^ inst_1_1/clk (array_tile)
183+
0.21 1.35 ^ inst_1_1/e_out (array_tile)
184+
0.00 1.35 ^ inst_2_1/w_in (array_tile)
185+
1.35 data arrival time
186186

187187
5.00 5.00 clock clk (rise edge)
188188
0.00 5.00 clock source latency
189189
0.00 5.00 ^ clk (in)
190-
0.04 5.04 ^ wire8/Z (BUF_X8)
191-
0.03 5.07 ^ wire7/Z (BUF_X16)
192-
0.06 5.13 ^ load_slew6/Z (BUF_X8)
193-
0.06 5.18 ^ wire5/Z (BUF_X16)
190+
0.04 5.04 ^ wire9/Z (BUF_X8)
191+
0.03 5.07 ^ wire8/Z (BUF_X16)
192+
0.06 5.13 ^ wire6/Z (BUF_X8)
193+
0.05 5.18 ^ wire5/Z (BUF_X16)
194194
0.05 5.23 ^ wire4/Z (BUF_X16)
195195
0.06 5.29 ^ wire3/Z (BUF_X32)
196196
0.06 5.34 ^ wire2/Z (BUF_X32)
197197
0.04 5.39 ^ wire1/Z (BUF_X32)
198198
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
199199
0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
200200
0.04 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
201-
0.04 5.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
201+
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
202202
0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
203203
0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
204204
0.03 5.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
205205
0.03 5.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
206206
0.03 5.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
207-
0.03 5.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
208-
0.04 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
207+
0.03 5.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
208+
0.04 5.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
209209
0.03 5.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
210210
0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
211211
0.03 5.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
212-
0.04 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
213-
0.05 6.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
214-
0.04 6.05 ^ max_length12/Z (BUF_X8)
215-
0.04 6.08 ^ wire11/Z (BUF_X8)
216-
0.02 6.10 ^ inst_2_1/clk (array_tile)
217-
0.00 6.10 clock reconvergence pessimism
218-
-0.05 6.05 library setup time
219-
6.05 data required time
212+
0.04 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
213+
0.05 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
214+
0.04 6.04 ^ load_slew18/Z (BUF_X8)
215+
0.03 6.07 ^ load_slew16/Z (BUF_X1)
216+
0.00 6.07 ^ inst_2_1/clk (array_tile)
217+
0.00 6.07 clock reconvergence pessimism
218+
-0.05 6.02 library setup time
219+
6.02 data required time
220220
---------------------------------------------------------
221-
6.05 data required time
222-
-1.36 data arrival time
221+
6.02 data required time
222+
-1.35 data arrival time
223223
---------------------------------------------------------
224-
4.69 slack (MET)
224+
4.67 slack (MET)
225225

226226

227227
Startpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)
@@ -234,74 +234,75 @@ Path Type: max
234234
0.00 0.00 clock clk (rise edge)
235235
0.00 0.00 clock source latency
236236
0.00 0.00 ^ clk (in)
237-
0.04 0.04 ^ wire8/Z (BUF_X8)
238-
0.03 0.07 ^ wire7/Z (BUF_X16)
239-
0.06 0.13 ^ load_slew6/Z (BUF_X8)
240-
0.06 0.18 ^ wire5/Z (BUF_X16)
237+
0.04 0.04 ^ wire9/Z (BUF_X8)
238+
0.03 0.07 ^ wire8/Z (BUF_X16)
239+
0.06 0.13 ^ wire6/Z (BUF_X8)
240+
0.05 0.18 ^ wire5/Z (BUF_X16)
241241
0.05 0.23 ^ wire4/Z (BUF_X16)
242242
0.06 0.29 ^ wire3/Z (BUF_X32)
243243
0.06 0.34 ^ wire2/Z (BUF_X32)
244244
0.04 0.39 ^ wire1/Z (BUF_X32)
245245
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
246246
0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
247247
0.04 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
248-
0.04 0.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
248+
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
249249
0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
250250
0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
251251
0.03 0.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
252252
0.03 0.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
253253
0.03 0.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
254-
0.03 0.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
255-
0.04 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
254+
0.03 0.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
255+
0.04 0.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
256256
0.03 0.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
257257
0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
258258
0.03 0.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
259-
0.04 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
260-
0.05 1.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
261-
0.04 1.05 ^ max_length12/Z (BUF_X8)
262-
0.04 1.08 ^ wire11/Z (BUF_X8)
263-
0.02 1.10 ^ inst_2_1/clk (array_tile)
264-
0.21 1.32 ^ inst_2_1/e_out (array_tile)
265-
0.00 1.32 ^ inst_3_1/w_in (array_tile)
266-
1.32 data arrival time
259+
0.04 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
260+
0.05 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
261+
0.04 1.04 ^ load_slew18/Z (BUF_X8)
262+
0.03 1.07 ^ load_slew16/Z (BUF_X1)
263+
0.00 1.07 ^ inst_2_1/clk (array_tile)
264+
0.21 1.28 ^ inst_2_1/e_out (array_tile)
265+
0.00 1.28 ^ inst_3_1/w_in (array_tile)
266+
1.28 data arrival time
267267

268268
5.00 5.00 clock clk (rise edge)
269269
0.00 5.00 clock source latency
270270
0.00 5.00 ^ clk (in)
271-
0.04 5.04 ^ wire8/Z (BUF_X8)
272-
0.03 5.07 ^ wire7/Z (BUF_X16)
273-
0.06 5.13 ^ load_slew6/Z (BUF_X8)
274-
0.06 5.18 ^ wire5/Z (BUF_X16)
271+
0.04 5.04 ^ wire9/Z (BUF_X8)
272+
0.03 5.07 ^ wire8/Z (BUF_X16)
273+
0.06 5.13 ^ wire6/Z (BUF_X8)
274+
0.05 5.18 ^ wire5/Z (BUF_X16)
275275
0.05 5.23 ^ wire4/Z (BUF_X16)
276276
0.06 5.29 ^ wire3/Z (BUF_X32)
277277
0.06 5.34 ^ wire2/Z (BUF_X32)
278278
0.04 5.39 ^ wire1/Z (BUF_X32)
279279
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
280280
0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
281281
0.04 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
282-
0.04 5.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
282+
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
283283
0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
284284
0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
285285
0.03 5.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
286286
0.03 5.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
287287
0.03 5.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
288-
0.03 5.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
289-
0.04 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
288+
0.03 5.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
289+
0.04 5.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
290290
0.03 5.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
291291
0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
292292
0.03 5.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
293-
0.04 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
294-
0.05 6.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
295-
0.04 6.05 ^ max_length12/Z (BUF_X8)
296-
0.05 6.10 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
297-
0.00 6.10 ^ inst_3_1/clk (array_tile)
298-
0.00 6.10 clock reconvergence pessimism
299-
-0.05 6.05 library setup time
300-
6.05 data required time
293+
0.04 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
294+
0.05 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
295+
0.04 6.04 ^ load_slew18/Z (BUF_X8)
296+
0.04 6.08 ^ wire17/Z (BUF_X4)
297+
0.04 6.12 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
298+
0.00 6.12 ^ inst_3_1/clk (array_tile)
299+
0.00 6.12 clock reconvergence pessimism
300+
-0.05 6.07 library setup time
301+
6.07 data required time
301302
---------------------------------------------------------
302-
6.05 data required time
303-
-1.32 data arrival time
303+
6.07 data required time
304+
-1.28 data arrival time
304305
---------------------------------------------------------
305-
4.73 slack (MET)
306+
4.79 slack (MET)
306307

307308

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