We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
2 parents 25e4ab5 + babc567 commit c47bc3bCopy full SHA for c47bc3b
src/rcx/src/extBenchDB.cpp
@@ -435,8 +435,8 @@ uint extMain::benchVerilog_assign(FILE* fp)
435
}
436
uint extRCModel::benchDB_WS(extMainOptions* opt, extMeasure* measure)
437
{
438
- Ath__array1D<double>* widthTable = new Ath__array1D<double>(4);
439
- Ath__array1D<double>* spaceTable = new Ath__array1D<double>(4);
+ auto widthTable = std::make_unique<Ath__array1D<double>>(4);
+ auto spaceTable = std::make_unique<Ath__array1D<double>>(4);
440
Ath__array1D<double>* wTable = &opt->_widthTable;
441
Ath__array1D<double>* sTable = &opt->_spaceTable;
442
Ath__array1D<double>* gTable = &opt->_gridTable;
0 commit comments