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Merge pull request #8186 from The-OpenROAD-Project-staging/rcx-leak
rcx: fix ASAN leak in extRCModel::benchDB_WS
2 parents 25e4ab5 + babc567 commit c47bc3b

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src/rcx/src/extBenchDB.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -435,8 +435,8 @@ uint extMain::benchVerilog_assign(FILE* fp)
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}
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uint extRCModel::benchDB_WS(extMainOptions* opt, extMeasure* measure)
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{
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Ath__array1D<double>* widthTable = new Ath__array1D<double>(4);
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Ath__array1D<double>* spaceTable = new Ath__array1D<double>(4);
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auto widthTable = std::make_unique<Ath__array1D<double>>(4);
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auto spaceTable = std::make_unique<Ath__array1D<double>>(4);
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Ath__array1D<double>* wTable = &opt->_widthTable;
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Ath__array1D<double>* sTable = &opt->_spaceTable;
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Ath__array1D<double>* gTable = &opt->_gridTable;

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