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eder-matheuseder-matheus
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Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenROAD into est_via_res
2 parents ab6d99d + 88adbed commit c7ac7fb

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27 files changed

+2576
-179
lines changed

27 files changed

+2576
-179
lines changed

‎src/cts/test/BUILD‎

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@@ -7,10 +7,14 @@ COMPULSORY_TESTS = [
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"array",
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"array_ins_delay",
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"array_no_blockages",
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"array_repair_clock_nets",
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"balance_levels",
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"check_buffers",
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"check_buffers_blockages",
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"check_buffers_blockages_merge",
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"check_buffer_inference1",
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"check_buffer_inference2",
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"check_buffer_inference3",
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"check_charBuf",
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"check_max_fanout1",
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"check_max_fanout2",
@@ -20,6 +24,7 @@ COMPULSORY_TESTS = [
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"find_clock_pad",
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"hier_insertion_delay",
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"insertion_delay",
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"inverters",
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"lvt_lib",
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"max_cap",
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"no_clocks",
@@ -76,6 +81,9 @@ filegroup(
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"Nangate45/fakeram45_64x96.lef",
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"Nangate45/fakeram45_64x96.lib",
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"Nangate45/work_around_yosys/cells.v",
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"ModNangate45/ModNangate45_typ.lib",
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"ModNangate45/ModNangate45.lef",
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"check_buffers.def",
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"array_dummy.tcl",
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"array_full_flow.tcl",
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"array_tile.lef",

‎src/dbSta/test/BUILD‎

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@@ -5,6 +5,7 @@ load("//test:regression.bzl", "regression_test")
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# From CMakeLists.txt or_integration_tests(TESTS
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COMPULSORY_TESTS = [
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"block_sta1",
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"check_axioms",
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"clock_pin",
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"constant1",
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"find_clks1",
@@ -29,6 +30,7 @@ COMPULSORY_TESTS = [
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"read_verilog8",
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"read_verilog9",
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"read_verilog10",
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"read_verilog10_no_prop",
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"read_verilog11",
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"readdb_hier",
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"report_cell_usage",
@@ -38,6 +40,7 @@ COMPULSORY_TESTS = [
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"report_cell_usage_physical_only",
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"report_json1",
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"report_timing_histogram",
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"report_logic_depth_histogram",
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"sdc_get1",
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"sdc_names1",
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"sdc_names2",

‎src/drt/test/BUILD‎

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@@ -16,7 +16,7 @@ COMPULSORY_TESTS = [
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"ta_pin_aligned",
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"top_level_term",
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"top_level_term2",
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"via_access_layer"
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"via_access_layer",
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]
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# Disabled in CMakeLists.txt

‎src/exa/test/BUILD‎

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@@ -0,0 +1,30 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2022-2025, The OpenROAD Authors
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load("//test:regression.bzl", "regression_test")
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TESTS = [
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"basic",
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]
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filegroup(
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name = "test_resources",
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# overly broad glob, could be refined later, but
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# symlinks are cheap and OpenROAD binary changes, the common
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# use case is that all tests have to be re-run.
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srcs = glob(
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["**/*"],
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exclude = [
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test + "." + ext
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for test in TESTS
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for ext in [
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"tcl",
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"py",
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]
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],
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),
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)
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[regression_test(
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name = test_name,
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data = [":test_resources"],
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) for test_name in TESTS]

‎src/gpl/test/clust01.ok‎

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@@ -1,4 +1,4 @@
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[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 24 layers, 9 vias
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[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 30 layers, 9 vias
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[INFO ODB-0227] LEF file: ./SingleBit/asap7sc7p5t_28_L_1x_220121a.lef, created 212 library cells
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[INFO ODB-0227] LEF file: ./2BitTrayH2/asap7sc7p5t_DFFHQNV2X.lef, created 9 library cells
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[INFO ODB-0394] Duplicate site asap7sc7p5t_pg in asap7sc7p5t_DFFHQNV4X already seen in asap7sc7p5t_DFFHQNV2X

‎src/gpl/test/clust02.ok‎

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[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 24 layers, 9 vias
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[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 30 layers, 9 vias
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[INFO ODB-0227] LEF file: ./SingleBit/asap7sc7p5t_28_L_1x_220121a.lef, created 212 library cells
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[INFO ODB-0227] LEF file: ./2BitTrayH2/asap7sc7p5t_DFFHQNV2X.lef, created 9 library cells
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[INFO ODB-0394] Duplicate site asap7sc7p5t_pg in asap7sc7p5t_DFFHQNV4X already seen in asap7sc7p5t_DFFHQNV2X

‎src/gpl/test/clust03.ok‎

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[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 24 layers, 9 vias
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[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 30 layers, 9 vias
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[INFO ODB-0227] LEF file: ./SingleBit/asap7sc7p5t_28_L_1x_220121a.lef, created 212 library cells
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[INFO IFP-0001] Added 370 rows of 1851 site asap7sc7p5t.
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[INFO GPL-0137] No tray found for group of 100 flop instances containing DFFHQNx1_ASAP7_75t_L

‎src/gpl/test/convergence01.ok‎

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@@ -8,7 +8,7 @@
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[WARNING STA-1212] asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
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[WARNING STA-1212] asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
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[WARNING STA-1212] asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
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[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 24 layers, 9 vias
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[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 30 layers, 9 vias
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[INFO ODB-0227] LEF file: ./asap7/asap7sc7p5t_28_R_1x_220121a.lef, created 212 library cells
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[INFO ODB-0128] Design: Element
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[INFO ODB-0130] Created 65 pins.

‎src/gpl/test/nograd01.ok‎

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[INFO ODB-0227] LEF file: asap7/asap7_tech_1x_201209.lef, created 24 layers, 9 vias
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[INFO ODB-0227] LEF file: asap7/asap7_tech_1x_201209.lef, created 30 layers, 9 vias
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[INFO ODB-0227] LEF file: asap7/asap7sc7p5t_28_R_1x_220121a.lef, created 212 library cells
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[INFO ODB-0128] Design: calibrate_rc
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[INFO ODB-0130] Created 12 pins.

‎src/grt/test/BUILD‎

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@@ -48,6 +48,8 @@ TESTS = [
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"read_segments_error1",
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"read_segments_error2",
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"read_segments_error3",
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"read_segments_error4",
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"read_segments_error5",
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"region_adjustment",
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"remove_buffers1",
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"remove_buffers2",

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