Skip to content

Commit c9cc993

Browse files
authored
Merge pull request #8502 from luis201420/cts_add_option_skip_nets
Cts: Add option to skip nets
2 parents 7ab952f + 2d70ffe commit c9cc993

File tree

9 files changed

+254
-5
lines changed

9 files changed

+254
-5
lines changed

src/cts/README.md

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,7 @@ set_cts_config
151151
[-sink_clustering_levels levels]
152152
[-sink_clustering_max_diameter max_diameter]
153153
[-sink_clustering_size cluster_size]
154+
[-skip_nets <list_of_clk_nets_to_skip>]
154155
[-tree_buf <buf>]
155156
[-wire_unit wire_unit]
156157
```
@@ -176,6 +177,7 @@ set_cts_config
176177
| `-sink_clustering_max_diameter` | Specifies maximum diameter (in microns) of sink cluster for the register tree. The allowed values are integers `[0, MAX_INT]`. If this is not specified the diameter will be automatically chosen between `50, 100 or 200`, based on the tree buffer max cap. |
177178
| `-sink_clustering_size` | Specifies the maximum number of sinks per cluster for the register tree. The allowed values are integers `[0, MAX_INT]`. If this is not specified the size will be automatically chosen between `10, 20 or 30` based on the tree buffer max cap. |
178179
| `-sink_clustering_levels` | ... |
180+
| `-skip_nets` | Tcl list containing the clock nets to be skipped (e.g. `{net1, net2}`). If the net is a root clock net, the whole clock is skipped, otherwise only the subnet specified is skipped. |
179181
| `-wire_unit` | Minimum unit distance between buffers for a specific wire. If this parameter is omitted, the code gets the value from ten times the height of `-root_buffer`. |
180182

181183
### Report CTS configuration
@@ -208,6 +210,7 @@ reset_cts_config
208210
[-sink_clustering_levels]
209211
[-sink_clustering_max_diameter]
210212
[-sink_clustering_size]
213+
[-skip_nets]
211214
[-tree_buf]
212215
[-wire_unit]
213216
```

src/cts/src/CtsOptions.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,17 @@ class CtsOptions : public odb::dbBlockCallBackObj
125125
clockNetsObjs_ = nets;
126126
}
127127
std::vector<odb::dbNet*> getClockNetsObjs() const { return clockNetsObjs_; }
128+
void setSkipNets(odb::dbNet* nets) { skipNets_.push_back(nets); }
129+
std::vector<odb::dbNet*> getSkipNets() const { return skipNets_; }
130+
std::string getSkipNetsToString() const
131+
{
132+
std::ostringstream skip_nets_names;
133+
for (const odb::dbNet* db_net : skipNets_) {
134+
skip_nets_names << db_net->getConstName() << " ";
135+
}
136+
return skip_nets_names.str();
137+
}
138+
void resetSkipNets() { skipNets_.clear(); }
128139
void setMetricsFile(const std::string& metricFile)
129140
{
130141
metricFile_ = metricFile;
@@ -394,6 +405,7 @@ class CtsOptions : public odb::dbBlockCallBackObj
394405
unsigned numStaticLayers_ = 0;
395406
std::vector<std::string> bufferList_;
396407
std::vector<odb::dbNet*> clockNetsObjs_;
408+
std::vector<odb::dbNet*> skipNets_;
397409
utl::Logger* logger_ = nullptr;
398410
stt::SteinerTreeBuilder* sttBuilder_ = nullptr;
399411
bool obsAware_ = true;

src/cts/src/TritonCTS.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -302,9 +302,16 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet,
302302
TreeBuilder* parent)
303303
{
304304
TreeBuilder* clockBuilder = nullptr;
305+
std::vector<odb::dbNet*> skipNets = options_->getSkipNets();
305306
if (driverNet->isSpecial()) {
306307
logger_->info(
307308
CTS, 116, "Special net \"{}\" skipped.", driverNet->getName());
309+
} else if (std::find(skipNets.begin(), skipNets.end(), driverNet)
310+
!= skipNets.end()) {
311+
logger_->warn(CTS,
312+
44,
313+
"Skipping net {}, specified by the user...",
314+
driverNet->getName());
308315
} else {
309316
clockBuilder = initClock(driverNet, clkInputNet, sdcClockName, parent);
310317
}
@@ -1959,12 +1966,20 @@ bool TritonCTS::masterExists(const std::string& master) const
19591966
void TritonCTS::findClockRoots(sta::Clock* clk,
19601967
std::set<odb::dbNet*>& clockNets)
19611968
{
1969+
std::vector<odb::dbNet*> skipNets = options_->getSkipNets();
19621970
for (const sta::Pin* pin : clk->leafPins()) {
19631971
odb::dbITerm* instTerm;
19641972
odb::dbBTerm* port;
19651973
odb::dbModITerm* moditerm;
19661974
network_->staToDb(pin, instTerm, port, moditerm);
19671975
odb::dbNet* net = instTerm ? instTerm->getNet() : port->getNet();
1976+
if (std::find(skipNets.begin(), skipNets.end(), net) != skipNets.end()) {
1977+
logger_->warn(CTS,
1978+
42,
1979+
"Skipping root net {}, specified by the user...",
1980+
net->getName());
1981+
continue;
1982+
}
19681983
clockNets.insert(net);
19691984
}
19701985
}

src/cts/src/TritonCTS.i

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,12 @@ set_clock_nets(const char* names)
222222
return getTritonCts()->setClockNets(names);
223223
}
224224

225+
void
226+
set_skip_clock_nets(odb::dbNet* net)
227+
{
228+
getTritonCts()->getParms()->setSkipNets(net);
229+
}
230+
225231
void
226232
set_buffer_list(const char* buffers)
227233
{
@@ -376,6 +382,11 @@ get_sink_clustering_size()
376382
return getTritonCts()->getParms()->getSinkClusteringSize();
377383
}
378384

385+
std::string
386+
get_skip_nets()
387+
{
388+
return getTritonCts()->getParms()->getSkipNetsToString();
389+
}
379390
std::string
380391
get_tree_buf()
381392
{
@@ -479,6 +490,11 @@ reset_sink_clustering_size()
479490
getTritonCts()->getParms()->resetSinkClusteringSize();
480491
}
481492
void
493+
reset_skip_nets()
494+
{
495+
getTritonCts()->getParms()->resetSkipNets();
496+
}
497+
void
482498
reset_tree_buf()
483499
{
484500
getTritonCts()->getParms()->resetTreeBuffer();

src/cts/src/TritonCTS.tcl

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ sta::define_cmd_args "set_cts_config" {[-apply_ndr strategy] \
5252
[-sink_clustering_levels levels] \
5353
[-sink_clustering_max_diameter] \
5454
[-sink_clustering_size] \
55+
[-skip_nets] \
5556
[-tree_buf buf] \
5657
[-wire_unit unit]
5758
}
@@ -60,8 +61,8 @@ proc set_cts_config { args } {
6061
keys {-apply_ndr -branching_point_buffers_distance -buf_list -clustering_exponent \
6162
-clustering_unbalance_ratio -delay_buffer_derate -distance_between_buffers \
6263
-library -macro_clustering_max_diameter -macro_clustering_size \
63-
-num_static_layers -sink_buffer_max_cap_derate -sink_clustering_levels -root_buf\
64-
-sink_clustering_max_diameter -sink_clustering_size -tree_buf -wire_unit} \
64+
-num_static_layers -sink_buffer_max_cap_derate -sink_clustering_levels -root_buf \
65+
-sink_clustering_max_diameter -sink_clustering_size -skip_nets -tree_buf -wire_unit} \
6566
flags {}
6667

6768
sta::check_argc_eq0 "set_cts_config" $args
@@ -136,6 +137,12 @@ proc set_cts_config { args } {
136137
set size $keys(-sink_clustering_size)
137138
cts::set_sink_clustering_size $size
138139
}
140+
if { [info exists keys(-skip_nets)] } {
141+
foreach net [get_nets $keys(-skip_nets)] {
142+
set db_net [sta::sta_to_db_net $net]
143+
cts::set_skip_clock_nets $db_net
144+
}
145+
}
139146
if { [info exists keys(-tree_buf)] } {
140147
set buf $keys(-tree_buf)
141148
cts::set_tree_buf $buf
@@ -186,6 +193,10 @@ proc report_cts_config { args } {
186193
set sink_clustering_levels [cts::get_sink_clustering_levels]
187194
set sink_max_diameter [cts::get_sink_clustering_max_diameter]
188195
set sink_cluster_size [cts::get_sink_clustering_size]
196+
set skip_nets_list [cts::get_skip_nets]
197+
if { $skip_nets_list eq "" } {
198+
set skip_nets_list "undefined"
199+
}
189200
set tree_buffer [cts::get_tree_buf]
190201
if { $tree_buffer eq "" } {
191202
set tree_buffer "undefined"
@@ -211,6 +222,7 @@ proc report_cts_config { args } {
211222
puts "-sink_clustering_levels: $sink_clustering_levels"
212223
puts "-sink_clustering_max_diameter: $sink_max_diameter"
213224
puts "-sink_clustering_size: $sink_cluster_size"
225+
puts "-skip_nets: $skip_nets_list"
214226
puts "-tree_buf: $tree_buffer"
215227
puts "-wire_unit: $wire_segment_unit"
216228
puts "****'***************************************"
@@ -232,6 +244,7 @@ sta::define_cmd_args "reset_cts_config" {[-apply_ndr] \
232244
[-sink_clustering_levels] \
233245
[-sink_clustering_max_diameter] \
234246
[-sink_clustering_size] \
247+
[-skip_nets] \
235248
[-tree_buf] \
236249
[-wire_unit]}
237250

@@ -242,7 +255,7 @@ proc reset_cts_config { args } {
242255
-clustering_unbalance_ratio -delay_buffer_derate -distance_between_buffers \
243256
-library -macro_clustering_max_diameter -macro_clustering_size \
244257
-num_static_layers -root_buf -sink_buffer_max_cap_derate -sink_clustering_levels \
245-
-sink_clustering_max_diameter -sink_clustering_size -tree_buf -wire_unit}
258+
-sink_clustering_max_diameter -sink_clustering_size -skip_nets -tree_buf -wire_unit}
246259

247260
set reset_all [expr { [array size flags] == 0 }]
248261

@@ -310,13 +323,17 @@ proc reset_cts_config { args } {
310323
cts::reset_sink_clustering_size
311324
utl::info CTS 226 "Sink clustering size has been removed."
312325
}
326+
if { $reset_all || [info exists flags(-skip_nets)] } {
327+
cts::reset_skip_nets
328+
utl::info CTS 227 "Skip nets has been removed."
329+
}
313330
if { $reset_all || [info exists flags(-tree_buf)] } {
314331
cts::reset_tree_buf
315-
utl::info CTS 227 "Tree buffer has been removed."
332+
utl::info CTS 228 "Tree buffer has been removed."
316333
}
317334
if { $reset_all || [info exists flags(-wire_unit)] } {
318335
cts::reset_wire_segment_distance_unit
319-
utl::info CTS 228 "Wire segment unit has been removed."
336+
utl::info CTS 229 "Wire segment unit has been removed."
320337
}
321338
}
322339

src/cts/test/BUILD

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ COMPULSORY_TESTS = [
4242
"simple_test_clustered",
4343
"simple_test_clustered_max_cap",
4444
"simple_test_hier",
45+
"skip_nets",
4546
"twice",
4647
]
4748

src/cts/test/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ or_integration_tests(
4343
simple_test_clustered
4444
simple_test_clustered_max_cap
4545
simple_test_hier
46+
skip_nets
4647
twice
4748
)
4849

src/cts/test/skip_nets.ok

Lines changed: 160 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,160 @@
1+
[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
2+
[INFO ODB-0128] Design: multi_sink
3+
[INFO ODB-0130] Created 1 pins.
4+
[INFO ODB-0131] Created 291 components and 1743 component-terminals.
5+
[INFO ODB-0133] Created 4 nets and 294 connections.
6+
*******************************************
7+
CTS config:
8+
-apply_ndr: HALF
9+
-buf_list: CLKBUF_X3
10+
-branching_point_buffers_distance: 480000
11+
-clustering_exponent: 4
12+
-clustering_unbalance_ratio: 0.6
13+
-delay_buffer_derate: 1.0
14+
-distance_between_buffers: 200000
15+
-library: undefined
16+
-macro_clustering_max_diameter: 50.0
17+
-macro_clustering_size: 4
18+
-num_static_layers: 1
19+
-root_buf: CLKBUF_X3
20+
-sink_buffer_max_cap_derate: 0.01
21+
-sink_clustering_levels: 0
22+
-sink_clustering_max_diameter: 50.0
23+
-sink_clustering_size: 20
24+
-skip_nets: gclk1 gclk3
25+
-tree_buf: undefined
26+
-wire_unit: 20
27+
****'***************************************
28+
[INFO CTS-0050] Root buffer is CLKBUF_X3.
29+
[INFO CTS-0051] Sink buffer is CLKBUF_X3.
30+
[INFO CTS-0052] The following clock buffers will be used for CTS:
31+
CLKBUF_X3
32+
[INFO CTS-0049] Characterization buffer is CLKBUF_X3.
33+
[INFO CTS-0007] Net "clk" found for clock "clk".
34+
[INFO CTS-0011] Clock net "clk" for macros has 2 sinks.
35+
[INFO CTS-0011] Clock net "clk_regs" for registers has 144 sinks.
36+
[WARNING CTS-0044] Skipping net gclk1, specified by the user...
37+
[INFO CTS-0010] Clock net "gclk2" has 36 sinks.
38+
[WARNING CTS-0044] Skipping net gclk3, specified by the user...
39+
[INFO CTS-0008] TritonCTS found 3 clock nets.
40+
[INFO CTS-0097] Characterization used 1 buffer(s) types.
41+
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
42+
[INFO CTS-0027] Generating H-Tree topology for net clk.
43+
[INFO CTS-0028] Total number of sinks: 2.
44+
[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 50.0 um.
45+
[INFO CTS-0030] Number of static layers: 1.
46+
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
47+
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
48+
[INFO CTS-0023] Original sink region: [(53595, 151620), (147835, 166180)].
49+
[INFO CTS-0024] Normalized sink region: [(3.82821, 10.83), (10.5596, 11.87)].
50+
[INFO CTS-0025] Width: 6.7314.
51+
[INFO CTS-0026] Height: 1.0400.
52+
Level 1
53+
Direction: Horizontal
54+
Sinks per sub-region: 1
55+
Sub-region size: 3.3657 X 1.0400
56+
[INFO CTS-0034] Segment length (rounded): 1.
57+
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
58+
[INFO CTS-0035] Number of sinks covered: 2.
59+
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
60+
[INFO CTS-0027] Generating H-Tree topology for net clk_regs.
61+
[INFO CTS-0028] Total number of sinks: 144.
62+
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
63+
[INFO CTS-0030] Number of static layers: 1.
64+
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
65+
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
66+
[INFO CTS-0023] Original sink region: [(8930, 7170), (196650, 85570)].
67+
[INFO CTS-0024] Normalized sink region: [(0.637857, 0.512143), (14.0464, 6.11214)].
68+
[INFO CTS-0025] Width: 13.4086.
69+
[INFO CTS-0026] Height: 5.6000.
70+
Level 1
71+
Direction: Horizontal
72+
Sinks per sub-region: 72
73+
Sub-region size: 6.7043 X 5.6000
74+
[INFO CTS-0034] Segment length (rounded): 4.
75+
Level 2
76+
Direction: Vertical
77+
Sinks per sub-region: 36
78+
Sub-region size: 6.7043 X 2.8000
79+
[INFO CTS-0034] Segment length (rounded): 1.
80+
Level 3
81+
Direction: Horizontal
82+
Sinks per sub-region: 18
83+
Sub-region size: 3.3521 X 2.8000
84+
[INFO CTS-0034] Segment length (rounded): 1.
85+
Level 4
86+
Direction: Vertical
87+
Sinks per sub-region: 9
88+
Sub-region size: 3.3521 X 1.4000
89+
[INFO CTS-0034] Segment length (rounded): 1.
90+
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
91+
[INFO CTS-0035] Number of sinks covered: 144.
92+
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
93+
[INFO CTS-0027] Generating H-Tree topology for net gclk2.
94+
[INFO CTS-0028] Total number of sinks: 36.
95+
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
96+
[INFO CTS-0030] Number of static layers: 1.
97+
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
98+
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
99+
[INFO CTS-0023] Original sink region: [(8930, 96770), (97850, 130370)].
100+
[INFO CTS-0024] Normalized sink region: [(0.637857, 6.91214), (6.98929, 9.31214)].
101+
[INFO CTS-0025] Width: 6.3514.
102+
[INFO CTS-0026] Height: 2.4000.
103+
Level 1
104+
Direction: Horizontal
105+
Sinks per sub-region: 18
106+
Sub-region size: 3.1757 X 2.4000
107+
[INFO CTS-0034] Segment length (rounded): 1.
108+
Level 2
109+
Direction: Vertical
110+
Sinks per sub-region: 9
111+
Sub-region size: 3.1757 X 1.2000
112+
[INFO CTS-0034] Segment length (rounded): 1.
113+
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
114+
[INFO CTS-0035] Number of sinks covered: 36.
115+
[INFO CTS-0018] Created 3 clock buffers.
116+
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
117+
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
118+
[INFO CTS-0015] Created 3 clock nets.
119+
[INFO CTS-0016] Fanout distribution for the current clock = 1:2..
120+
[INFO CTS-0017] Max level of the clock tree: 1.
121+
[INFO CTS-0018] Created 17 clock buffers.
122+
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
123+
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
124+
[INFO CTS-0015] Created 17 clock nets.
125+
[INFO CTS-0016] Fanout distribution for the current clock = 6:1, 7:3, 8:2, 9:4, 10:2, 11:3, 12:1..
126+
[INFO CTS-0017] Max level of the clock tree: 4.
127+
[INFO CTS-0018] Created 5 clock buffers.
128+
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
129+
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
130+
[INFO CTS-0015] Created 5 clock nets.
131+
[INFO CTS-0016] Fanout distribution for the current clock = 8:1, 9:2, 10:1..
132+
[INFO CTS-0017] Max level of the clock tree: 2.
133+
[INFO CTS-0098] Clock net "clk"
134+
[INFO CTS-0099] Sinks 3
135+
[INFO CTS-0100] Leaf buffers 0
136+
[INFO CTS-0101] Average sink wire length 57.59 um
137+
[INFO CTS-0102] Path depth 2 - 2
138+
[INFO CTS-0207] Leaf load cells 18
139+
[INFO CTS-0098] Clock net "clk_regs"
140+
[INFO CTS-0099] Sinks 159
141+
[INFO CTS-0100] Leaf buffers 0
142+
[INFO CTS-0101] Average sink wire length 45.22 um
143+
[INFO CTS-0102] Path depth 2 - 2
144+
[INFO CTS-0207] Leaf load cells 18
145+
[INFO CTS-0098] Clock net "gclk2"
146+
[INFO CTS-0099] Sinks 39
147+
[INFO CTS-0100] Leaf buffers 0
148+
[INFO CTS-0101] Average sink wire length 29.38 um
149+
[INFO CTS-0102] Path depth 2 - 2
150+
[INFO CTS-0207] Leaf load cells 18
151+
[DEBUG CTS-insertion delay] top buffer delay for macro tree clkbuf_0_clk is 2.666e-11
152+
[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_regs_0_clk is 2.480e-11
153+
[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_0_gclk2 is 3.492e-11
154+
[INFO CTS-0033] Balancing latency for clock clk
155+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (100608 169407)
156+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (101216 138954)
157+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_clk is inserted at (101824 108501)
158+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_clk is inserted at (102432 78048)
159+
[INFO CTS-0036] inserted 4 delay buffers
160+
[INFO CTS-0037] Total number of delay buffers: 4

0 commit comments

Comments
 (0)