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| 1 | +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells |
| 2 | +[INFO ODB-0128] Design: multi_sink |
| 3 | +[INFO ODB-0130] Created 1 pins. |
| 4 | +[INFO ODB-0131] Created 291 components and 1743 component-terminals. |
| 5 | +[INFO ODB-0133] Created 4 nets and 294 connections. |
| 6 | +******************************************* |
| 7 | +CTS config: |
| 8 | +-apply_ndr: HALF |
| 9 | +-buf_list: CLKBUF_X3 |
| 10 | +-branching_point_buffers_distance: 480000 |
| 11 | +-clustering_exponent: 4 |
| 12 | +-clustering_unbalance_ratio: 0.6 |
| 13 | +-delay_buffer_derate: 1.0 |
| 14 | +-distance_between_buffers: 200000 |
| 15 | +-library: undefined |
| 16 | +-macro_clustering_max_diameter: 50.0 |
| 17 | +-macro_clustering_size: 4 |
| 18 | +-num_static_layers: 1 |
| 19 | +-root_buf: CLKBUF_X3 |
| 20 | +-sink_buffer_max_cap_derate: 0.01 |
| 21 | +-sink_clustering_levels: 0 |
| 22 | +-sink_clustering_max_diameter: 50.0 |
| 23 | +-sink_clustering_size: 20 |
| 24 | +-skip_nets: gclk1 gclk3 |
| 25 | +-tree_buf: undefined |
| 26 | +-wire_unit: 20 |
| 27 | +****'*************************************** |
| 28 | +[INFO CTS-0050] Root buffer is CLKBUF_X3. |
| 29 | +[INFO CTS-0051] Sink buffer is CLKBUF_X3. |
| 30 | +[INFO CTS-0052] The following clock buffers will be used for CTS: |
| 31 | + CLKBUF_X3 |
| 32 | +[INFO CTS-0049] Characterization buffer is CLKBUF_X3. |
| 33 | +[INFO CTS-0007] Net "clk" found for clock "clk". |
| 34 | +[INFO CTS-0011] Clock net "clk" for macros has 2 sinks. |
| 35 | +[INFO CTS-0011] Clock net "clk_regs" for registers has 144 sinks. |
| 36 | +[WARNING CTS-0044] Skipping net gclk1, specified by the user... |
| 37 | +[INFO CTS-0010] Clock net "gclk2" has 36 sinks. |
| 38 | +[WARNING CTS-0044] Skipping net gclk3, specified by the user... |
| 39 | +[INFO CTS-0008] TritonCTS found 3 clock nets. |
| 40 | +[INFO CTS-0097] Characterization used 1 buffer(s) types. |
| 41 | +[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used. |
| 42 | +[INFO CTS-0027] Generating H-Tree topology for net clk. |
| 43 | +[INFO CTS-0028] Total number of sinks: 2. |
| 44 | +[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 50.0 um. |
| 45 | +[INFO CTS-0030] Number of static layers: 1. |
| 46 | +[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). |
| 47 | +[INFO CTS-0021] Distance between buffers: 7 units (100 um). |
| 48 | +[INFO CTS-0023] Original sink region: [(53595, 151620), (147835, 166180)]. |
| 49 | +[INFO CTS-0024] Normalized sink region: [(3.82821, 10.83), (10.5596, 11.87)]. |
| 50 | +[INFO CTS-0025] Width: 6.7314. |
| 51 | +[INFO CTS-0026] Height: 1.0400. |
| 52 | + Level 1 |
| 53 | + Direction: Horizontal |
| 54 | + Sinks per sub-region: 1 |
| 55 | + Sub-region size: 3.3657 X 1.0400 |
| 56 | +[INFO CTS-0034] Segment length (rounded): 1. |
| 57 | +[INFO CTS-0032] Stop criterion found. Max number of sinks is 15. |
| 58 | +[INFO CTS-0035] Number of sinks covered: 2. |
| 59 | +[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used. |
| 60 | +[INFO CTS-0027] Generating H-Tree topology for net clk_regs. |
| 61 | +[INFO CTS-0028] Total number of sinks: 144. |
| 62 | +[INFO CTS-0090] Sinks will be clustered based on buffer max cap. |
| 63 | +[INFO CTS-0030] Number of static layers: 1. |
| 64 | +[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). |
| 65 | +[INFO CTS-0021] Distance between buffers: 7 units (100 um). |
| 66 | +[INFO CTS-0023] Original sink region: [(8930, 7170), (196650, 85570)]. |
| 67 | +[INFO CTS-0024] Normalized sink region: [(0.637857, 0.512143), (14.0464, 6.11214)]. |
| 68 | +[INFO CTS-0025] Width: 13.4086. |
| 69 | +[INFO CTS-0026] Height: 5.6000. |
| 70 | + Level 1 |
| 71 | + Direction: Horizontal |
| 72 | + Sinks per sub-region: 72 |
| 73 | + Sub-region size: 6.7043 X 5.6000 |
| 74 | +[INFO CTS-0034] Segment length (rounded): 4. |
| 75 | + Level 2 |
| 76 | + Direction: Vertical |
| 77 | + Sinks per sub-region: 36 |
| 78 | + Sub-region size: 6.7043 X 2.8000 |
| 79 | +[INFO CTS-0034] Segment length (rounded): 1. |
| 80 | + Level 3 |
| 81 | + Direction: Horizontal |
| 82 | + Sinks per sub-region: 18 |
| 83 | + Sub-region size: 3.3521 X 2.8000 |
| 84 | +[INFO CTS-0034] Segment length (rounded): 1. |
| 85 | + Level 4 |
| 86 | + Direction: Vertical |
| 87 | + Sinks per sub-region: 9 |
| 88 | + Sub-region size: 3.3521 X 1.4000 |
| 89 | +[INFO CTS-0034] Segment length (rounded): 1. |
| 90 | +[INFO CTS-0032] Stop criterion found. Max number of sinks is 15. |
| 91 | +[INFO CTS-0035] Number of sinks covered: 144. |
| 92 | +[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used. |
| 93 | +[INFO CTS-0027] Generating H-Tree topology for net gclk2. |
| 94 | +[INFO CTS-0028] Total number of sinks: 36. |
| 95 | +[INFO CTS-0090] Sinks will be clustered based on buffer max cap. |
| 96 | +[INFO CTS-0030] Number of static layers: 1. |
| 97 | +[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). |
| 98 | +[INFO CTS-0021] Distance between buffers: 7 units (100 um). |
| 99 | +[INFO CTS-0023] Original sink region: [(8930, 96770), (97850, 130370)]. |
| 100 | +[INFO CTS-0024] Normalized sink region: [(0.637857, 6.91214), (6.98929, 9.31214)]. |
| 101 | +[INFO CTS-0025] Width: 6.3514. |
| 102 | +[INFO CTS-0026] Height: 2.4000. |
| 103 | + Level 1 |
| 104 | + Direction: Horizontal |
| 105 | + Sinks per sub-region: 18 |
| 106 | + Sub-region size: 3.1757 X 2.4000 |
| 107 | +[INFO CTS-0034] Segment length (rounded): 1. |
| 108 | + Level 2 |
| 109 | + Direction: Vertical |
| 110 | + Sinks per sub-region: 9 |
| 111 | + Sub-region size: 3.1757 X 1.2000 |
| 112 | +[INFO CTS-0034] Segment length (rounded): 1. |
| 113 | +[INFO CTS-0032] Stop criterion found. Max number of sinks is 15. |
| 114 | +[INFO CTS-0035] Number of sinks covered: 36. |
| 115 | +[INFO CTS-0018] Created 3 clock buffers. |
| 116 | +[INFO CTS-0012] Minimum number of buffers in the clock path: 2. |
| 117 | +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. |
| 118 | +[INFO CTS-0015] Created 3 clock nets. |
| 119 | +[INFO CTS-0016] Fanout distribution for the current clock = 1:2.. |
| 120 | +[INFO CTS-0017] Max level of the clock tree: 1. |
| 121 | +[INFO CTS-0018] Created 17 clock buffers. |
| 122 | +[INFO CTS-0012] Minimum number of buffers in the clock path: 2. |
| 123 | +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. |
| 124 | +[INFO CTS-0015] Created 17 clock nets. |
| 125 | +[INFO CTS-0016] Fanout distribution for the current clock = 6:1, 7:3, 8:2, 9:4, 10:2, 11:3, 12:1.. |
| 126 | +[INFO CTS-0017] Max level of the clock tree: 4. |
| 127 | +[INFO CTS-0018] Created 5 clock buffers. |
| 128 | +[INFO CTS-0012] Minimum number of buffers in the clock path: 2. |
| 129 | +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. |
| 130 | +[INFO CTS-0015] Created 5 clock nets. |
| 131 | +[INFO CTS-0016] Fanout distribution for the current clock = 8:1, 9:2, 10:1.. |
| 132 | +[INFO CTS-0017] Max level of the clock tree: 2. |
| 133 | +[INFO CTS-0098] Clock net "clk" |
| 134 | +[INFO CTS-0099] Sinks 3 |
| 135 | +[INFO CTS-0100] Leaf buffers 0 |
| 136 | +[INFO CTS-0101] Average sink wire length 57.59 um |
| 137 | +[INFO CTS-0102] Path depth 2 - 2 |
| 138 | +[INFO CTS-0207] Leaf load cells 18 |
| 139 | +[INFO CTS-0098] Clock net "clk_regs" |
| 140 | +[INFO CTS-0099] Sinks 159 |
| 141 | +[INFO CTS-0100] Leaf buffers 0 |
| 142 | +[INFO CTS-0101] Average sink wire length 45.22 um |
| 143 | +[INFO CTS-0102] Path depth 2 - 2 |
| 144 | +[INFO CTS-0207] Leaf load cells 18 |
| 145 | +[INFO CTS-0098] Clock net "gclk2" |
| 146 | +[INFO CTS-0099] Sinks 39 |
| 147 | +[INFO CTS-0100] Leaf buffers 0 |
| 148 | +[INFO CTS-0101] Average sink wire length 29.38 um |
| 149 | +[INFO CTS-0102] Path depth 2 - 2 |
| 150 | +[INFO CTS-0207] Leaf load cells 18 |
| 151 | +[DEBUG CTS-insertion delay] top buffer delay for macro tree clkbuf_0_clk is 2.666e-11 |
| 152 | +[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_regs_0_clk is 2.480e-11 |
| 153 | +[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_0_gclk2 is 3.492e-11 |
| 154 | +[INFO CTS-0033] Balancing latency for clock clk |
| 155 | +[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (100608 169407) |
| 156 | +[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (101216 138954) |
| 157 | +[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_clk is inserted at (101824 108501) |
| 158 | +[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_clk is inserted at (102432 78048) |
| 159 | +[INFO CTS-0036] inserted 4 delay buffers |
| 160 | +[INFO CTS-0037] Total number of delay buffers: 4 |
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