cts: update skip_nets.ok

Signed-off-by: Matt Liberty <[email protected]>

Author: maliberty

src/cts/test/skip_nets.ok

@@ -131,9 +131,9 @@ CTS config:
 [INFO CTS-0016]     Fanout distribution for the current clock = 8:1, 9:2, 10:1..
 [INFO CTS-0017]     Max level of the clock tree: 2.
 [INFO CTS-0098] Clock net "clk"
-[INFO CTS-0099]  Sinks 3
+[INFO CTS-0099]  Sinks 2
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 57.59 um
+[INFO CTS-0101]  Average sink wire length 47.55 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 18
 [INFO CTS-0098] Clock net "clk_regs"
@@ -148,9 +148,6 @@ CTS config:
 [INFO CTS-0101]  Average sink wire length 29.38 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 18
-[DEBUG CTS-insertion delay] top buffer delay for macro tree clkbuf_0_clk is 2.666e-11
-[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_regs_0_clk is 2.480e-11
-[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_0_gclk2 is 3.492e-11
 [INFO CTS-0033] Balancing latency for clock clk
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (100608 169407)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (101216 138954)