cts: update ok messages

arthurjolo · arthurjolo · commit d55c816551bf · 2025-11-13T13:34:38.000-03:00
Signed-off-by: arthurjolo &lt;arthurjl@precisioninno.com&gt;
diff --git a/src/cts/test/array.ok b/src/cts/test/array.ok
@@ -103,13 +103,13 @@
 [INFO CTS-0100]  Leaf buffers 103
 [INFO CTS-0101]  Average sink wire length 9313.40 um
 [INFO CTS-0102]  Path depth 16 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 2254
 [INFO CTS-0100]  Leaf buffers 227
 [INFO CTS-0101]  Average sink wire length 4121.94 um
 [INFO CTS-0102]  Path depth 17 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 [INFO CTS-0033] Balancing latency for clock clk
 [INFO CTS-0036]  inserted 3 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 3
diff --git a/src/cts/test/array_ins_delay.ok b/src/cts/test/array_ins_delay.ok
@@ -103,13 +103,13 @@
 [INFO CTS-0100]  Leaf buffers 103
 [INFO CTS-0101]  Average sink wire length 9313.40 um
 [INFO CTS-0102]  Path depth 16 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 2254
 [INFO CTS-0100]  Leaf buffers 227
 [INFO CTS-0101]  Average sink wire length 4121.94 um
 [INFO CTS-0102]  Path depth 17 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 [INFO CTS-0033] Balancing latency for clock clk
 [INFO CTS-0036]  inserted 3 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 3
diff --git a/src/cts/test/array_no_blockages.ok b/src/cts/test/array_no_blockages.ok
@@ -102,13 +102,13 @@
 [INFO CTS-0100]  Leaf buffers 103
 [INFO CTS-0101]  Average sink wire length 9415.86 um
 [INFO CTS-0102]  Path depth 16 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 2254
 [INFO CTS-0100]  Leaf buffers 227
 [INFO CTS-0101]  Average sink wire length 4117.74 um
 [INFO CTS-0102]  Path depth 17 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 [INFO CTS-0033] Balancing latency for clock clk
 [INFO CTS-0036]  inserted 4 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 4
diff --git a/src/cts/test/array_repair_clock_nets.ok b/src/cts/test/array_repair_clock_nets.ok
@@ -103,13 +103,13 @@
 [INFO CTS-0100]  Leaf buffers 103
 [INFO CTS-0101]  Average sink wire length 9313.40 um
 [INFO CTS-0102]  Path depth 16 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 2254
 [INFO CTS-0100]  Leaf buffers 227
 [INFO CTS-0101]  Average sink wire length 4121.94 um
 [INFO CTS-0102]  Path depth 17 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 [INFO RSZ-0047] Found 38 long wires.
 [INFO RSZ-0048] Inserted 112 buffers in 38 nets.
 [INFO CTS-0033] Balancing latency for clock clk
diff --git a/src/cts/test/check_buffer_inference1.ok b/src/cts/test/check_buffer_inference1.ok
@@ -60,5 +60,5 @@
 [INFO CTS-0100]  Leaf buffers 29
 [INFO CTS-0101]  Average sink wire length 129.19 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_buffer_inference2.ok b/src/cts/test/check_buffer_inference2.ok
@@ -60,5 +60,5 @@
 [INFO CTS-0100]  Leaf buffers 29
 [INFO CTS-0101]  Average sink wire length 129.19 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_buffer_inference3.ok b/src/cts/test/check_buffer_inference3.ok
@@ -60,5 +60,5 @@
 [INFO CTS-0100]  Leaf buffers 29
 [INFO CTS-0101]  Average sink wire length 129.19 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_buffers.ok b/src/cts/test/check_buffers.ok
@@ -48,5 +48,5 @@
 [INFO CTS-0100]  Leaf buffers 29
 [INFO CTS-0101]  Average sink wire length 129.19 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_buffers_blockages.ok b/src/cts/test/check_buffers_blockages.ok
@@ -62,5 +62,5 @@
 [INFO CTS-0100]  Leaf buffers 29
 [INFO CTS-0101]  Average sink wire length 130.69 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_buffers_blockages_merge.ok b/src/cts/test/check_buffers_blockages_merge.ok
@@ -63,5 +63,5 @@
 [INFO CTS-0100]  Leaf buffers 29
 [INFO CTS-0101]  Average sink wire length 130.04 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_charBuf.ok b/src/cts/test/check_charBuf.ok
@@ -42,4 +42,4 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 18.87 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 0
+[INFO CTS-0207]  Dummy loads inserted 0
diff --git a/src/cts/test/check_max_fanout1.ok b/src/cts/test/check_max_fanout1.ok
@@ -62,5 +62,5 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 279.37 um
 [INFO CTS-0102]  Path depth 3 - 3
-[INFO CTS-0207]  Leaf load cells 22
+[INFO CTS-0207]  Dummy loads inserted 22
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_max_fanout2.ok b/src/cts/test/check_max_fanout2.ok
@@ -53,5 +53,5 @@
 [INFO CTS-0100]  Leaf buffers 36
 [INFO CTS-0101]  Average sink wire length 126.12 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_max_fanout3.ok b/src/cts/test/check_max_fanout3.ok
@@ -53,5 +53,5 @@
 [INFO CTS-0100]  Leaf buffers 50
 [INFO CTS-0101]  Average sink wire length 262.20 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 40
+[INFO CTS-0207]  Dummy loads inserted 40
 Found 0 unconnected buffers.
diff --git a/src/cts/test/check_wire_rc_cts.ok b/src/cts/test/check_wire_rc_cts.ok
@@ -48,5 +48,5 @@
 [INFO CTS-0100]  Leaf buffers 29
 [INFO CTS-0101]  Average sink wire length 129.19 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 #unconnected buffers: 0
diff --git a/src/cts/test/dummy_load.ok b/src/cts/test/dummy_load.ok
@@ -48,5 +48,5 @@
 [INFO CTS-0100]  Leaf buffers 29
 [INFO CTS-0101]  Average sink wire length 129.19 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 Found 0 unconnected buffers.
diff --git a/src/cts/test/find_clock.ok b/src/cts/test/find_clock.ok
@@ -41,4 +41,4 @@ Use set_wire_rc to set them.
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 18.87 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 0
+[INFO CTS-0207]  Dummy loads inserted 0
diff --git a/src/cts/test/find_clock_pad.ok b/src/cts/test/find_clock_pad.ok
@@ -43,4 +43,4 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 17.47 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 0
+[INFO CTS-0207]  Dummy loads inserted 0
diff --git a/src/cts/test/gated_clock1.ok b/src/cts/test/gated_clock1.ok
@@ -123,13 +123,13 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 45.22 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 29
+[INFO CTS-0207]  Dummy loads inserted 15
 [INFO CTS-0098] Clock net "gclk1"
 [INFO CTS-0099]  Sinks 158
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 83.63 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 29
+[INFO CTS-0207]  Dummy loads inserted 14
 [INFO CTS-0033] Balancing latency for clock clk
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (101013 149105)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (102026 98350)
diff --git a/src/cts/test/gated_clock2.ok b/src/cts/test/gated_clock2.ok
@@ -201,33 +201,33 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 47.55 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 159
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 45.22 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 15
 [INFO CTS-0124] Clock net "gclk1"
 [INFO CTS-0125]  Sinks 1
 [INFO CTS-0098] Clock net "gclk1_regs"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 23.12 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0098] Clock net "gclk2"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 29.38 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0098] Clock net "gclk3"
 [INFO CTS-0099]  Sinks 78
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 37.31 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 6
 [INFO CTS-0033] Balancing latency for clock clk
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (53610 163461)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (53625 160743)
diff --git a/src/cts/test/gated_clock3.ok b/src/cts/test/gated_clock3.ok
@@ -226,39 +226,39 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 63.31 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 1
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 159
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 45.22 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 15
 [INFO CTS-0098] Clock net "gclk1"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 27.44 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0098] Clock net "gclk3"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 28.84 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0124] Clock net "gclk4"
 [INFO CTS-0125]  Sinks 1
 [INFO CTS-0098] Clock net "gclk4_regs"
 [INFO CTS-0099]  Sinks 38
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 23.34 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 2
 [INFO CTS-0098] Clock net "gclk2"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 29.38 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 27
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0033] Balancing latency for clock clk
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (149560 120545)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (151285 117669)
diff --git a/src/cts/test/gated_clock4.ok b/src/cts/test/gated_clock4.ok
@@ -268,39 +268,39 @@ delta HPWL                49070 %
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 51.45 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 26
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "h1\/gclk5"
 [INFO CTS-0099]  Sinks 148
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 62.60 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 26
+[INFO CTS-0207]  Dummy loads inserted 14
 [INFO CTS-0098] Clock net "h1\/gclk2"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 41.68 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 26
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0124] Clock net "gclk4"
 [INFO CTS-0125]  Sinks 1
 [INFO CTS-0098] Clock net "gclk4_regs"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 20.43 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 26
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0098] Clock net "gclk3"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 40.27 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 26
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0098] Clock net "gclk1"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 41.50 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 26
+[INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0033] Balancing latency for clock core
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_core is inserted at (973083 1973195)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_core is inserted at (988171 1974209)
diff --git a/src/cts/test/gated_clock5.ok b/src/cts/test/gated_clock5.ok
@@ -122,19 +122,19 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 121.52 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 28
+[INFO CTS-0207]  Dummy loads inserted 1
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 147
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 43.85 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 28
+[INFO CTS-0207]  Dummy loads inserted 13
 [INFO CTS-0098] Clock net "gclk1"
 [INFO CTS-0099]  Sinks 158
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 83.63 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 28
+[INFO CTS-0207]  Dummy loads inserted 14
 [INFO CTS-0033] Balancing latency for clock clk
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (29897 104848)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (29897 100181)
diff --git a/src/cts/test/hier_insertion_delay.ok b/src/cts/test/hier_insertion_delay.ok
@@ -114,7 +114,7 @@ delta HPWL                    6 %
 [INFO CTS-0100]  Leaf buffers 28
 [INFO CTS-0101]  Average sink wire length 31.00 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 2
+[INFO CTS-0207]  Dummy loads inserted 2
 [INFO CTS-0033] Balancing latency for clock core
 [INFO CTS-0036]  inserted 2 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 2
diff --git a/src/cts/test/insertion_delay.ok b/src/cts/test/insertion_delay.ok
@@ -71,7 +71,7 @@
 [INFO CTS-0100]  Leaf buffers 28
 [INFO CTS-0101]  Average sink wire length 72.77 um
 [INFO CTS-0102]  Path depth 3 - 3
-[INFO CTS-0207]  Leaf load cells 1
+[INFO CTS-0207]  Dummy loads inserted 1
 [INFO CTS-0033] Balancing latency for clock core
 [INFO CTS-0036]  inserted 3 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 3
diff --git a/src/cts/test/inverters.ok b/src/cts/test/inverters.ok
@@ -76,7 +76,7 @@
 [INFO CTS-0100]  Leaf buffers 39
 [INFO CTS-0101]  Average sink wire length 63.24 um
 [INFO CTS-0102]  Path depth 2 - 3
-[INFO CTS-0207]  Leaf load cells 22
+[INFO CTS-0207]  Dummy loads inserted 22
 [INFO CTS-0033] Balancing latency for clock clk
 [INFO CTS-0036]  inserted 3 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 3
diff --git a/src/cts/test/lvt_lib.ok b/src/cts/test/lvt_lib.ok
@@ -115,12 +115,12 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 46.51 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 30
+[INFO CTS-0207]  Dummy loads inserted 15
 [INFO CTS-0098] Clock net "CELL\/clk2"
 [INFO CTS-0099]  Sinks 165
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 66.44 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 30
+[INFO CTS-0207]  Dummy loads inserted 15
 [INFO CTS-0033] Balancing latency for clock clk
 [INFO CTS-0036]  inserted 0 delay buffers
diff --git a/src/cts/test/max_cap.ok b/src/cts/test/max_cap.ok
@@ -41,7 +41,7 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 1169.67 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 0
+[INFO CTS-0207]  Dummy loads inserted 0
 max slew
 
 Pin                                    Limit    Slew   Slack
diff --git a/src/cts/test/post_cts_opt.ok b/src/cts/test/post_cts_opt.ok
@@ -38,4 +38,4 @@
 [INFO CTS-0100]  Leaf buffers 22
 [INFO CTS-0101]  Average sink wire length 118.11 um
 [INFO CTS-0102]  Path depth 3 - 3
-[INFO CTS-0207]  Leaf load cells 6
+[INFO CTS-0207]  Dummy loads inserted 6
diff --git a/src/cts/test/simple_test.ok b/src/cts/test/simple_test.ok
@@ -39,7 +39,7 @@
 [INFO CTS-0100]  Leaf buffers 0
 [INFO CTS-0101]  Average sink wire length 18.87 um
 [INFO CTS-0102]  Path depth 2 - 2
-[INFO CTS-0207]  Leaf load cells 0
+[INFO CTS-0207]  Dummy loads inserted 0
 Total number of Clock Roots: 1.
 Total number of Buffers Inserted: 3.
 Total number of Clock Subnets: 3.
diff --git a/src/cts/test/simple_test_clustered.ok b/src/cts/test/simple_test_clustered.ok
diff --git a/src/cts/test/simple_test_clustered_max_cap.ok b/src/cts/test/simple_test_clustered_max_cap.ok
diff --git a/src/cts/test/simple_test_hier.ok b/src/cts/test/simple_test_hier.ok
diff --git a/src/cts/test/skip_nets.ok b/src/cts/test/skip_nets.ok
diff --git a/src/cts/test/twice.ok b/src/cts/test/twice.ok
