udate ok files

Signed-off-by: arthurjolo <[email protected]>

Author: arthurjolo

src/dbSta/test/escape_slash.ok

@@ -66,14 +66,14 @@ delta HPWL                56871 %
 [INFO CTS-0030]  Number of static layers: 1.
 [INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
 [INFO CTS-0021]  Distance between buffers: 7 units (100 um).
-[INFO CTS-0023]  Original sink region: [(946595, 1947820), (983835, 1983380)].
-[INFO CTS-0024]  Normalized sink region: [(67.6139, 139.13), (70.2739, 141.67)].
-[INFO CTS-0025]     Width:  2.6600.
-[INFO CTS-0026]     Height: 2.5400.
+[INFO CTS-0023]  Original sink region: [(1003215, 1965350), (1006445, 1972180)].
+[INFO CTS-0024]  Normalized sink region: [(71.6582, 140.382), (71.8889, 140.87)].
+[INFO CTS-0025]     Width:  0.2307.
+[INFO CTS-0026]     Height: 0.4879.
  Level 1
-    Direction: Horizontal
+    Direction: Vertical
     Sinks per sub-region: 2
-    Sub-region size: 1.3300 X 2.5400
+    Sub-region size: 0.2307 X 0.2439
 [INFO CTS-0034]     Segment length (rounded): 1.
 [INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
 [INFO CTS-0035]  Number of sinks covered: 4.
@@ -140,8 +140,8 @@ delta HPWL                56871 %
 [INFO CTS-0030]  Number of static layers: 1.
 [INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
 [INFO CTS-0021]  Distance between buffers: 7 units (100 um).
-[INFO CTS-0023]  Original sink region: [(964455, 1966580), (964455, 1966580)].
-[INFO CTS-0024]  Normalized sink region: [(68.8896, 140.47), (68.8896, 140.47)].
+[INFO CTS-0023]  Original sink region: [(1006445, 1987750), (1006445, 1987750)].
+[INFO CTS-0024]  Normalized sink region: [(71.8889, 141.982), (71.8889, 141.982)].
 [INFO CTS-0025]     Width:  0.0000.
 [INFO CTS-0026]     Height: 0.0000.
  Level 1
@@ -265,19 +265,19 @@ delta HPWL                56871 %
 [INFO CTS-0098] Clock net "clk"
 [INFO CTS-0099]  Sinks 4
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 51.45 um
+[INFO CTS-0101]  Average sink wire length 31.68 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "hi_gclk2"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 50.99 um
+[INFO CTS-0101]  Average sink wire length 30.05 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0098] Clock net "hi_gclk5"
 [INFO CTS-0099]  Sinks 149
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 45.09 um
+[INFO CTS-0101]  Average sink wire length 24.83 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 15
 [INFO CTS-0124] Clock net "gclk4"
@@ -291,23 +291,23 @@ delta HPWL                56871 %
 [INFO CTS-0098] Clock net "gclk3"
 [INFO CTS-0099]  Sinks 39
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 40.27 um
+[INFO CTS-0101]  Average sink wire length 13.20 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 3
 [INFO CTS-0098] Clock net "gclk1"
 [INFO CTS-0099]  Sinks 38
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 44.58 um
+[INFO CTS-0101]  Average sink wire length 28.47 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Dummy loads inserted 2
 [INFO CTS-0033] Balancing latency for clock core
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_core is inserted at (964406 1977451)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_core is inserted at (982218 1971523)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_core is inserted at (951995 1970476)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_core is inserted at (952524 1974128)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_core is inserted at (968965 1966825)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_core is inserted at (972465 1966825)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_core is inserted at (975965 1966825)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_core is inserted at (1004147 1977105)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_core is inserted at (1001622 1965472)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_core is inserted at (1004613 1958637)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_core is inserted at (1004147 1961285)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_core is inserted at (1003681 1963932)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_core is inserted at (1005080 1974656)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_core is inserted at (1005080 1979323)
 [INFO CTS-0036]  inserted 7 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 7
 No differences found.