Merge pull request #8053 from eder-matheus/dpl_fix

eder-matheus · web-flow · commit d957ce88f246 · 2025-08-18T21:10:08.000-03:00
dpl: avoid padding violation on cells adjacent to the core edge
diff --git a/src/dpl/src/PlacementDRC.cpp b/src/dpl/src/PlacementDRC.cpp
@@ -302,7 +302,9 @@ bool PlacementDRC::checkPadding(const Node* cell,
     for (GridY grid_y{y}; grid_y < cell_y_end; grid_y++) {
       const Pixel* pixel = grid_->gridPixel(grid_x, grid_y);
       if (pixel == nullptr) {  // at the core edge
-        if (!cell->isFixed()) {
+        const bool left_edge = x == 0;
+        const bool right_edge = cell_x_end == grid_->getRowSiteCount();
+        if (!cell->isFixed() && !left_edge && !right_edge) {
           // Padding violation with the core edge.
           return false;
         }
diff --git a/src/dpl/test/BUILD b/src/dpl/test/BUILD
@@ -56,6 +56,7 @@ COMPULSORY_TESTS = [
     "pad06",
     "pad07",
     "pad08",
+    "pad09",
     "regions1",
     "regions2",
     "regions3",
diff --git a/src/dpl/test/CMakeLists.txt b/src/dpl/test/CMakeLists.txt
@@ -59,6 +59,7 @@ or_integration_tests(
     pad06
     pad07
     pad08
+    pad09
     regions1
     regions2
     regions3
diff --git a/src/dpl/test/fillers2.defok b/src/dpl/test/fillers2.defok
@@ -33,16 +33,14 @@ VIAS 3 ;
     - via5_960x2800 + VIARULE Via5Array-0 + CUTSIZE 280 280  + LAYERS metal5 metal6 via5  + CUTSPACING 320 320  + ENCLOSURE 40 60 40 60  + ROWCOL 5 2  ;
     - via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280  + LAYERS metal6 metal7 via6  + CUTSPACING 320 320  + ENCLOSURE 340 360 340 360  + ROWCOL 4 1  ;
 END VIAS
-COMPONENTS 9 ;
-    - FILLER_0_0 FILLCELL_X2 + SOURCE DIST + PLACED ( 3800 2800 ) FS ;
-    - FILLER_0_25 FILLCELL_X4 + SOURCE DIST + PLACED ( 13300 2800 ) FS ;
-    - FILLER_0_29 FILLCELL_X2 + SOURCE DIST + PLACED ( 14820 2800 ) FS ;
+COMPONENTS 7 ;
+    - FILLER_0_23 FILLCELL_X8 + SOURCE DIST + PLACED ( 12540 2800 ) FS ;
     - FILLER_0_31 FILLCELL_X1 + SOURCE DIST + PLACED ( 15580 2800 ) FS ;
-    - FILLER_0_9 FILLCELL_X16 + SOURCE DIST + PLACED ( 7220 2800 ) FS ;
+    - FILLER_0_7 FILLCELL_X16 + SOURCE DIST + PLACED ( 6460 2800 ) FS ;
     - FILLER_1_0 FILLCELL_X32 + SOURCE DIST + PLACED ( 3800 5600 ) N ;
     - FILLER_2_0 FILLCELL_X32 + SOURCE DIST + PLACED ( 3800 8400 ) FS ;
     - FILLER_3_0 FILLCELL_X32 + SOURCE DIST + PLACED ( 3800 11200 ) N ;
-    - _277_ BUF_X4 + PLACED ( 4560 2800 ) FS ;
+    - _277_ BUF_X4 + PLACED ( 3800 2800 ) FS ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL
diff --git a/src/dpl/test/fillers2.ok b/src/dpl/test/fillers2.ok
@@ -6,12 +6,12 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          3.7 u
-average displacement        3.7 u
-max displacement            3.7 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL              9.9 u
-delta HPWL                  332 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
-[INFO DPL-0001] Placed 8 filler instances.
+[INFO DPL-0001] Placed 6 filler instances.
 No differences found.
diff --git a/src/dpl/test/fillers2_verbose.ok b/src/dpl/test/fillers2_verbose.ok
@@ -6,17 +6,16 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          3.7 u
-average displacement        3.7 u
-max displacement            3.7 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL              9.9 u
-delta HPWL                  332 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
-[INFO DPL-0001] Placed 8 filler instances.
+[INFO DPL-0001] Placed 6 filler instances.
 Filler usage:
   FILLCELL_X1:  1
   FILLCELL_X16: 1
-  FILLCELL_X2:  2
   FILLCELL_X32: 3
-  FILLCELL_X4:  1
+  FILLCELL_X8:  1
diff --git a/src/dpl/test/mirror2.def b/src/dpl/test/mirror2.def
@@ -35,7 +35,7 @@ VIAS 3 ;
 END VIAS
 COMPONENTS 2 ;
     - b1 BUF_X1 + PLACED ( 3800 2800 ) N ;
-    - block1 BLOCK1 + FIXED ( 4940 2810 ) N ;
+    - block1 BLOCK1 + FIXED ( 4560 2810 ) N ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 -140 ) N + LAYER metal6 ( -140 -140 ) ( 140 140 ) ;
diff --git a/src/dpl/test/mirror2.ok b/src/dpl/test/mirror2.ok
@@ -8,12 +8,12 @@
 [INFO ODB-0133]     Created 3 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          2.9 u
-average displacement        1.4 u
-max displacement            2.9 u
-original HPWL               0.9 u
+total displacement          2.7 u
+average displacement        1.3 u
+max displacement            2.7 u
+original HPWL               0.7 u
 legalized HPWL              2.1 u
-delta HPWL                  136 %
+delta HPWL                  199 %
 
 block orient R0
 [INFO DPL-0020] Mirrored 1 instances
diff --git a/src/dpl/test/pad01.defok b/src/dpl/test/pad01.defok
@@ -34,7 +34,7 @@ VIAS 3 ;
     - via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280  + LAYERS metal6 metal7 via6  + CUTSPACING 320 320  + ENCLOSURE 340 360 340 360  + ROWCOL 4 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - _277_ BUF_X4 + PLACED ( 5700 2800 ) FS ;
+    - _277_ BUF_X4 + PLACED ( 3800 2800 ) FS ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL
diff --git a/src/dpl/test/pad01.ok b/src/dpl/test/pad01.ok
@@ -6,11 +6,11 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          4.2 u
-average displacement        4.2 u
-max displacement            4.2 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL             11.0 u
-delta HPWL                  382 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
 No differences found.
diff --git a/src/dpl/test/pad07.defok b/src/dpl/test/pad07.defok
@@ -34,7 +34,7 @@ VIAS 3 ;
     - via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280  + LAYERS metal6 metal7 via6  + CUTSPACING 320 320  + ENCLOSURE 340 360 340 360  + ROWCOL 4 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - _277_ BUF_X4 + PLACED ( 5700 2800 ) FS ;
+    - _277_ BUF_X4 + PLACED ( 3800 2800 ) FS ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL
diff --git a/src/dpl/test/pad07.ok b/src/dpl/test/pad07.ok
@@ -6,11 +6,11 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          4.2 u
-average displacement        4.2 u
-max displacement            4.2 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL             11.0 u
-delta HPWL                  382 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
 No differences found.
diff --git a/src/dpl/test/pad08.defok b/src/dpl/test/pad08.defok
@@ -34,7 +34,7 @@ VIAS 3 ;
     - via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280  + LAYERS metal6 metal7 via6  + CUTSPACING 320 320  + ENCLOSURE 340 360 340 360  + ROWCOL 4 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - _277_ BUF_X4 + PLACED ( 5700 2800 ) FS ;
+    - _277_ BUF_X4 + PLACED ( 3800 2800 ) FS ;
 END COMPONENTS
 PINS 2 ;
     - input + NET input + DIRECTION INPUT + USE SIGNAL
diff --git a/src/dpl/test/pad08.ok b/src/dpl/test/pad08.ok
@@ -6,11 +6,11 @@
 [INFO ODB-0133]     Created 2 nets and 2 connections.
 Placement Analysis
 ---------------------------------
-total displacement          4.2 u
-average displacement        4.2 u
-max displacement            4.2 u
+total displacement          3.3 u
+average displacement        3.3 u
+max displacement            3.3 u
 original HPWL               2.3 u
-legalized HPWL             11.0 u
-delta HPWL                  382 %
+legalized HPWL              9.1 u
+delta HPWL                  299 %
 
 No differences found.
diff --git a/src/dpl/test/pad09.def b/src/dpl/test/pad09.def
@@ -0,0 +1,12 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN aes_cipher_top ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 2000000 2000000 ) ;
+ROW ROW_283 unit 30240 975690 FS DO 3624 BY 1 STEP 480 0 ;
+COMPONENTS 2 ;
+    - ANTENNA_283 sky130_fd_sc_hs__diode_2 + PLACED ( 30240 975690 ) FS ;
+    - ANTENNA_284 sky130_fd_sc_hs__diode_2 + PLACED ( 1768800 975690 ) FS ;
+END COMPONENTS
+END DESIGN
diff --git a/src/dpl/test/pad09.defok b/src/dpl/test/pad09.defok
@@ -0,0 +1,14 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN aes_cipher_top ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 2000000 2000000 ) ;
+ROW ROW_283 unit 30240 975690 FS DO 3624 BY 1 STEP 480 0 ;
+COMPONENTS 2 ;
+    - ANTENNA_283 sky130_fd_sc_hs__diode_2 + PLACED ( 30240 975690 ) FS ;
+    - ANTENNA_284 sky130_fd_sc_hs__diode_2 + PLACED ( 1768800 975690 ) FS ;
+END COMPONENTS
+NETS 0 ;
+END NETS
+END DESIGN
diff --git a/src/dpl/test/pad09.ok b/src/dpl/test/pad09.ok
@@ -0,0 +1,5 @@
+[INFO ODB-0227] LEF file: sky130hs/sky130hs.tlef, created 13 layers, 25 vias
+[INFO ODB-0227] LEF file: sky130hs/sky130hs_std_cell.lef, created 390 library cells
+[INFO ODB-0128] Design: aes_cipher_top
+[INFO ODB-0131]     Created 2 components and 10 component-terminals.
+No differences found.
diff --git a/src/dpl/test/pad09.tcl b/src/dpl/test/pad09.tcl
@@ -0,0 +1,12 @@
+# set_placement_padding 2
+source "helpers.tcl"
+read_lef sky130hs/sky130hs.tlef
+read_lef sky130hs/sky130hs_std_cell.lef
+read_def pad09.def
+# check -masters arg parsing
+set_placement_padding -global -left 2 -right 2
+check_placement
+
+set def_file [make_result_file pad09.def]
+write_def $def_file
+diff_file pad09.defok $def_file
diff --git a/test/aes_sky130hd.metrics b/test/aes_sky130hd.metrics
diff --git a/test/aes_sky130hd.metrics_limits b/test/aes_sky130hd.metrics_limits
diff --git a/test/ibex_sky130hs.metrics b/test/ibex_sky130hs.metrics
diff --git a/test/ibex_sky130hs.metrics_limits b/test/ibex_sky130hs.metrics_limits
diff --git a/test/jpeg_sky130hs.metrics b/test/jpeg_sky130hs.metrics
diff --git a/test/jpeg_sky130hs.metrics_limits b/test/jpeg_sky130hs.metrics_limits
