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test/orfs: use write_verilog -remove_cells exclude physical only cells
avoids empty.dff Signed-off-by: Øyvind Harboe <[email protected]>
1 parent 1a9fd6d commit e4f6d36

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5 files changed

+17
-44
lines changed

5 files changed

+17
-44
lines changed

test/orfs/gcd/BUILD

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@@ -1,5 +1,6 @@
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load("@bazel-orfs//:eqy.bzl", "eqy_test")
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load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_run")
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load("//test/orfs/mock-array:mock-array.bzl", "ASAP7_REMOVE_CELLS")
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package(features = ["layering_check"])
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@@ -50,6 +51,7 @@ STAGES = [
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"gcd_{stage}.v".format(stage = stage),
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],
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arguments = {
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"ASAP7_REMOVE_CELLS": " ".join(ASAP7_REMOVE_CELLS),
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"OUTPUT": "$(location :gcd_{stage}.v)".format(stage = stage),
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},
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script = "//test/orfs/mock-array:write_verilog.tcl",

test/orfs/mock-array/BUILD

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@@ -1,7 +1,7 @@
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load("@bazel-orfs//:eqy.bzl", "eqy_test")
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load("@bazel-orfs//:openroad.bzl", "orfs_run")
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load("@bazel-orfs//toolchains/scala:chisel.bzl", "chisel_binary")
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load(":mock-array.bzl", "config", "element", "mock_array", "verilog")
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load(":mock-array.bzl", "ASAP7_REMOVE_CELLS", "config", "element", "mock_array", "verilog")
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package(
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features = ["-layering_check"], # TODO: enable
@@ -111,6 +111,7 @@ orfs_run(
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"{}_floorplan.v".format(module),
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],
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arguments = {
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"ASAP7_REMOVE_CELLS": " ".join(ASAP7_REMOVE_CELLS),
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"OUTPUT": "$(location :{}_floorplan.v)".format(module),
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},
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script = ":write_verilog.tcl",
@@ -129,7 +130,6 @@ filegroup(
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"asap7/asap7sc7p5t_INVBUF_RVT_TT_201020.v",
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"asap7/asap7sc7p5t_OA_RVT_TT_201020.v",
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"asap7/asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
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"asap7/empty.v",
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"@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/dff.v",
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],
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visibility = ["//visibility:public"],

test/orfs/mock-array/asap7/empty.v

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This file was deleted.

test/orfs/mock-array/mock-array.bzl

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@@ -10,6 +10,18 @@ load("@rules_shell//shell:sh_test.bzl", "sh_test")
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load("@rules_verilator//verilator:defs.bzl", "verilator_cc_library")
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load("@rules_verilator//verilog:defs.bzl", "verilog_library")
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# Empty cells we don't need or want, eqy doesn't grok them
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ASAP7_REMOVE_CELLS = [
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"TAPCELL_ASAP7_75t_R",
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"FILLERxp5_ASAP7_75",
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"FILLER_ASAP7_75t_R",
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"DECAPx1_ASAP7_75t_R",
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"DECAPx2_ASAP7_75t_R",
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"DECAPx4_ASAP7_75t_R",
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"DECAPx6_ASAP7_75t_R",
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"DECAPx10_ASAP7_75t_R",
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]
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FIRTOOL_OPTIONS = [
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"-disable-all-randomization",
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"-strip-debug-info",
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@@ -1,2 +1,2 @@
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source $::env(SCRIPTS_DIR)/open.tcl
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write_verilog $::env(OUTPUT)
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log_cmd write_verilog -remove_cells $::env(ASAP7_REMOVE_CELLS) $::env(OUTPUT)

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