cts: remove unused funtions that were moved from TritonCTS -> LatencyBalacer

Signed-off-by: arthurjolo <[email protected]>

Author: arthurjolo

src/cts/include/cts/TritonCTS.h

@@ -206,22 +206,6 @@ class TritonCTS
   void setAllClocksPropagated();
   void repairClockNets();
   void balanceMacroRegisterLatencies();
-  float getVertexClkArrival(sta::Vertex* sinkVertex,
-                            odb::dbNet* topNet,
-                            odb::dbITerm* iterm);
-  void computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph);
-  void computeSinkArrivalRecur(odb::dbNet* topClokcNet,
-                               odb::dbITerm* iterm,
-                               float& sumArrivals,
-                               unsigned& numSinks,
-                               sta::Graph* graph);
-  bool propagateClock(odb::dbITerm* input);
-  void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder);
-  void computeTopBufferDelay(TreeBuilder* builder);
-  odb::dbInst* insertDelayBuffer(odb::dbInst* driver,
-                                 const std::string& clockName,
-                                 int locX,
-                                 int locY);
 
   sta::dbSta* openSta_ = nullptr;
   sta::dbNetwork* network_ = nullptr;

src/cts/src/TritonCTS.cpp

@@ -2345,13 +2345,6 @@ void TritonCTS::printClockNetwork(const Clock& clockNet) const
 
 void TritonCTS::setAllClocksPropagated()
 {
-  // Compute ideal buffer delay to use in delay insertion
-  if (options_->insertionDelayEnabled()) {
-    for (auto& iter : builders_) {
-      TreeBuilder* builder = iter.get();
-      computeTopBufferDelay(builder);
-    }
-  }
   sta::Sdc* sdc = openSta_->sdc();
   for (sta::Clock* clk : *sdc->clocks()) {
     openSta_->setPropagatedClock(clk);
@@ -2406,351 +2399,4 @@ void TritonCTS::balanceMacroRegisterLatencies()
   }
 }
 
-float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex,
-                                     odb::dbNet* topNet,
-                                     odb::dbITerm* iterm)
-{
-  sta::VertexPathIterator pathIter(sinkVertex, openSta_);
-  float clkPathArrival = 0.0;
-  while (pathIter.hasNext()) {
-    sta::Path* path = pathIter.next();
-    const sta::ClockEdge* clock_edge = path->clkEdge(openSta_);
-    if (clock_edge == nullptr) {
-      continue;
-    }
-
-    if (clock_edge->transition() != sta::RiseFall::rise()) {
-      // only populate with rising edges
-      continue;
-    }
-
-    if (path->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) {
-      continue;
-      // only populate with max delay
-    }
-
-    const sta::Clock* clock = path->clock(openSta_);
-    if (clock) {
-      sta::PathExpanded expand(path, openSta_);
-      const sta::Path* start = expand.startPath();
-
-      odb::dbNet* pathStartNet = nullptr;
-
-      odb::dbITerm* term;
-      odb::dbBTerm* port;
-      odb::dbModITerm* modIterm;
-      network_->staToDb(start->pin(openSta_), term, port, modIterm);
-      if (term) {
-        pathStartNet = term->getNet();
-      }
-      if (port) {
-        pathStartNet = port->getNet();
-      }
-      if (pathStartNet == topNet) {
-        clkPathArrival = path->arrival();
-        return clkPathArrival;
-      }
-    }
-  }
-  logger_->warn(CTS, 2, "No paths found for pin {}.", iterm->getName());
-  return clkPathArrival;
-}
-
-void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph)
-{
-  Clock clock = builder->getClock();
-  odb::dbNet* topInputClockNet = clock.getNetObj();
-  if (builder->getTopInputNet() != nullptr) {
-    topInputClockNet = builder->getTopInputNet();
-  }
-  // compute average input arrival at all sinks
-  float sumArrivals = 0.0;
-  unsigned numSinks = 0;
-  clock.forEachSink([&](const ClockInst& sink) {
-    odb::dbITerm* iterm = sink.getDbInputPin();
-    computeSinkArrivalRecur(
-        topInputClockNet, iterm, sumArrivals, numSinks, graph);
-  });
-  float aveArrival = sumArrivals / (float) numSinks;
-  builder->setAveSinkArrival(aveArrival);
-  debugPrint(logger_,
-             CTS,
-             "insertion delay",
-             1,
-             "{} {}: average sink arrival is {:0.3e}",
-             (builder->getTreeType() == TreeType::MacroTree) ? "macro tree"
-                                                             : "register tree",
-             clock.getName(),
-             builder->getAveSinkArrival());
-}
-
-void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet,
-                                        odb::dbITerm* iterm,
-                                        float& sumArrivals,
-                                        unsigned& numSinks,
-                                        sta::Graph* graph)
-{
-  if (iterm) {
-    odb::dbInst* inst = iterm->getInst();
-    if (inst) {
-      if (isSink(iterm)) {
-        // either register or macro input pin
-        sta::Pin* pin = network_->dbToSta(iterm);
-        if (pin) {
-          sta::Vertex* sinkVertex = graph->pinDrvrVertex(pin);
-          float arrival = getVertexClkArrival(sinkVertex, topClokcNet, iterm);
-          // add insertion delay
-          float insDelay = 0.0;
-          sta::LibertyCell* libCell
-              = network_->libertyCell(network_->dbToSta(inst));
-          odb::dbMTerm* mterm = iterm->getMTerm();
-          if (libCell && mterm) {
-            sta::LibertyPort* libPort
-                = libCell->findLibertyPort(mterm->getConstName());
-            if (libPort) {
-              const float rise = libPort->clkTreeDelay(
-                  0.0, sta::RiseFall::rise(), sta::MinMax::max());
-              const float fall = libPort->clkTreeDelay(
-                  0.0, sta::RiseFall::fall(), sta::MinMax::max());
-
-              if (rise != 0 || fall != 0) {
-                insDelay = (rise + fall) / 2.0;
-              }
-            }
-          }
-          sumArrivals += (arrival + insDelay);
-          numSinks++;
-        }
-      } else {
-        // not a sink, but a clock gater
-        odb::dbITerm* outTerm = inst->getFirstOutput();
-        if (outTerm) {
-          odb::dbNet* outNet = outTerm->getNet();
-          bool propagate = propagateClock(iterm);
-          if (outNet && propagate) {
-            odb::dbSet<odb::dbITerm> iterms = outNet->getITerms();
-            odb::dbSet<odb::dbITerm>::iterator iter;
-            for (iter = iterms.begin(); iter != iterms.end(); ++iter) {
-              odb::dbITerm* inTerm = *iter;
-              if (inTerm->getIoType() == odb::dbIoType::INPUT) {
-                computeSinkArrivalRecur(
-                    topClokcNet, inTerm, sumArrivals, numSinks, graph);
-              }
-            }
-          }
-        }
-      }
-    }
-  }
-}
-
-bool TritonCTS::propagateClock(odb::dbITerm* input)
-{
-  odb::dbInst* inst = input->getInst();
-  sta::Cell* masterCell = network_->dbToSta(inst->getMaster());
-  sta::LibertyCell* libertyCell = network_->libertyCell(masterCell);
-
-  if (!libertyCell) {
-    return false;
-  }
-  // Clock tree buffers
-  if (libertyCell->isInverter() || libertyCell->isBuffer()) {
-    return true;
-  }
-  // Combinational components
-  if (!libertyCell->hasSequentials()) {
-    return true;
-  }
-  sta::LibertyPort* inputPort
-      = libertyCell->findLibertyPort(input->getMTerm()->getConstName());
-
-  // Clock Gater / Latch improvised as clock gater
-  if (inputPort) {
-    return inputPort->isClockGateClock() || inputPort->isLatchData();
-  }
-
-  return false;
-}
-
-// Balance latencies between macro tree and register tree
-// by adding delay buffers to one tree
-void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder,
-                                TreeBuilder* registerBuilder)
-{
-  float latencyDiff = macroBuilder->getAveSinkArrival()
-                      - registerBuilder->getAveSinkArrival();
-  int numBuffers = 0;
-  TreeBuilder* builder = nullptr;
-  if (latencyDiff > 0) {
-    // add buffers to register tree
-    numBuffers = (int) (latencyDiff / registerBuilder->getTopBufferDelay());
-    builder = registerBuilder;
-  } else {
-    // add buffers to macro tree (not common but why not?)
-    numBuffers
-        = (int) (std::abs(latencyDiff) / macroBuilder->getTopBufferDelay());
-    builder = macroBuilder;
-  }
-
-  // We don't want to add more delay buffers than needed because
-  // wire delays are not considered.  The fewer the delay buffers, the better.
-  numBuffers = numBuffers * options_->getDelayBufferDerate();
-  if (numBuffers == 0) {
-    // clang-format off
-    debugPrint(logger_, CTS, "insertion delay", 1, "no delay buffers are needed"
-               " to adjust latencies");
-    // clang-format on
-    return;
-  }
-  // clang-format off
-  debugPrint(logger_, CTS, "insertion delay", 1, "{} delay buffers are needed"
-             " to adjust latencies at {} tree", numBuffers,
-             (builder->getTreeType() == TreeType::MacroTree)? "macro" : "register");
-  // clang-format on
-
-  // disconnect driver output
-  odb::dbInst* driver = builder->getTopBuffer();
-  odb::dbITerm* driverOutputTerm = driver->getFirstOutput();
-  odb::dbNet* outputNet = driverOutputTerm->getNet();
-
-  // hierarchy support:
-  // Get the hierarchical net if any and propagate to end of chain
-  sta::Pin* op_pin = network_->dbToSta(driverOutputTerm);
-  odb::dbModNet* candidate_hier_net = network_->hasHierarchicalElements()
-                                          ? network_->hierNet(op_pin)
-                                          : nullptr;
-  odb::dbNet* orig_flat_net = network_->flatNet(op_pin);
-
-  // get bbox of current load pins without driver output pin
-  driverOutputTerm->disconnect();
-  odb::Rect bbox = outputNet->getTermBBox();
-  int destX = bbox.xCenter();
-  int destY = bbox.yCenter();
-  int sourceX, sourceY;
-  driver->getLocation(sourceX, sourceY);
-  float offsetX = (float) (destX - sourceX) / (numBuffers + 1);
-  float offsetY = (float) (destY - sourceY) / (numBuffers + 1);
-
-  double scalingFactor = techChar_->getLengthUnit();
-  for (int i = 0; i < numBuffers; i++) {
-    double locX = (double) (sourceX + offsetX * (i + 1)) / scalingFactor;
-    double locY = (double) (sourceY + offsetY * (i + 1)) / scalingFactor;
-    Point<double> bufferLoc(locX, locY);
-    Point<double> legalBufferLoc
-        = builder->legalizeOneBuffer(bufferLoc, options_->getRootBuffer());
-    odb::dbInst* buffer
-        = insertDelayBuffer(driver,
-                            builder->getClock().getSdcName(),
-                            legalBufferLoc.getX() * scalingFactor,
-                            legalBufferLoc.getY() * scalingFactor);
-    driver = buffer;
-  }
-  // take care of output pin connections
-  // driver is now the last delay buffer
-  driverOutputTerm = driver->getFirstOutput();
-  driverOutputTerm->disconnect();
-  // hierarchical fix. guarded by network has hierarchy
-  if (candidate_hier_net && network_->hasHierarchy()) {
-    network_->connectPin((sta::Pin*) driverOutputTerm,
-                         (sta::Net*) orig_flat_net,
-                         (sta::Net*) candidate_hier_net);
-  } else {
-    driverOutputTerm->connect(outputNet);
-  }
-}
-
-void TritonCTS::computeTopBufferDelay(TreeBuilder* builder)
-{
-  Clock clock = builder->getClock();
-  odb::dbInst* topBuffer
-      = block_->findInst(builder->getTopBufferName().c_str());
-  if (topBuffer) {
-    builder->setTopBuffer(topBuffer);
-    odb::dbITerm* inputTerm = getFirstInput(topBuffer);
-    odb::dbITerm* outputTerm = topBuffer->getFirstOutput();
-    sta::Pin* inputPin = network_->dbToSta(inputTerm);
-    sta::Pin* outputPin = network_->dbToSta(outputTerm);
-
-    float inputArrival = openSta_->pinArrival(
-        inputPin, sta::RiseFall::rise(), sta::MinMax::max());
-    float outputArrival = openSta_->pinArrival(
-        outputPin, sta::RiseFall::rise(), sta::MinMax::max());
-    float bufferDelay = outputArrival - inputArrival;
-    // add a 10% increase on the buffer delay as this is an ideal model
-    // TODO: compute the exact delay adding a buffer adds,
-    // removing the need for the derate
-    builder->setTopBufferDelay(bufferDelay * 1.1);
-    debugPrint(logger_,
-               CTS,
-               "insertion delay",
-               1,
-               "top buffer delay for {} {} is {:0.3e}",
-               (builder->getTreeType() == TreeType::MacroTree)
-                   ? "macro tree"
-                   : "register tree",
-               topBuffer->getName(),
-               builder->getTopBufferDelay());
-  }
-}
-
-// Create a new delay buffer and connect output pin of driver to input pin of
-// new buffer. Output pin of new buffer will be connected later.
-odb::dbInst* TritonCTS::insertDelayBuffer(odb::dbInst* driver,
-                                          const std::string& clockName,
-                                          int locX,
-                                          int locY)
-
-{
-  // creat a new input net
-  std::string newNetName
-      = "delaynet_" + std::to_string(delayBufIndex_) + "_" + clockName;
-
-  // hierarchy fix, make the net in the right scope
-  odb::dbModule* module = driver->getModule();
-  if (module == nullptr) {
-    // if none put in top level
-    module = block_->getTopModule();
-  }
-  sta::Instance* scope
-      = (module == nullptr || (module == block_->getTopModule()))
-            ? network_->topInstance()
-            : (sta::Instance*) (module->getModInst());
-  odb::dbNet* newNet = network_->staToDb(network_->makeNet(
-      newNetName.c_str(), scope, odb::dbNameUniquifyType::IF_NEEDED));
-
-  newNet->setSigType(odb::dbSigType::CLOCK);
-
-  // create a new delay buffer
-  std::string newBufName
-      = "delaybuf_" + std::to_string(delayBufIndex_++) + "_" + clockName;
-  odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str());
-
-  // fix: make buffer in same hierarchical module as driver
-
-  odb::dbInst* newBuf
-      = odb::dbInst::create(block_, master, newBufName.c_str(), false, module);
-
-  newBuf->setSourceType(odb::dbSourceType::TIMING);
-  newBuf->setLocation(locX, locY);
-  newBuf->setPlacementStatus(odb::dbPlacementStatus::PLACED);
-
-  // connect driver output with new buffer input
-  odb::dbITerm* driverOutTerm = driver->getFirstOutput();
-  odb::dbITerm* newBufInTerm = getFirstInput(newBuf);
-
-  driverOutTerm->disconnect();
-  driverOutTerm->connect(newNet);
-  newBufInTerm->connect(newNet);
-
-  debugPrint(logger_,
-             CTS,
-             "insertion delay",
-             1,
-             "new delay buffer {} is inserted at ({} {})",
-             newBuf->getName(),
-             locX,
-             locY);
-
-  return newBuf;
-}
 }  // namespace cts

src/cts/test/gated_clock1.ok

@@ -130,9 +130,6 @@
 [INFO CTS-0101]  Average sink wire length 83.63 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 29
-[DEBUG CTS-insertion delay] top buffer delay for macro tree clkbuf_0_clk is 2.480e-11
-[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_regs_0_clk is 2.480e-11
-[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_0_gclk1 is 5.007e-11
 [INFO CTS-0033] Balancing latency for clock clk
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (101013 149105)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (102026 98350)