cgt: fix ibex_sky130hd_gated_tcl.vok -> ibex_sky130hd_gated.vok

maliberty · maliberty · commit f361507f48f4 · 2025-09-09T17:20:46.000Z
Signed-off-by: Matt Liberty &lt;mliberty@precisioninno.com&gt;
diff --git a/src/cgt/test/ibex_sky130hd.tcl b/src/cgt/test/ibex_sky130hd.tcl
@@ -8,4 +8,4 @@ create_clock [get_ports clk_i] -name core_clock -period 10
 clock_gating -max_cover 50
 set verilog_file [make_result_file ibex_sky130hd_gated_tcl.v]
 write_verilog $verilog_file
-diff_file ibex_sky130hd_gated_tcl.vok $verilog_file
+diff_file ibex_sky130hd_gated.vok $verilog_file
