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arthurjoloarthurjolo
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update ok files
Signed-off-by: arthurjolo <[email protected]>
1 parent 1feffa0 commit f781e9f

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3 files changed

+98
-101
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3 files changed

+98
-101
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‎src/cts/test/gated_clock3.ok‎

Lines changed: 77 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,18 @@
99
CLKBUF_X3
1010
[INFO CTS-0049] Characterization buffer is CLKBUF_X3.
1111
[INFO CTS-0007] Net "clk" found for clock "clk".
12-
[INFO CTS-0011] Clock net "clk" for macros has 4 sinks.
12+
[INFO CTS-0011] Clock net "clk" for macros has 3 sinks.
1313
[INFO CTS-0011] Clock net "clk_regs" for registers has 144 sinks.
14-
[WARNING CTS-0041] Net "clonenet_1_gclk4" has 1 sinks. Skipping...
15-
[INFO CTS-0010] Clock net "gclk2" has 36 sinks.
1614
[INFO CTS-0010] Clock net "gclk1" has 36 sinks.
1715
[INFO CTS-0010] Clock net "gclk3" has 36 sinks.
18-
[INFO CTS-0010] Clock net "gclk4" has 36 sinks.
19-
[INFO CTS-0008] TritonCTS found 6 clock nets.
16+
[INFO CTS-0011] Clock net "gclk4" for macros has 1 sinks.
17+
[INFO CTS-0011] Clock net "gclk4_regs" for registers has 36 sinks.
18+
[INFO CTS-0010] Clock net "gclk2" has 36 sinks.
19+
[INFO CTS-0008] TritonCTS found 7 clock nets.
2020
[INFO CTS-0097] Characterization used 1 buffer(s) types.
2121
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
2222
[INFO CTS-0027] Generating H-Tree topology for net clk.
23-
[INFO CTS-0028] Total number of sinks: 4.
23+
[INFO CTS-0028] Total number of sinks: 3.
2424
[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 50.0 um.
2525
[INFO CTS-0030] Number of static layers: 1.
2626
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
@@ -35,7 +35,7 @@
3535
Sub-region size: 3.5489 X 3.0879
3636
[INFO CTS-0034] Segment length (rounded): 2.
3737
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
38-
[INFO CTS-0035] Number of sinks covered: 4.
38+
[INFO CTS-0035] Number of sinks covered: 3.
3939
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
4040
[INFO CTS-0027] Generating H-Tree topology for net clk_regs.
4141
[INFO CTS-0028] Total number of sinks: 144.
@@ -70,29 +70,6 @@
7070
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
7171
[INFO CTS-0035] Number of sinks covered: 144.
7272
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
73-
[INFO CTS-0027] Generating H-Tree topology for net gclk2.
74-
[INFO CTS-0028] Total number of sinks: 36.
75-
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
76-
[INFO CTS-0030] Number of static layers: 1.
77-
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
78-
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
79-
[INFO CTS-0023] Original sink region: [(8930, 96770), (97850, 130370)].
80-
[INFO CTS-0024] Normalized sink region: [(0.637857, 6.91214), (6.98929, 9.31214)].
81-
[INFO CTS-0025] Width: 6.3514.
82-
[INFO CTS-0026] Height: 2.4000.
83-
Level 1
84-
Direction: Horizontal
85-
Sinks per sub-region: 18
86-
Sub-region size: 3.1757 X 2.4000
87-
[INFO CTS-0034] Segment length (rounded): 1.
88-
Level 2
89-
Direction: Vertical
90-
Sinks per sub-region: 9
91-
Sub-region size: 3.1757 X 1.2000
92-
[INFO CTS-0034] Segment length (rounded): 1.
93-
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
94-
[INFO CTS-0035] Number of sinks covered: 36.
95-
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
9673
[INFO CTS-0027] Generating H-Tree topology for net gclk1.
9774
[INFO CTS-0028] Total number of sinks: 36.
9875
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
@@ -140,6 +117,24 @@
140117
[INFO CTS-0035] Number of sinks covered: 36.
141118
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
142119
[INFO CTS-0027] Generating H-Tree topology for net gclk4.
120+
[INFO CTS-0028] Total number of sinks: 1.
121+
[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 50.0 um.
122+
[INFO CTS-0030] Number of static layers: 1.
123+
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
124+
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
125+
[INFO CTS-0023] Original sink region: [(56825, 115390), (56825, 115390)].
126+
[INFO CTS-0024] Normalized sink region: [(4.05893, 8.24214), (4.05893, 8.24214)].
127+
[INFO CTS-0025] Width: 0.0000.
128+
[INFO CTS-0026] Height: 0.0000.
129+
Level 1
130+
Direction: Vertical
131+
Sinks per sub-region: 1
132+
Sub-region size: 0.0000 X 0.0000
133+
[INFO CTS-0034] Segment length (rounded): 1.
134+
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
135+
[INFO CTS-0035] Number of sinks covered: 1.
136+
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
137+
[INFO CTS-0027] Generating H-Tree topology for net gclk4_regs.
143138
[INFO CTS-0028] Total number of sinks: 36.
144139
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
145140
[INFO CTS-0030] Number of static layers: 1.
@@ -161,11 +156,34 @@
161156
[INFO CTS-0034] Segment length (rounded): 1.
162157
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
163158
[INFO CTS-0035] Number of sinks covered: 36.
159+
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
160+
[INFO CTS-0027] Generating H-Tree topology for net gclk2.
161+
[INFO CTS-0028] Total number of sinks: 36.
162+
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
163+
[INFO CTS-0030] Number of static layers: 1.
164+
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
165+
[INFO CTS-0021] Distance between buffers: 7 units (100 um).
166+
[INFO CTS-0023] Original sink region: [(8930, 96770), (97850, 130370)].
167+
[INFO CTS-0024] Normalized sink region: [(0.637857, 6.91214), (6.98929, 9.31214)].
168+
[INFO CTS-0025] Width: 6.3514.
169+
[INFO CTS-0026] Height: 2.4000.
170+
Level 1
171+
Direction: Horizontal
172+
Sinks per sub-region: 18
173+
Sub-region size: 3.1757 X 2.4000
174+
[INFO CTS-0034] Segment length (rounded): 1.
175+
Level 2
176+
Direction: Vertical
177+
Sinks per sub-region: 9
178+
Sub-region size: 3.1757 X 1.2000
179+
[INFO CTS-0034] Segment length (rounded): 1.
180+
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
181+
[INFO CTS-0035] Number of sinks covered: 36.
164182
[INFO CTS-0018] Created 3 clock buffers.
165183
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
166184
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
167185
[INFO CTS-0015] Created 3 clock nets.
168-
[INFO CTS-0016] Fanout distribution for the current clock = 2:2..
186+
[INFO CTS-0016] Fanout distribution for the current clock = 1:1, 2:1..
169187
[INFO CTS-0017] Max level of the clock tree: 1.
170188
[INFO CTS-0018] Created 17 clock buffers.
171189
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
@@ -177,55 +195,54 @@
177195
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
178196
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
179197
[INFO CTS-0015] Created 5 clock nets.
180-
[INFO CTS-0016] Fanout distribution for the current clock = 8:1, 9:2, 10:1..
198+
[INFO CTS-0016] Fanout distribution for the current clock = 8:2, 9:1, 11:1..
181199
[INFO CTS-0017] Max level of the clock tree: 2.
182200
[INFO CTS-0018] Created 5 clock buffers.
183201
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
184202
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
185203
[INFO CTS-0015] Created 5 clock nets.
186-
[INFO CTS-0016] Fanout distribution for the current clock = 8:2, 9:1, 11:1..
204+
[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 9:2, 11:1..
187205
[INFO CTS-0017] Max level of the clock tree: 2.
206+
[INFO CTS-0018] Created 2 clock buffers.
207+
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
208+
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
209+
[INFO CTS-0015] Created 2 clock nets.
210+
[INFO CTS-0016] Fanout distribution for the current clock = 1:1..
211+
[INFO CTS-0017] Max level of the clock tree: 1.
188212
[INFO CTS-0018] Created 5 clock buffers.
189213
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
190214
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
191215
[INFO CTS-0015] Created 5 clock nets.
192-
[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 9:2, 11:1..
216+
[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 9:1, 10:2..
193217
[INFO CTS-0017] Max level of the clock tree: 2.
194218
[INFO CTS-0018] Created 5 clock buffers.
195219
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
196220
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
197221
[INFO CTS-0015] Created 5 clock nets.
198-
[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 9:1, 10:2..
222+
[INFO CTS-0016] Fanout distribution for the current clock = 8:1, 9:2, 10:1..
199223
[INFO CTS-0017] Max level of the clock tree: 2.
200224
[INFO CTS-0098] Clock net "clk"
201-
[INFO CTS-0099] Sinks 4
225+
[INFO CTS-0099] Sinks 3
202226
[INFO CTS-0100] Leaf buffers 0
203-
[INFO CTS-0101] Average sink wire length 69.19 um
227+
[INFO CTS-0101] Average sink wire length 74.46 um
204228
[INFO CTS-0102] Path depth 2 - 2
205-
<<<<<<< HEAD
206-
[INFO CTS-0207] Leaf load cells 26
207-
=======
208229
[INFO CTS-0207] Dummy loads inserted 1
209-
>>>>>>> master
210230
[INFO CTS-0098] Clock net "clk_regs"
211231
[INFO CTS-0099] Sinks 159
212232
[INFO CTS-0100] Leaf buffers 0
213233
[INFO CTS-0101] Average sink wire length 45.22 um
214234
[INFO CTS-0102] Path depth 2 - 2
215-
<<<<<<< HEAD
216-
[INFO CTS-0207] Leaf load cells 26
217-
=======
218235
[INFO CTS-0207] Dummy loads inserted 15
219236
[INFO CTS-0098] Clock net "gclk1"
220237
[INFO CTS-0099] Sinks 39
221238
[INFO CTS-0100] Leaf buffers 0
222-
[INFO CTS-0101] Average sink wire length 27.44 um
239+
[INFO CTS-0101] Average sink wire length 24.86 um
223240
[INFO CTS-0102] Path depth 2 - 2
224241
[INFO CTS-0207] Dummy loads inserted 3
225242
[INFO CTS-0098] Clock net "gclk3"
226243
[INFO CTS-0099] Sinks 39
227244
[INFO CTS-0100] Leaf buffers 0
228-
[INFO CTS-0101] Average sink wire length 28.84 um
245+
[INFO CTS-0101] Average sink wire length 24.94 um
229246
[INFO CTS-0102] Path depth 2 - 2
230247
[INFO CTS-0207] Dummy loads inserted 3
231248
[INFO CTS-0124] Clock net "gclk4"
@@ -236,39 +253,24 @@
236253
[INFO CTS-0101] Average sink wire length 23.34 um
237254
[INFO CTS-0102] Path depth 2 - 2
238255
[INFO CTS-0207] Dummy loads inserted 2
239-
>>>>>>> master
240256
[INFO CTS-0098] Clock net "gclk2"
241257
[INFO CTS-0099] Sinks 39
242258
[INFO CTS-0100] Leaf buffers 0
243259
[INFO CTS-0101] Average sink wire length 24.92 um
244260
[INFO CTS-0102] Path depth 2 - 2
245-
<<<<<<< HEAD
246-
[INFO CTS-0207] Leaf load cells 26
247-
[INFO CTS-0098] Clock net "gclk1"
248-
[INFO CTS-0099] Sinks 39
249-
[INFO CTS-0100] Leaf buffers 0
250-
[INFO CTS-0101] Average sink wire length 24.86 um
251-
[INFO CTS-0102] Path depth 2 - 2
252-
[INFO CTS-0207] Leaf load cells 26
253-
[INFO CTS-0098] Clock net "gclk3"
254-
[INFO CTS-0099] Sinks 39
255-
[INFO CTS-0100] Leaf buffers 0
256-
[INFO CTS-0101] Average sink wire length 24.94 um
257-
[INFO CTS-0102] Path depth 2 - 2
258-
[INFO CTS-0207] Leaf load cells 26
259-
[INFO CTS-0098] Clock net "gclk4"
260-
[INFO CTS-0099] Sinks 38
261-
[INFO CTS-0100] Leaf buffers 0
262-
[INFO CTS-0101] Average sink wire length 25.21 um
263-
[INFO CTS-0102] Path depth 2 - 2
264-
[INFO CTS-0207] Leaf load cells 26
265-
=======
266261
[INFO CTS-0207] Dummy loads inserted 3
267-
>>>>>>> master
268262
[INFO CTS-0033] Balancing latency for clock clk
269-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (67792 148005)
270-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (120760 138230)
271-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_clk is inserted at (101013 149105)
272-
[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_clk is inserted at (102026 98350)
273-
[INFO CTS-0036] inserted 4 delay buffers
274-
[INFO CTS-0037] Total number of delay buffers: 4
263+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (137784 115191)
264+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (145397 114993)
265+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_clk is inserted at (73276 143117)
266+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_clk is inserted at (67792 148005)
267+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_clk is inserted at (62308 152892)
268+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_clk is inserted at (113760 138230)
269+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_clk is inserted at (120760 138230)
270+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_7_clk is inserted at (127760 138230)
271+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_8_clk is inserted at (100608 169407)
272+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_9_clk is inserted at (101216 138954)
273+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_10_clk is inserted at (101824 108501)
274+
[DEBUG CTS-insertion delay] new delay buffer delaybuf_11_clk is inserted at (102432 78048)
275+
[INFO CTS-0036] inserted 12 delay buffers
276+
[INFO CTS-0037] Total number of delay buffers: 12

‎src/cts/test/gated_clock4.ok‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -311,6 +311,4 @@ delta HPWL 49070 %
311311
[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_core is inserted at (1005080 1985475)
312312
[INFO CTS-0036] inserted 7 delay buffers
313313
[INFO CTS-0037] Total number of delay buffers: 7
314-
Differences found at line 4.
315-
wire delaynet_4_core;
316-
wire delaynet_3_core;
314+
No differences found.

‎src/cts/test/gated_clock4.vok‎

Lines changed: 20 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
11
module multi_sink (clk);
22
input clk;
33

4-
wire delaynet_4_core;
5-
wire clknet_1_0__leaf_clk;
4+
wire delaynet_3_core;
5+
wire clknet_1_1__leaf_clk;
66
wire gclk1;
77
wire gclk3;
88
wire gclk4;
99
wire gclk4_regs;
1010
wire clknet_0_clk;
11-
wire clknet_1_1__leaf_clk;
11+
wire clknet_1_0__leaf_clk;
1212
wire \clknet_4_0__leaf_h1/gclk5 ;
1313
wire \clknet_4_1__leaf_h1/gclk5 ;
1414
wire \clknet_4_2__leaf_h1/gclk5 ;
@@ -46,22 +46,19 @@ module multi_sink (clk);
4646
wire delaynet_0_core;
4747
wire delaynet_1_core;
4848
wire delaynet_2_core;
49-
wire delaynet_3_core;
49+
wire delaynet_4_core;
5050
wire delaynet_5_core;
5151
wire delaynet_6_core;
52-
wire delaynet_7_core;
5352

54-
CLKBUF_X3 delaybuf_7_core (.A(delaynet_6_core),
55-
.Z(delaynet_7_core));
56-
CLKBUF_X3 delaybuf_6_core (.A(clknet_0_clk),
53+
CLKBUF_X3 delaybuf_6_core (.A(delaynet_5_core),
5754
.Z(delaynet_6_core));
58-
CLKBUF_X3 delaybuf_5_core (.A(clknet_1_0__leaf_clk),
55+
CLKBUF_X3 delaybuf_5_core (.A(delaynet_4_core),
5956
.Z(delaynet_5_core));
60-
CLKBUF_X3 delaybuf_4_core (.A(delaynet_3_core),
57+
CLKBUF_X3 delaybuf_4_core (.A(clknet_0_clk),
6158
.Z(delaynet_4_core));
6259
CLKBUF_X3 delaybuf_3_core (.A(delaynet_2_core),
6360
.Z(delaynet_3_core));
64-
CLKBUF_X3 delaybuf_2_core (.A(clknet_1_1__leaf_clk),
61+
CLKBUF_X3 delaybuf_2_core (.A(clknet_1_0__leaf_clk),
6562
.Z(delaynet_2_core));
6663
CLKBUF_X3 delaybuf_1_core (.A(delaynet_0_core),
6764
.Z(delaynet_1_core));
@@ -127,9 +124,9 @@ module multi_sink (clk);
127124
INV_X2 clkload2 (.A(\clknet_4_2__leaf_h1/gclk5 ));
128125
INV_X4 clkload1 (.A(\clknet_4_1__leaf_h1/gclk5 ));
129126
INV_X4 clkload0 (.A(\clknet_4_0__leaf_h1/gclk5 ));
130-
CLKBUF_X3 clkbuf_1_1__f_clk (.A(clknet_0_clk),
127+
CLKBUF_X3 clkbuf_1_1__f_clk (.A(delaynet_6_core),
131128
.Z(clknet_1_1__leaf_clk));
132-
CLKBUF_X3 clkbuf_1_0__f_clk (.A(delaynet_7_core),
129+
CLKBUF_X3 clkbuf_1_0__f_clk (.A(clknet_0_clk),
133130
.Z(clknet_1_0__leaf_clk));
134131
CLKBUF_X3 clkbuf_0_clk (.A(clk),
135132
.Z(clknet_0_clk));
@@ -243,19 +240,19 @@ module multi_sink (clk);
243240
DFF_X1 ff285 (.CK(clknet_2_0__leaf_gclk3));
244241
DFF_X1 ff286 (.CK(clknet_2_2__leaf_gclk3));
245242
DFF_X1 ff287 (.CK(clknet_2_3__leaf_gclk3));
246-
CLKGATE_X1 gclk1 (.CK(delaynet_5_core),
243+
CLKGATE_X1 gclk1 (.CK(clknet_1_1__leaf_clk),
247244
.GCK(gclk1));
248245
CLKGATE_X1 gclk3 (.CK(clknet_1_0__leaf_gclk4),
249246
.GCK(gclk3));
250-
CLKGATE_X1 gclk4 (.CK(clknet_1_1__leaf_clk),
247+
CLKGATE_X1 gclk4 (.CK(clknet_1_0__leaf_clk),
251248
.GCK(gclk4));
252-
hier_block h1 (.delaynet_4_core_i(delaynet_4_core),
253-
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
249+
hier_block h1 (.delaynet_3_core_i(delaynet_3_core),
250+
.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk));
254251
endmodule
255-
module hier_block (delaynet_4_core_i,
256-
clknet_1_0__leaf_clk_i);
257-
input delaynet_4_core_i;
258-
input clknet_1_0__leaf_clk_i;
252+
module hier_block (delaynet_3_core_i,
253+
clknet_1_1__leaf_clk_i);
254+
input delaynet_3_core_i;
255+
input clknet_1_1__leaf_clk_i;
259256

260257
wire gclk2;
261258
wire gclk5;
@@ -496,8 +493,8 @@ module hier_block (delaynet_4_core_i,
496493
DFF_X1 ff97 (.CK(\clknet_4_15__leaf_h1/gclk5 ));
497494
DFF_X1 ff98 (.CK(\clknet_4_4__leaf_h1/gclk5 ));
498495
DFF_X1 ff99 (.CK(\clknet_4_13__leaf_h1/gclk5 ));
499-
CLKGATE_X1 gclk2 (.CK(delaynet_4_core_i),
496+
CLKGATE_X1 gclk2 (.CK(clknet_1_1__leaf_clk_i),
500497
.GCK(gclk2));
501-
CLKGATE_X1 gclk5 (.CK(clknet_1_0__leaf_clk_i),
498+
CLKGATE_X1 gclk5 (.CK(delaynet_3_core_i),
502499
.GCK(gclk5));
503500
endmodule

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