Merge remote-tracking branch 'origin/master' into dpl-remove-pad-fillers

Author: gadfort

Jenkinsfile

@@ -221,9 +221,10 @@ def bazelTest = {
             stage('bazelisk test ...') {
                 withCredentials([string(credentialsId: 'bazel-auth-token-b64', variable: 'BAZEL_AUTH_TOKEN_B64')]) {
                     timeout(time: 120, unit: 'MINUTES') {
-                        def cmd = 'bazelisk test --config=ci --show_timestamps --test_output=errors --curses=no --force_pic --remote_header="Authorization=Basic $BAZEL_AUTH_TOKEN_B64"'
+                        def cmd = 'bazelisk test --config=ci --show_timestamps --test_output=errors --curses=no --force_pic --remote_header="Authorization=Basic $BAZEL_AUTH_TOKEN_B64" --profile=build.profile'
                         try {
                             sh label: 'Bazel Build', script: cmd + ' ...';
+                            sh label: 'Bazel Build', script: 'bazelisk analyze-profile build.profile';
                         } catch (e) {
                             currentBuild.result = 'FAILURE';
                             sh label: 'Bazel Build (keep_going)', script: cmd + ' --keep_going ...';

src/cts/test/BUILD

@@ -161,6 +161,9 @@ filegroup(
             "max_cap": [
                 "//src/rsz/test:hi_fanout.tcl",
             ],
+            "skip_nets": [
+                "gated_clock2.def",
+            ],
         }.get(test_name, []),
     )
     for test_name in ALL_TESTS

src/cts/test/skip_nets.ok

@@ -131,9 +131,9 @@ CTS config:
 [INFO CTS-0016]     Fanout distribution for the current clock = 8:1, 9:2, 10:1..
 [INFO CTS-0017]     Max level of the clock tree: 2.
 [INFO CTS-0098] Clock net "clk"
-[INFO CTS-0099]  Sinks 3
+[INFO CTS-0099]  Sinks 2
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 57.59 um
+[INFO CTS-0101]  Average sink wire length 47.55 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 18
 [INFO CTS-0098] Clock net "clk_regs"
@@ -148,9 +148,6 @@ CTS config:
 [INFO CTS-0101]  Average sink wire length 29.38 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 18
-[DEBUG CTS-insertion delay] top buffer delay for macro tree clkbuf_0_clk is 2.666e-11
-[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_regs_0_clk is 2.480e-11
-[DEBUG CTS-insertion delay] top buffer delay for register tree clkbuf_0_gclk2 is 3.492e-11
 [INFO CTS-0033] Balancing latency for clock clk
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_0_clk is inserted at (100608 169407)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (101216 138954)

src/ram/CMakeLists.txt

@@ -62,21 +62,21 @@ messages(
   TARGET ram
 )
 
-#if (Python3_FOUND AND BUILD_PYTHON)
-#  swig_lib(NAME          ram_py
-#           NAMESPACE     ram
-#           LANGUAGE      python
-#           I_FILE        src/ram-py.i
-#           SWIG_INCLUDES ${PROJECT_SOURCE_DIR}/include/ram
-#           SCRIPTS       ${CMAKE_CURRENT_BINARY_DIR}/ram_py.py
-#  )
-#
-#  target_link_libraries(ram_py
-#    PUBLIC
-#      ram
-#      odb
-#  )
-#
-#endif()
+if (Python3_FOUND AND BUILD_PYTHON)
+  swig_lib(NAME          ram_py
+           NAMESPACE     ram
+           LANGUAGE      python
+           I_FILE        src/ram-py.i
+           SWIG_INCLUDES ${PROJECT_SOURCE_DIR}/include/ram
+           SCRIPTS       ${CMAKE_CURRENT_BINARY_DIR}/ram_py.py
+  )
+
+  target_link_libraries(ram_py
+    PUBLIC
+      ram
+      odb
+  )
+
+endif()
 
 add_subdirectory(test)

src/ram/include/ram/ram.h

@@ -90,15 +90,15 @@ class RamGen
 
   sta::dbNetwork* network_;
   odb::dbDatabase* db_;
-  odb::dbBlock* block_;
+  odb::dbBlock* block_{nullptr};
   Logger* logger_;
 
-  odb::dbMaster* storage_cell_;
-  odb::dbMaster* tristate_cell_;
-  odb::dbMaster* inv_cell_;
-  odb::dbMaster* and2_cell_;
-  odb::dbMaster* clock_gate_cell_;
-  odb::dbMaster* buffer_cell_;
+  odb::dbMaster* storage_cell_{nullptr};
+  odb::dbMaster* tristate_cell_{nullptr};
+  odb::dbMaster* inv_cell_{nullptr};
+  odb::dbMaster* and2_cell_{nullptr};
+  odb::dbMaster* clock_gate_cell_{nullptr};
+  odb::dbMaster* buffer_cell_{nullptr};
 };
 
 }  // namespace ram

src/ram/src/ram-py.i

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2022-2025, The OpenROAD Authors
+
+%{
+#include "ord/OpenRoad.hh"
+#include "ram/ram.h"
+
+%}
+
+%include "../../Exception-py.i"
+%include "ram/ram.h"