Logic hierarchy breakdown in GUI

[aviadb]

Hello,
Trying to do some area estimations for optimizations and area reduction.
Is there an option to see the logic hierarchy breakdown in GUI or reports?
For example taking the riscv32i design

I see 0 modules instantiated under the top and no breakdown per logic hierarchy.

[maliberty]

You need to preserve those hierarchy in synthesis in order to be able to see them in openroad. Doing so comes with some loss of efficiency as you get no cross boundary optimization (though there is some in progress for that in yosys).

[mi-and-core]

As maliberty says setting ...something... like

export SYNTH_HIERARCHICAL = 1
export RTLMP_MAX_LEVEL = 3

in your designs config.mk will results like this:

[aviadb]

Thank you @mi-and-core ,
that is exactly what I was looking for.

Any option to do run comparison?
I am using the OpenROAD-flow-scripts, and executing the make file creates a "base" run.
Is it possible to do a clean run with a different name so that I can compare the two?

[maliberty]

Orfs has the FLOW_VARIANT variable for this purpose

[aviadb]

Thanks