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There are abc and yosys commands to recover names via SAT sweeping which attempts to find equivalent nets before and after mapping. I don't have first hand experience of using it so can't qualify how easy it would be to set up. |
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Has Yosys gotten any new features w.r.t. better, more readable, signal names for timing reports that ORFS is not using?
Ideally wire names in the Verilog would be used as well as register names to form more helpful names.
Usually I get something like this in timing reports:
intelligble register name -> blob of gates names 23525 etc. -> intelligble register name
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