Hold Violations after SPEF Extraction

[mole99]

Hi! I need some help regarding CTS on my chip Greyhound using the IHP Open PDK.

I had the same problem as I do now with my first tapeout of Greyhound: https://github.com/mole99/greyhound-ihp/tree/main
As you can see, there is a huge macro in the middle, the eFPGA fabric. Below the eFPGA fabric is the core area for the SoC.

At the time, I disabled cell placement to the left of the eFPGA, since if I didn't, I got hold violations after SPEF extraction - the reason being that the clock tree was completely skewed. Before SPEF extraction, STA was fine.

If I disable cell placement to the left of the eFPGA, that means I have to route 32*16 wires through that gap, as they need to connect to the left side of the eFPGA macro. If I enable cell placement, the FrameData registers can be placed next to their respective rows, which means 32 wires + a few select lines, allowing me to save area for another column of CLBs (Configurable Logic Blocks) increasing the capacity of the eFPGA.

After the first tapeout, Donn pointed me to this issue: #6651
This would have matched exactly what I saw: when the FrameData registers are placed to the left of the eFPGA, I get long vertical clock wires, which could have lead to the discrepancy between RC values and SPEF extraction due to this issue.

I'm currently working on the second revision of Greyhound with an updated version of LibreLane that contains this bug fix. Unfortunately, I still get hold violations after SPEF extraction when I enable cell placement to the left of the eFPGA.

Clock tree before SPEF extraction:

Clock tree after SPEF extraction:

(By the way, I'm using a hierarchical netlist, but flattened the outcome is the same.)

The command (or variants of it) that I use to run CTS is:

clock_tree_synthesis -buf_list sg13g2_buf_8 sg13g2_buf_4 sg13g2_buf_2 -root_buf sg13g2_buf_16 -sink_clustering_enable -obstruction_aware     

I also tried disabling -sink_clustering_enable, but it gives me even worse results.

I also tried to manually specify -sink_clustering_max_diameter 50 and -sink_clustering_max_diameter 250, but no improvement.

-sink_clustering_size is limited to 8 anyways for this technology, as I found out in: #8111

Also, the placement of the clock buffers is odd. The clock buffers appear to be mostly placed on a central horizontal spine in the middle of the bottom core area.

I traced this part of the clock tree and it goes all the way up to the center left of the eFPGA before going all the way down to the bottom left corner where the IO pad for the clock is located. So it seems that CTS creates unnecessary long paths for the sinks, but it doesn't seem to notice, since before SPEF extraction STA is fine.

Are the RC constants correct? OpenROAD uses the RC constants from the tech lef, so I verified the following.

Metal1 from tech lef:

  WIDTH		0.16 ;
  CAPACITANCE  CPERSQDIST 3.49E-05 ;
  RESISTANCE RPERSQ 0.135 ;

Calculation for the resistance: 0.135 / 0.16 = 0.84375

For the capacitance I'm not sure how to calculate the "Cap/Unit Distance", maybe someone can help me there?

Cont from techlef:

  RESISTANCE 22.0 ;

The resistances matches the values in OpenROAD:

== Technology LEF Values ==
=== Routing Layers ===
Name                Direction           Res/Unit Distance   Cap/Unit Distance   
Metal1              HORIZONTAL          8.437500e-04        6.878400e-05        
Metal2              VERTICAL            5.150000e-04        9.302000e-05        
Metal3              HORIZONTAL          5.150000e-04        9.200000e-05        
Metal4              VERTICAL            5.150000e-04        9.178800e-05        
Metal5              HORIZONTAL          5.150000e-04        8.882600e-05        
TopMetal1           VERTICAL            1.280488e-05        1.108496e-04        
TopMetal2           HORIZONTAL          7.250000e-06        9.006000e-05        
=== Vias ===
Name                Cut Resistance      
Cont                2.200000e-02        
Via1                2.000000e-02        
Via2                2.000000e-02        
Via3                2.000000e-02        
Via4                2.000000e-02        
TopVia1             4.000000e-03        
TopVia2             2.200000e-03

I assume the other layers match as well...

But maybe the units are not matching? Should 8.437500e-04 be 8.437500e-01?

Maybe I can artificially increase the routing resistance in order to get the CTS to notice the parasitics?

Another possibility is that the SPEF values are incorrect. But I have no reason to believe that, since they uncovered real issues in my design i.e. the clock path for a sink is going all across the chip.

Is this a limitation due to the strange shape of my core area? Is something else going wrong?
Does anyone have any suggestions for me to try or knows what could be the issue?

I use LibreLane, so reproducing might be a little more difficult/unusual for you. But I can easily provide an ODB from any step of the flow if that helps.

[maliberty]

Does your design have clock gating? What version of OR are you using as there have been a lot of recent improvements? What layers are you assuming for clocks (eg set_wire_rc) and do they match the final layers well? Are you using the values from LEF or from set_layer_rc?

[mole99]

Yes, it uses clock gating. One clock gate for the CV32E40X RISC-V CPU and one for the UART peripheral. You can see both in the clock tree as the two pink lines and they both look balanced. The one on the very right is the UART, the one left to it is the CPU.

The issue seems to be that the cache (placed at the bottom) is mixed with the FrameData registers (placed to the left of the eFPGA) in the clock tree, resulting in these long traces. But the real issue is that this problem doesn't show up before SPEF extraction.

Funny idea: Can I use a clock gate that is always enabled on the cache (or the FrameDate registers respectively) to separate them in the clock tree?

---

The LibreLane development branch is currently at:

commit 341650e72dad0dc8571822ff8c5d9c5e365327f7 (HEAD)
Merge: b50549ba07 e5bf71446e
Author: Matt Liberty <[email protected]>
Date:   Wed Jun 11 17:12:45 2025 -0700

Which should be recent enough, I think most of the CTS work was prior to that, correct?

---

This is what is set when I use the values from the tech LEF:

+ set_wire_rc_wrapper
+ set_wire_rc -clock -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2
+ set_wire_rc -signal -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2

This is when I set the values manually:

Spoiler: set_layer_rc

``` + set_layer_rc -layer Metal1 -capacitance 0.0000349 -corner nom_fast_1p32V_m40C -resistance 0.000135 + set_layer_rc -layer Metal2 -capacitance 0.0000181 -corner nom_fast_1p32V_m40C -resistance 0.000103 + set_layer_rc -layer Metal3 -capacitance 0.000214962 -corner nom_fast_1p32V_m40C -resistance 0.000103 + set_layer_rc -layer Metal4 -capacitance 0.000148128 -corner nom_fast_1p32V_m40C -resistance 0.000103 + set_layer_rc -layer Metal5 -capacitance 0.000154087 -corner nom_fast_1p32V_m40C -resistance 0.000103 + set_layer_rc -layer TopMetal1 -capacitance 0.000154087 -corner nom_fast_1p32V_m40C -resistance 0.000021 + set_layer_rc -layer TopMetal2 -capacitance 0.000154087 -corner nom_fast_1p32V_m40C -resistance 0.0000145 + set_layer_rc -layer Metal1 -capacitance 0.0000349 -corner nom_slow_1p08V_125C -resistance 0.000135 + set_layer_rc -layer Metal2 -capacitance 0.0000181 -corner nom_slow_1p08V_125C -resistance 0.000103 + set_layer_rc -layer Metal3 -capacitance 0.000214962 -corner nom_slow_1p08V_125C -resistance 0.000103 + set_layer_rc -layer Metal4 -capacitance 0.000148128 -corner nom_slow_1p08V_125C -resistance 0.000103 + set_layer_rc -layer Metal5 -capacitance 0.000154087 -corner nom_slow_1p08V_125C -resistance 0.000103 + set_layer_rc -layer TopMetal1 -capacitance 0.000154087 -corner nom_slow_1p08V_125C -resistance 0.000021 + set_layer_rc -layer TopMetal2 -capacitance 0.000154087 -corner nom_slow_1p08V_125C -resistance 0.0000145 + set_layer_rc -layer Metal1 -capacitance 0.0000349 -corner nom_typ_1p20V_25C -resistance 0.000135 + set_layer_rc -layer Metal2 -capacitance 0.0000181 -corner nom_typ_1p20V_25C -resistance 0.000103 + set_layer_rc -layer Metal3 -capacitance 0.000214962 -corner nom_typ_1p20V_25C -resistance 0.000103 + set_layer_rc -layer Metal4 -capacitance 0.000148128 -corner nom_typ_1p20V_25C -resistance 0.000103 + set_layer_rc -layer Metal5 -capacitance 0.000154087 -corner nom_typ_1p20V_25C -resistance 0.000103 + set_layer_rc -layer TopMetal1 -capacitance 0.000154087 -corner nom_typ_1p20V_25C -resistance 0.000021 + set_layer_rc -layer TopMetal2 -capacitance 0.000154087 -corner nom_typ_1p20V_25C -resistance 0.0000145 + set_layer_rc -via Cont -resistance 0.0022 -corner nom_fast_1p32V_m40C + set_layer_rc -via Via1 -resistance 0.0020 -corner nom_fast_1p32V_m40C + set_layer_rc -via Via2 -resistance 0.0020 -corner nom_fast_1p32V_m40C + set_layer_rc -via Via3 -resistance 0.0020 -corner nom_fast_1p32V_m40C + set_layer_rc -via Via4 -resistance 0.0020 -corner nom_fast_1p32V_m40C + set_layer_rc -via TopVia1 -resistance 0.0004 -corner nom_fast_1p32V_m40C + set_layer_rc -via TopVia2 -resistance 0.00022 -corner nom_fast_1p32V_m40C + set_layer_rc -via Cont -resistance 0.0022 -corner nom_slow_1p08V_125C + set_layer_rc -via Via1 -resistance 0.0020 -corner nom_slow_1p08V_125C + set_layer_rc -via Via2 -resistance 0.0020 -corner nom_slow_1p08V_125C + set_layer_rc -via Via3 -resistance 0.0020 -corner nom_slow_1p08V_125C + set_layer_rc -via Via4 -resistance 0.0020 -corner nom_slow_1p08V_125C + set_layer_rc -via TopVia1 -resistance 0.0004 -corner nom_slow_1p08V_125C + set_layer_rc -via TopVia2 -resistance 0.00022 -corner nom_slow_1p08V_125C + set_layer_rc -via Cont -resistance 0.0022 -corner nom_typ_1p20V_25C + set_layer_rc -via Via1 -resistance 0.0020 -corner nom_typ_1p20V_25C + set_layer_rc -via Via2 -resistance 0.0020 -corner nom_typ_1p20V_25C + set_layer_rc -via Via3 -resistance 0.0020 -corner nom_typ_1p20V_25C + set_layer_rc -via Via4 -resistance 0.0020 -corner nom_typ_1p20V_25C + set_layer_rc -via TopVia1 -resistance 0.0004 -corner nom_typ_1p20V_25C + set_layer_rc -via TopVia2 -resistance 0.00022 -corner nom_typ_1p20V_25C + set_layers_default_rc + set_vias_default_r + set_wire_rc_wrapper -use_corners + set_wire_rc -clock -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_fast_1p32V_m40C + set_wire_rc -signal -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_fast_1p32V_m40C + set_wire_rc -clock -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_slow_1p08V_125C + set_wire_rc -signal -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_slow_1p08V_125C + set_wire_rc -clock -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_typ_1p20V_25C + set_wire_rc -signal -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_typ_1p20V_25C + set_layer_rc -layer Metal1 -capacitance 0.0000349 -corner nom_fast_1p32V_m40C -resistance 0.000135 + set_layer_rc -layer Metal2 -capacitance 0.0000181 -corner nom_fast_1p32V_m40C -resistance 0.000103 + set_layer_rc -layer Metal3 -capacitance 0.000214962 -corner nom_fast_1p32V_m40C -resistance 0.000103 + set_layer_rc -layer Metal4 -capacitance 0.000148128 -corner nom_fast_1p32V_m40C -resistance 0.000103 + set_layer_rc -layer Metal5 -capacitance 0.000154087 -corner nom_fast_1p32V_m40C -resistance 0.000103 + set_layer_rc -layer TopMetal1 -capacitance 0.000154087 -corner nom_fast_1p32V_m40C -resistance 0.000021 + set_layer_rc -layer TopMetal2 -capacitance 0.000154087 -corner nom_fast_1p32V_m40C -resistance 0.0000145 + set_layer_rc -layer Metal1 -capacitance 0.0000349 -corner nom_slow_1p08V_125C -resistance 0.000135 + set_layer_rc -layer Metal2 -capacitance 0.0000181 -corner nom_slow_1p08V_125C -resistance 0.000103 + set_layer_rc -layer Metal3 -capacitance 0.000214962 -corner nom_slow_1p08V_125C -resistance 0.000103 + set_layer_rc -layer Metal4 -capacitance 0.000148128 -corner nom_slow_1p08V_125C -resistance 0.000103 + set_layer_rc -layer Metal5 -capacitance 0.000154087 -corner nom_slow_1p08V_125C -resistance 0.000103 + set_layer_rc -layer TopMetal1 -capacitance 0.000154087 -corner nom_slow_1p08V_125C -resistance 0.000021 + set_layer_rc -layer TopMetal2 -capacitance 0.000154087 -corner nom_slow_1p08V_125C -resistance 0.0000145 + set_layer_rc -layer Metal1 -capacitance 0.0000349 -corner nom_typ_1p20V_25C -resistance 0.000135 + set_layer_rc -layer Metal2 -capacitance 0.0000181 -corner nom_typ_1p20V_25C -resistance 0.000103 + set_layer_rc -layer Metal3 -capacitance 0.000214962 -corner nom_typ_1p20V_25C -resistance 0.000103 + set_layer_rc -layer Metal4 -capacitance 0.000148128 -corner nom_typ_1p20V_25C -resistance 0.000103 + set_layer_rc -layer Metal5 -capacitance 0.000154087 -corner nom_typ_1p20V_25C -resistance 0.000103 + set_layer_rc -layer TopMetal1 -capacitance 0.000154087 -corner nom_typ_1p20V_25C -resistance 0.000021 + set_layer_rc -layer TopMetal2 -capacitance 0.000154087 -corner nom_typ_1p20V_25C -resistance 0.0000145 + set_layer_rc -via Cont -resistance 0.0022 -corner nom_fast_1p32V_m40C + set_layer_rc -via Via1 -resistance 0.0020 -corner nom_fast_1p32V_m40C + set_layer_rc -via Via2 -resistance 0.0020 -corner nom_fast_1p32V_m40C + set_layer_rc -via Via3 -resistance 0.0020 -corner nom_fast_1p32V_m40C + set_layer_rc -via Via4 -resistance 0.0020 -corner nom_fast_1p32V_m40C + set_layer_rc -via TopVia1 -resistance 0.0004 -corner nom_fast_1p32V_m40C + set_layer_rc -via TopVia2 -resistance 0.00022 -corner nom_fast_1p32V_m40C + set_layer_rc -via Cont -resistance 0.0022 -corner nom_slow_1p08V_125C + set_layer_rc -via Via1 -resistance 0.0020 -corner nom_slow_1p08V_125C + set_layer_rc -via Via2 -resistance 0.0020 -corner nom_slow_1p08V_125C + set_layer_rc -via Via3 -resistance 0.0020 -corner nom_slow_1p08V_125C + set_layer_rc -via Via4 -resistance 0.0020 -corner nom_slow_1p08V_125C + set_layer_rc -via TopVia1 -resistance 0.0004 -corner nom_slow_1p08V_125C + set_layer_rc -via TopVia2 -resistance 0.00022 -corner nom_slow_1p08V_125C + set_layer_rc -via Cont -resistance 0.0022 -corner nom_typ_1p20V_25C + set_layer_rc -via Via1 -resistance 0.0020 -corner nom_typ_1p20V_25C + set_layer_rc -via Via2 -resistance 0.0020 -corner nom_typ_1p20V_25C + set_layer_rc -via Via3 -resistance 0.0020 -corner nom_typ_1p20V_25C + set_layer_rc -via Via4 -resistance 0.0020 -corner nom_typ_1p20V_25C + set_layer_rc -via TopVia1 -resistance 0.0004 -corner nom_typ_1p20V_25C + set_layer_rc -via TopVia2 -resistance 0.00022 -corner nom_typ_1p20V_25C + set_layers_default_rc + set_vias_default_r + set_wire_rc_wrapper -use_corners + set_wire_rc -clock -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_fast_1p32V_m40C + set_wire_rc -signal -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_fast_1p32V_m40C + set_wire_rc -clock -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_slow_1p08V_125C + set_wire_rc -signal -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_slow_1p08V_125C + set_wire_rc -clock -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_typ_1p20V_25C + set_wire_rc -signal -layers Metal2 Metal3 Metal4 Metal5 TopMetal1 TopMetal2 -corner nom_typ_1p20V_25C ```

I tried both with the same results.

Good point! Those layers are averaged, right? So the upper metal layers can skew the resistance a lot. The clock tree mostly uses Metal2 to Metal5, so let me try to remove TopMetal1 and TopMetal2 from set_wire_rc.

[mole99]

Indeed, it helped a bit!

+ set_wire_rc_wrapper
+ set_wire_rc -clock -layers Metal2 Metal3 Metal4 Metal5
+ set_wire_rc -signal -layers Metal2 Metal3 Metal4 Metal5

No hold violations in the slow corner, but still plenty in the typical and fast corner.

[maliberty]

You should try head of OR

[mole99]

Thanks Matt for taking a look.
Unfortunately, I can still reproduce the crash. I'm using the latest OpenROAD, which is now d97df48:

Spoiler log

OpenROAD d97df4813dba18edcd0e1bf17d7d0430fefb56c0 
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
openroad> define_corners fast_1p32V_m40C slow_1p08V_125C typ_1p20V_25C
openroad> read_liberty -corner fast_1p32V_m40C libs/RM_IHPSG13_1P_512x32_c2_bm_bist_fast_1p32V_m55C.lib
read_liberty -corner slow_1p08V_125C libs/RM_IHPSG13_1P_512x32_c2_bm_bist_slow_1p08V_125C.lib
read_liberty -corner typ_1p20V_25C libs/RM_IHPSG13_1P_512x32_c2_bm_bist_typ_1p20V_25C.lib

read_liberty -corner fast_1p32V_m40C libs/RM_IHPSG13_1P_1024x32_c2_bm_bist_fast_1p32V_m55C.lib
read_liberty -corner slow_1p08V_125C libs/RM_IHPSG13_1P_1024x32_c2_bm_bist_slow_1p08V_125C.lib
read_liberty -corner typ_1p20V_25C libs/RM_IHPSG13_1P_1024x32_c2_bm_bist_typ_1p20V_25C.lib

read_liberty -corner fast_1p32V_m40C libs/sg13g2_io_fast_1p32V_3p6V_m40C.lib
read_liberty -corner slow_1p08V_125C libs/sg13g2_io_slow_1p08V_3p0V_125C.lib
read_liberty -corner typ_1p20V_25C libs/sg13g2_io_typ_1p2V_3p3V_25C.lib

read_liberty -corner fast_1p32V_m40C libs/sg13g2_stdcell_fast_1p32V_m40C.lib
read_liberty -corner slow_1p08V_125C libs/sg13g2_stdcell_slow_1p08V_125C.lib
read_liberty -corner typ_1p20V_25C libs/sg13g2_stdcell_typ_1p20V_25C.lib
1
openroad> read_db greyhound_ihp_top.odb
openroad> source _env.tcl
read_sdc constraint.sdc
set_propagated_clock [all_clocks]
openroad> set_wire_rc -clock -layers "Metal2 Metal3 Metal4 Metal5"
set_wire_rc -signal -layers "Metal2 Metal3 Metal4 Metal5"
openroad> estimate_parasitics -placement
openroad> repair_timing -verbose -setup -setup_margin 0.05000000000000000277555756156289135105907917022705078125 -max_buffer_percent 50
[INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove 
[INFO RSZ-0094] Found 3818 endpoints with setup violations.
[INFO RSZ-0099] Repairing 3818 out of 3818 (100.00%) violating endpoints...
   Iter   | Removed | Resized | Inserted | Cloned |  Pin  |   Area   |    WNS   |   TNS      |  Viol  | Worst
          | Buffers |  Gates  | Buffers  |  Gates | Swaps |          |          |            | Endpts | Endpt
--------------------------------------------------------------------------------------------------------------
        0 |       0 |       0 |        0 |      0 |     0 |    +0.0% |  -23.615 |   -71727.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12740_/D
       10 |       1 |       8 |        0 |      0 |     0 |    -0.0% |  -20.711 |   -63017.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12099_/D
       20 |       1 |      18 |        0 |      0 |     0 |    -0.0% |  -20.219 |   -62830.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_11077_/D
       30 |       1 |      24 |        2 |      0 |     2 |    -0.0% |  -19.696 |   -61345.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
       40 |       1 |      32 |        3 |      0 |     3 |    -0.0% |  -18.834 |   -58751.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
       50 |       2 |      40 |        3 |      0 |     4 |    -0.0% |  -18.010 |   -56163.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_11894_/D
       60 |       4 |      46 |        4 |      0 |     5 |    -0.0% |  -17.604 |   -55338.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
       70 |       5 |      54 |        6 |      0 |     5 |    -0.0% |  -16.815 |   -52196.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_237_/D
       80 |       5 |      63 |        7 |      0 |     5 |    -0.0% |  -16.476 |   -52098.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_11347_/D
       90 |       5 |      73 |        7 |      0 |     5 |    -0.0% |  -16.252 |   -51770.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
      100 |       5 |      81 |        8 |      0 |     6 |    -0.0% |  -16.060 |   -51033.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
      110 |       6 |      87 |       10 |      0 |     7 |    -0.0% |  -15.795 |   -50178.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
      120 |       8 |      94 |       11 |      0 |     7 |    -0.0% |  -15.211 |   -47994.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
      130 |       8 |     104 |       11 |      0 |     7 |    -0.0% |  -14.877 |   -46962.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_210_/D
      140 |       8 |     114 |       11 |      0 |     7 |    -0.0% |  -14.361 |   -45293.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      150 |       9 |     121 |       12 |      0 |     8 |    -0.0% |  -14.174 |   -44493.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      160 |       9 |     130 |       12 |      0 |     9 |    -0.0% |  -13.927 |   -43972.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_227_/D
      170 |       9 |     136 |       14 |      0 |    11 |    -0.0% |  -13.802 |   -43602.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_218_/D
      180 |      11 |     144 |       14 |      0 |    11 |    -0.0% |  -13.707 |   -43412.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12159_/D
      190 |      11 |     154 |       14 |      0 |    11 |    -0.0% |  -13.508 |   -42880.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      200 |      12 |     161 |       15 |      0 |    12 |    -0.0% |  -12.900 |   -40401.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      210 |      13 |     169 |       16 |      0 |    12 |    -0.0% |  -12.776 |   -40058.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12405_/D
      220 |      13 |     179 |       16 |      0 |    12 |    -0.0% |  -12.696 |   -39822.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12754_/D
      230 |      13 |     188 |       17 |      0 |    12 |    -0.0% |  -12.282 |   -38243.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      240 |      13 |     194 |       18 |      0 |    15 |    -0.0% |  -12.030 |   -37145.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_210_/D
      250 |      13 |     203 |       18 |      0 |    16 |    -0.0% |  -11.676 |   -36096.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_223_/D
      260 |      14 |     210 |       19 |      0 |    17 |    -0.0% |  -11.530 |   -35835.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
      270 |      14 |     219 |       19 |      0 |    18 |    -0.0% |  -11.290 |   -34586.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      280 |      15 |     228 |       19 |      0 |    18 |    -0.0% |  -11.009 |   -33519.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      290 |      16 |     236 |       19 |      0 |    19 |    -0.0% |  -10.855 |   -32935.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      300 |      17 |     243 |       21 |      0 |    20 |    -0.0% |  -10.716 |   -32410.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      310 |      19 |     249 |       22 |      0 |    21 |    -0.0% |  -10.620 |   -32051.2 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      320 |      19 |     257 |       23 |      0 |    22 |    -0.0% |  -10.448 |   -31407.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      330 |      19 |     267 |       23 |      0 |    22 |    -0.0% |  -10.365 |   -31099.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      340 |      19 |     275 |       24 |      0 |    23 |    -0.0% |  -10.227 |   -30583.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      350 |      21 |     280 |       25 |      0 |    25 |    -0.0% |  -10.159 |   -30330.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      360 |      22 |     287 |       27 |      0 |    25 |    -0.0% |  -10.012 |   -29771.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      370 |      24 |     294 |       27 |      0 |    26 |    -0.0% |   -9.244 |   -26904.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      380 |      25 |     303 |       27 |      0 |    26 |    -0.0% |   -9.173 |   -26638.2 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      390 |      26 |     312 |       27 |      0 |    26 |    -0.0% |   -9.048 |   -26164.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      400 |      28 |     320 |       27 |      0 |    26 |    -0.0% |   -8.918 |   -25677.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      410 |      32 |     326 |       27 |      0 |    26 |    -0.0% |   -8.838 |   -25376.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      420 |      33 |     332 |       28 |      0 |    28 |    -0.0% |   -8.789 |   -25167.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      430 |      34 |     341 |       28 |      0 |    28 |    -0.0% |   -8.703 |   -24860.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      440 |      36 |     348 |       29 |      0 |    28 |    -0.0% |   -8.647 |   -24654.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      450 |      36 |     358 |       29 |      0 |    28 |    -0.0% |   -8.578 |   -24397.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      460 |      38 |     364 |       31 |      0 |    29 |    -0.0% |   -8.502 |   -24112.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      470 |      38 |     372 |       33 |      0 |    29 |    -0.0% |   -8.419 |   -23797.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      480 |      38 |     373 |       43 |      0 |    29 |    -0.0% |   -8.407 |   -23751.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      490 |      38 |     380 |       44 |      0 |    31 |    -0.0% |   -8.316 |   -23311.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1247_/D
      500 |      38 |     390 |       44 |      0 |    31 |    -0.0% |   -8.222 |   -23061.2 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
      510 |      40 |     398 |       44 |      0 |    31 |    -0.0% |   -8.125 |   -22231.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
      520 |      40 |     406 |       45 |      0 |    32 |    -0.0% |   -7.836 |   -21288.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_230_/D
      530 |      40 |     415 |       45 |      0 |    33 |    -0.0% |   -7.527 |   -20328.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_212_/D
      540 |      41 |     420 |       46 |      0 |    36 |    -0.0% |   -7.439 |   -20308.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1379_/D
      550 |      41 |     427 |       46 |      0 |    39 |    -0.0% |   -7.377 |   -20259.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/ex_stage_i/_0934_/D
      560 |      41 |     433 |       48 |      0 |    41 |    -0.0% |   -7.165 |   -19172.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/id_stage_i/_2082_/D
      570 |      41 |     440 |       51 |      0 |    42 |    -0.0% |   -7.058 |   -18966.9 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_212_/D
      580 |      41 |     446 |       53 |      0 |    44 |    -0.0% |   -6.839 |   -18527.9 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/ex_stage_i/_1043_/D
      590 |      41 |     456 |       53 |      0 |    44 |    -0.0% |   -6.646 |   -17848.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      600 |      41 |     462 |       55 |      0 |    47 |    -0.0% |   -6.419 |   -17254.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_225_/D
      610 |      41 |     471 |       56 |      0 |    47 |    -0.0% |   -5.992 |   -15666.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_224_/D
      620 |      41 |     480 |       56 |      0 |    48 |    -0.0% |   -5.907 |   -15450.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      630 |      41 |     489 |       56 |      0 |    49 |    -0.0% |   -5.839 |   -15201.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      640 |      41 |     499 |       56 |      0 |    49 |    -0.0% |   -5.769 |   -14949.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      650 |      41 |     508 |       56 |      0 |    50 |    -0.0% |   -5.716 |   -14754.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      660 |      42 |     515 |       57 |      0 |    51 |    -0.0% |   -5.613 |   -14383.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      670 |      42 |     523 |       58 |      0 |    52 |    -0.0% |   -5.517 |   -14034.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      680 |      43 |     528 |       60 |      0 |    54 |    -0.0% |   -5.488 |   -13931.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      690 |      43 |     537 |       60 |      0 |    55 |    -0.0% |   -5.431 |   -13729.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      700 |      43 |     544 |       61 |      0 |    57 |    -0.0% |   -5.383 |   -13559.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      710 |      43 |     553 |       61 |      0 |    58 |    -0.0% |   -5.276 |   -13435.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_11888_/D
      720 |      43 |     563 |       61 |      0 |    58 |    -0.0% |   -5.148 |   -13009.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      730 |      43 |     570 |       63 |      0 |    59 |    -0.0% |   -5.044 |   -12638.9 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      740 |      45 |     577 |       64 |      0 |    59 |    -0.0% |   -4.948 |   -12294.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1232_/D
      750 |      45 |     585 |       64 |      0 |    61 |    -0.0% |   -4.753 |   -10825.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1360_/D
      760 |      45 |     593 |       65 |      0 |    62 |    -0.0% |   -4.418 |   -10301.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1350_/D
      770 |      46 |     601 |       65 |      0 |    63 |    -0.0% |   -4.254 |   -10202.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12405_/D
      780 |      46 |     610 |       65 |      0 |    64 |    -0.0% |   -4.219 |   -10133.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_223_/D
      790 |      46 |     620 |       65 |      0 |    64 |    -0.0% |   -4.135 |    -9876.9 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_11268_/D
      800 |      46 |     629 |       66 |      0 |    64 |    -0.0% |   -4.098 |    -9843.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12498_/D
      810 |      46 |     639 |       66 |      0 |    64 |    -0.0% |   -4.073 |    -9815.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/id_stage_i/_2082_/D
      820 |      46 |     649 |       66 |      0 |    64 |    -0.0% |   -4.029 |    -9749.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12748_/D
      830 |      46 |     659 |       66 |      0 |    64 |    -0.0% |   -3.990 |    -9723.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_231_/D
      840 |      46 |     668 |       66 |      0 |    65 |    -0.0% |   -3.962 |    -9681.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_214_/D
      850 |      46 |     677 |       66 |      0 |    66 |    -0.0% |   -3.925 |    -9659.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_210_/D
      860 |      47 |     685 |       68 |      0 |    66 |    -0.0% |   -3.906 |    -9592.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/ex_stage_i/_0929_/D
      870 |      47 |     695 |       68 |      0 |    66 |    -0.0% |   -3.876 |    -9495.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
      880 |      47 |     701 |       69 |      0 |    69 |    -0.0% |   -3.827 |    -9328.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
      890 |      48 |     707 |       72 |      0 |    70 |    -0.0% |   -3.786 |    -9190.2 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
      900 |      48 |     713 |       74 |      0 |    72 |    -0.0% |   -3.765 |    -9117.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
      910 |      48 |     721 |       75 |      0 |    73 |    -0.0% |   -3.724 |    -8929.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12168_/D
      920 |      49 |     730 |       75 |      0 |    73 |    -0.0% |   -3.695 |    -8870.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_214_/D
      930 |      49 |     737 |       76 |      0 |    75 |    -0.0% |   -3.672 |    -8722.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
      940 |      49 |     744 |       78 |      0 |    76 |    -0.0% |   -3.642 |    -8674.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_207_/D
      950 |      49 |     754 |       78 |      0 |    76 |    -0.0% |   -3.594 |    -8625.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_10982_/D
      960 |      49 |     764 |       78 |      0 |    76 |    -0.0% |   -3.566 |    -8553.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
      970 |      49 |     773 |       78 |      0 |    77 |    -0.0% |   -3.500 |    -8326.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
      980 |      49 |     780 |       79 |      0 |    79 |    -0.0% |   -3.416 |    -8102.9 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
      990 |      49 |     789 |       80 |      0 |    79 |    -0.0% |   -3.382 |    -7797.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1253_/D
     1000 |      50 |     798 |       80 |      0 |    79 |    -0.0% |   -3.334 |    -7732.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_11898_/D
     1010 |      51 |     802 |       82 |      0 |    82 |    -0.0% |   -3.233 |    -6709.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
     1020 |      51 |     811 |       83 |      0 |    82 |    -0.0% |   -3.141 |    -6638.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1362_/D
     1030 |      52 |     819 |       83 |      0 |    83 |    -0.0% |   -3.045 |    -6236.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_235_/D
     1040 |      52 |     829 |       83 |      0 |    83 |    -0.0% |   -2.981 |    -6172.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/_1344_/D
     1050 |      52 |     838 |       84 |      0 |    83 |    -0.0% |   -2.925 |    -6128.2 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1060 |      53 |     846 |       84 |      0 |    84 |    -0.0% |   -2.742 |    -5632.9 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_231_/D
     1070 |      53 |     856 |       84 |      0 |    84 |    -0.0% |   -2.683 |    -5627.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/FC/READER/_1446_/D
     1080 |      53 |     864 |       85 |      0 |    85 |    -0.0% |   -2.462 |    -4959.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1090 |      53 |     873 |       86 |      0 |    85 |    -0.0% |   -2.433 |    -4863.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1100 |      54 |     882 |       86 |      0 |    85 |    -0.0% |   -2.382 |    -4613.9 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1110 |      54 |     891 |       87 |      0 |    85 |    -0.0% |   -2.312 |    -4513.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1120 |      56 |     898 |       87 |      0 |    86 |    -0.0% |   -2.284 |    -4421.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1130 |      59 |     905 |       87 |      0 |    86 |    -0.0% |   -2.237 |    -4268.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1140 |      59 |     914 |       87 |      0 |    87 |    -0.0% |   -2.217 |    -4203.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1150 |      61 |     922 |       87 |      0 |    87 |    -0.0% |   -2.178 |    -4076.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1160 |      61 |     932 |       87 |      0 |    87 |    -0.0% |   -2.138 |    -3946.7 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1170 |      61 |     942 |       87 |      0 |    87 |    -0.0% |   -2.093 |    -3804.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1180 |      62 |     949 |       88 |      0 |    88 |    -0.0% |   -2.071 |    -3734.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1190 |      62 |     959 |       88 |      0 |    88 |    -0.0% |   -2.045 |    -3650.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1200 |      62 |     964 |       89 |      0 |    92 |    -0.0% |   -2.028 |    -3597.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1210 |      62 |     973 |       90 |      0 |    92 |    -0.0% |   -2.014 |    -3548.2 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1220 |      62 |     983 |       90 |      0 |    92 |    -0.0% |   -1.978 |    -3437.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1230 |      62 |     990 |       91 |      0 |    94 |    -0.0% |   -1.946 |    -3335.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1240 |      63 |     995 |       93 |      0 |    96 |    -0.0% |   -1.915 |    -3238.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1250 |      64 |    1003 |       94 |      0 |    96 |    -0.0% |   -1.816 |    -2849.2 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1260 |      65 |    1010 |       95 |      0 |    97 |    -0.0% |   -1.678 |    -2488.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1270 |      65 |    1020 |       95 |      0 |    97 |    -0.0% |   -1.659 |    -2432.6 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1280 |      65 |    1029 |       96 |      0 |    97 |    -0.0% |   -1.623 |    -2326.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1290 |      65 |    1034 |      100 |      0 |    98 |    -0.0% |   -1.640 |    -2375.3 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1300 |      66 |    1043 |      100 |      0 |    98 |    -0.0% |   -1.575 |    -2345.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/id_stage_i/_2059_/D
     1310 |      66 |    1051 |      101 |      0 |    99 |    -0.0% |   -1.488 |    -2120.4 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1320 |      66 |    1058 |      102 |      0 |   101 |    -0.0% |   -1.484 |    -2109.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1330 |      66 |    1065 |      104 |      0 |   102 |    -0.0% |   -1.490 |    -2124.1 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1340 |      66 |    1071 |      106 |      0 |   104 |    -0.0% |   -1.413 |    -1917.0 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/if_stage_i/prefetch_unit_i/alignment_buffer_i/_1361_/D
     1350 |      67 |    1078 |      106 |      0 |   106 |    -0.0% |   -1.386 |    -1863.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_12006_/D
     1360 |      67 |    1088 |      106 |      0 |   106 |    -0.0% |   -1.346 |    -1775.8 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/ex_stage_i/_0934_/D
     1370 |      68 |    1097 |      106 |      0 |   106 |    -0.0% |   -1.318 |    -1728.2 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/_223_/D
     1380 |      68 |    1106 |      106 |      0 |   107 |    -0.0% |   -1.291 |    -1619.9 |   3818 | i_greyhound_ihp/i_greyhound_soc/cv32e40x_core/id_stage_i/_1839_/D
     1390 |      68 |    1116 |      106 |      0 |   107 |    -0.0% |   -1.259 |    -1579.5 |   3818 | i_greyhound_ihp/i_greyhound_soc/i_EF_QSPI_XIP_CTRL_AHBL/CACHE/_11702_/D
Signal 11 received
Stack trace:
 0# 0x000055D3C8D2916F in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
 1# 0x00007FBC59441470 in /nix/store/cg9s562sa33k78m63njfn1rw47dp9z0i-glibc-2.40-66/lib/libc.so.6
 2# rsz::BaseMove::simulateExpr(sta::FuncExpr*, sta::UnorderedMap<sta::LibertyPort const*, std::vector<bool, std::allocator<bool> >, std::hash<sta::LibertyPort const*>, std::equal_to<sta::LibertyPort const*> >&, unsigned long) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
 3# rsz::BaseMove::isPortEqiv(sta::FuncExpr*, sta::LibertyCell const*, sta::LibertyPort const*, sta::LibertyPort const*) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
 4# rsz::SwapPinsMove::equivCellPins(sta::LibertyCell const*, sta::LibertyPort*, sta::Set<sta::LibertyPort*, std::less<sta::LibertyPort*> >&) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
 5# rsz::SwapPinsMove::doMove(sta::Path const*, int, float, sta::PathExpanded*, float) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
 6# rsz::RepairSetup::repairPath(sta::Path*, float, float) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
 7# rsz::RepairSetup::repairSetup(float, double, int, int, bool, std::vector<rsz::MoveType, std::allocator<rsz::MoveType> > const&, bool, bool, bool, bool, bool, bool, bool) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
 8# rsz::Resizer::repairSetup(double, double, int, int, bool, bool, std::vector<rsz::MoveType, std::allocator<rsz::MoveType> > const&, bool, bool, bool, bool, bool, bool, bool) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
 9# rsz::repair_setup(double, double, int, int, bool, bool, std::vector<rsz::MoveType, std::allocator<rsz::MoveType> >, bool, bool, bool, bool, bool, bool, bool) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
10# 0x000055D3C8EB839D in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
11# TclNRRunCallbacks in /nix/store/wpfdp7vzd7h7ahnmp4rvxfcklg4viknl-tcl-8.6.15/lib/libtcl.so
12# 0x00007FBC5EC9FA7C in /nix/store/wpfdp7vzd7h7ahnmp4rvxfcklg4viknl-tcl-8.6.15/lib/libtcl.so
13# Tcl_EvalEx in /nix/store/wpfdp7vzd7h7ahnmp4rvxfcklg4viknl-tcl-8.6.15/lib/libtcl.so
14# Tcl_Eval in /nix/store/wpfdp7vzd7h7ahnmp4rvxfcklg4viknl-tcl-8.6.15/lib/libtcl.so
15# ord::tclInit(Tcl_Interp*) in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
16# Tcl_MainEx in /nix/store/wpfdp7vzd7h7ahnmp4rvxfcklg4viknl-tcl-8.6.15/lib/libtcl.so
17# main in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
18# 0x00007FBC5942A47E in /nix/store/cg9s562sa33k78m63njfn1rw47dp9z0i-glibc-2.40-66/lib/libc.so.6
19# __libc_start_main in /nix/store/cg9s562sa33k78m63njfn1rw47dp9z0i-glibc-2.40-66/lib/libc.so.6
20# _start in /nix/store/3r01j6a1hs450cr82r3x4cj0hi67svki-openroad-2025-08-31/bin/openroad
Segmentation fault         openroad

[maliberty]

The PR was only merged just now - were you testing from my branch? If not you wouldn't see the change and should try again.

[mole99]

Argh, no I used head of OR back then. Sorry about that...

This is now head of OR including your patch:

Unfortunately, the hold violations are still there. This is using the RC values from the tech lef. Any ideas I can try?

The main issue as I see it is the left part of the clock tree: here the FrameData registers and the cache are mixed, even though their sinks have completely different locations. The FrameData registers are on the left of the eFPGA and the cache is underneath the eFPGA.

[mole99]

I inserted an always-on clock gate in the subtree of the FrameDate registers, and behold only a handful of hold violations!

However, all of these sinks should be at the same level (and they are prior to SPEF extraction), so it seems that the RC values actually underestimate the parasitics.

So either the RC values in the tech lef are wrong, or the conversion in OpenROAD to Res/Unit Distance and Cap/Unit Distance, or something somewhere else 🤔

[mole99]

@maliberty There's something really strange going on...
I'm currently trying to insert ECO buffers in the clock tree to delay the other subtrees and thus balance everything out.

I have the following chain of buffers:

sg13g2_buf_16 -> sg13g2_buf_16 -> sg13g2_buf_1 -> sg13g2_buf_1 -> sg13g2_buf_1 -> and so on...

(All of the cells are placed directly next to each other.)

From what I understand, the blue part in the clock tree represents the cell delay and the green part the delay introduced by routing?

Now common sense would say that the path from sg13g2_buf_16 -> sg13g2_buf_1 is much faster than the path from sg13g2_buf_1 -> sg13g2_buf_1, right? (As long as all of the cells are placed near each other, which they are.)

These are the delays that the clock tree shows me for the typical corner:

sg13g2_buf_16 -> sg13g2_buf_1: 0.039ns
sg13g2_buf_1 -> sg13g2_buf_1: 0.036ns

How is this possible? The first path should be much faster.

Perhaps someone with more experience can take a look at the liberty files, but to me they look alright:

• sg13g2_buf_16
• sg13g2_buf_1

Maybe I need to issue some commands after inserting the buffers using the odbpy API to recalculate the delays in the clock tree? But I thought OpenROAD is doing this on the fly when loading the LIBs and viewing the "Clock Tree Viewer".

I attached a reproducible so that you can take a look at the design.

issue_reproducible.zip

[mole99]

Can someone tell me how to calculate the "Cap/Unit Distance" so that I can check it against the values in OpenROAD?

[maliberty]

The value in LEF is just an average case. The actual capacitance will depend on the specific context of each shape. I don't know how IHP computed these values nor the ones in IHP_rcx_patterns.rules. It think you are better off asking them about this data. I don't currently see an OR bug but more of a PDK data question.

[rovinski]

Has someone run the RC calibration script for IHP? That could be a way to get better pre/post-extract correlation.

[mole99]

Probably not. Now I'm intrigued, where can I find this script?

[maliberty]

We did, see The-OpenROAD-Project/OpenROAD-flow-scripts@a3ea4d0

[mole99]

Thanks a lot! The calibrated RC constants haven't yet been integrated into LibreLane (for none of the PDKs, if I see correctly).

With these values, Greyhound now builds successfully with zero hold violatios 👏

[maliberty]

Please open issues for specific problems that need investigating and keep them focused to one problem. A running dialog of various problems is hard to manage.

[mole99]

Yeah, will do! When I started this discussion, it was about fixing those hold violations, but the topic drifted off in many directions.