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Hi! I need some help regarding CTS on my chip Greyhound using the IHP Open PDK. I had the same problem as I do now with my first tapeout of Greyhound: https://github.com/mole99/greyhound-ihp/tree/main
At the time, I disabled cell placement to the left of the eFPGA, since if I didn't, I got hold violations after SPEF extraction - the reason being that the clock tree was completely skewed. Before SPEF extraction, STA was fine. If I disable cell placement to the left of the eFPGA, that means I have to route 32*16 wires through that gap, as they need to connect to the left side of the eFPGA macro. If I enable cell placement, the FrameData registers can be placed next to their respective rows, which means 32 wires + a few select lines, allowing me to save area for another column of CLBs (Configurable Logic Blocks) increasing the capacity of the eFPGA. After the first tapeout, Donn pointed me to this issue: #6651 I'm currently working on the second revision of Greyhound with an updated version of LibreLane that contains this bug fix. Unfortunately, I still get hold violations after SPEF extraction when I enable cell placement to the left of the eFPGA. Clock tree before SPEF extraction:
Clock tree after SPEF extraction:
(By the way, I'm using a hierarchical netlist, but flattened the outcome is the same.) The command (or variants of it) that I use to run CTS is: I also tried disabling I also tried to manually specify
Also, the placement of the clock buffers is odd. The clock buffers appear to be mostly placed on a central horizontal spine in the middle of the bottom core area.
I traced this part of the clock tree and it goes all the way up to the center left of the eFPGA before going all the way down to the bottom left corner where the IO pad for the clock is located. So it seems that CTS creates unnecessary long paths for the sinks, but it doesn't seem to notice, since before SPEF extraction STA is fine. Are the RC constants correct? OpenROAD uses the RC constants from the tech lef, so I verified the following. Metal1 from tech lef: Calculation for the resistance: 0.135 / 0.16 = 0.84375 For the capacitance I'm not sure how to calculate the "Cap/Unit Distance", maybe someone can help me there? Cont from techlef: The resistances matches the values in OpenROAD: I assume the other layers match as well... But maybe the units are not matching? Should Maybe I can artificially increase the routing resistance in order to get the CTS to notice the parasitics? Another possibility is that the SPEF values are incorrect. But I have no reason to believe that, since they uncovered real issues in my design i.e. the clock path for a sink is going all across the chip. Is this a limitation due to the strange shape of my core area? Is something else going wrong? I use LibreLane, so reproducing might be a little more difficult/unusual for you. But I can easily provide an ODB from any step of the flow if that helps. |
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Replies: 4 comments 28 replies
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Does your design have clock gating? What version of OR are you using as there have been a lot of recent improvements? What layers are you assuming for clocks (eg set_wire_rc) and do they match the final layers well? Are you using the values from LEF or from set_layer_rc? |
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You should try head of OR |
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Can someone tell me how to calculate the "Cap/Unit Distance" so that I can check it against the values in OpenROAD? |
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Please open issues for specific problems that need investigating and keep them focused to one problem. A running dialog of various problems is hard to manage. |
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We did, see The-OpenROAD-Project/OpenROAD-flow-scripts@a3ea4d0