Debugging the slew rate violation and issues in openROAD

[Anilkumargundu]

Hello OpenROAD Community,

I'm relatively new to using OpenROAD for my RTL-to-GDSII flow and have been working through the floorplanning, CTS, and timing closure stages. I've hit a roadblock with some persistent slew violations that I haven't been able to resolve.

My Issue:
Despite trying several approaches, I continue to encounter slew violations that are preventing me from progressing.

I'm now at a point where: Some commands I try seem to be unsupported or have limitations I don't understand. My usual methods for fixing slew violations aren't working in this context. Could anyone with more experience in the OpenROAD flow please advise? Are there specific commands or scripts I should be focusing on? Has anyone encountered similar issues and found a solution?

Is there any specific commands where I can fix these strengths directly?

Thanks

[maliberty]

There were some very recent fixes to slew fixing so you might retry with the head of master. Beyond that it would be helpful to have a test case if you can share one.

[Anilkumargundu]

Hi,

Thank you for the prompt response. I have managed to fix those violations after going through the documents. Thanks a lot.

I have one more fundamental question.
After performing all steps in openROAD for the RTL code I have written (including synthesis, floorplanning, PDN creation, CTS, STA, and so on), I am unable to find VDD and VSS pins in my final GDS file. Generally, we never talk about VDD and VSS in RTL code.

I understand that openROAD might take care of connecting all VDD and VSS internally, but how can we expose these VDD and VSS connections as external pins?

Thanks

[Anilkumargundu]

I tried placing the VDD/VSS pins in the RTL and then tried to place the related pins in the synthesized RTL after yosys. Then the VDD/VSS pins are effectively created, however they are not connected to anything.

How can I fix this issue

[maliberty]

I believe you want the -pins option to define_pdn_grid

[Anilkumargundu]

I have checked them, everything seems to be correct. But still not able to connect to VDD and VSS pins

I have cross-checked it , the power pins and VSS are defined, the pin is metal 2 which is in green color not connected to the grid (which is VPWR)

OBSERVATION :
When I try to get the pins of the standard cells, the pins are being assigned random names as below. Maybe that is why I am not able to map the power and ground pins

get_lib_pins sky130_fd_sc_hd__edfxtp_1/
_406d4b2e4e5f0000_p_LibertyPort _606f4b2e4e5f0000_p_LibertyPort _50754b2e4e5f0000_p_LibertyPort _d07f4b2e4e5f0000_p_LibertyPort _40904b2e4e5f0000_p_LibertyPort _c0bc4b2e4e5f0000_p_LibertyPort*

It is supposed to have these pins :

Some more information :

I have seen in the .lib files each std cell has VPWR and VGND pins.

After synthesis I am searching for the nets VPWR and VGND but they are not found. But when I see the layout the net_names are still there as VPWR and VGND

report_net -connections VGND
[WARNING STA-0235] report_net -connections is deprecated.
[ERROR STA-0232] net VGND not found.

Anyone faced this kind of problem?