gated clock tree without constraints vs. with constraints

[aviadb]

Hi,
I am testing the dynamic power consumption of my design.
I deliberately inserted clock gates cells (sky130 sky130_fd_sc_hd__dlclkp_2) to drive logic branches.
While doing so I have seen that the clock tree viewer behaves differently if there are defined constraints for the
generated clock_gated clocks or not.

For example, without defining any generated clocks, the clock tree viewer shows:

Looking at this preview, I see that there is a new branch created out of the main "clk" branch that drives the majority of seq logic.

Next, I defined two generated clocks and rerun the orfs, the result is:

Seeing three different clock trees which is fine, but without seeing a general branches view, where I can see the split from the main "clk" to the gated clock like before.

Is there an option to enable such an extra view in the clock tree viewer?

It is very handy for me to better understand the clock tree schematics more comprehensively, especially, what clock derive a new clock tree.

[maliberty]

Clock gating cells general do not require a generated clock statement in SDC. What are you trying to model?

[aviadb]

Hi @maliberty ,
Thank you for your fast reply.

I am trying to model the impacts on clock gating on the power consumption.

1. Full run without any clock gates (in design)
2. Full run with clock gates but without generated clocks constraints in sdc
3. full run with clock gates and generated clocks constraints

Each flow variant creates a set of netlist, spef and sdc files that I insert into OpenSTA with accompanying VCD to simulate the dynamic power.

The results are different for each run.

The sdc constaints I use:
create_clock -name $clk_name -period $clk_period $clk_port
create_generated_clock -name gclk_50M
-source $clk_port
-divide_by 2
[get_pins clkgate_i/gck_i/GCLK]

create_generated_clock -name gclk_2k
-source [get_pins clkgate_i/gck_i/GCLK]
-divide_by 25000
[get_pins io_ctrl_i/clkgate_2khz_i/gck_i/GCLK]

First step for me to spot a possible power optimization possibilities is to review the clock tree in the clock tree viewer.
If I observe a big chunk of seq logic running on a non optimal clock freq, I try to insert a clock gater there.
I am looking for the option to view the entire clock tree + branching from the main clock and derived clocks similarly to what the clock tree viewer present when not including the generated clocks constraints.