diff --git a/src/mpl/src/MplObserver.h b/src/mpl/src/MplObserver.h
index 994a5e2f357..9e4eedb7e0e 100644
--- a/src/mpl/src/MplObserver.h
+++ b/src/mpl/src/MplObserver.h
@@ -54,6 +54,18 @@ class MplObserver
   virtual void setOutline(const odb::Rect& outline) {}
   virtual void setGuides(const std::map<int, Rect>& guides) {}
   virtual void setFences(const std::map<int, Rect>& fences) {}
+  virtual void setIOConstraintsMap(
+      const ClusterToBoundaryRegionMap& io_cluster_to_constraint)
+  {
+  }
+  virtual void setBlockedRegionsForPins(
+      const std::vector<odb::Rect>& blocked_regions_for_pins)
+  {
+  }
+  virtual void setAvailableRegionsForUnconstrainedPins(
+      const BoundaryRegionList& regions)
+  {
+  }
 
   virtual void setAreaPenalty(const PenaltyData& penalty) {}
   virtual void setBoundaryPenalty(const PenaltyData& penalty) {}
diff --git a/src/mpl/src/SACoreHardMacro.cpp b/src/mpl/src/SACoreHardMacro.cpp
index a3166a8a07b..693c8299671 100644
--- a/src/mpl/src/SACoreHardMacro.cpp
+++ b/src/mpl/src/SACoreHardMacro.cpp
@@ -31,7 +31,8 @@ SACoreHardMacro::SACoreHardMacro(PhysicalHierarchy* tree,
                                  int num_perturb_per_step,
                                  unsigned seed,
                                  MplObserver* graphics,
-                                 utl::Logger* logger)
+                                 utl::Logger* logger,
+                                 odb::dbBlock* block)
     : SimulatedAnnealingCore<HardMacro>(tree,
                                         outline,
                                         macros,
@@ -45,7 +46,8 @@ SACoreHardMacro::SACoreHardMacro(PhysicalHierarchy* tree,
                                         num_perturb_per_step,
                                         seed,
                                         graphics,
-                                        logger)
+                                        logger,
+                                        block)
 {
   flip_prob_ = flip_prob;
 }
diff --git a/src/mpl/src/SACoreHardMacro.h b/src/mpl/src/SACoreHardMacro.h
index 632dae2d5c7..df34e1c4183 100644
--- a/src/mpl/src/SACoreHardMacro.h
+++ b/src/mpl/src/SACoreHardMacro.h
@@ -34,7 +34,8 @@ class SACoreHardMacro : public SimulatedAnnealingCore<HardMacro>
                   int num_perturb_per_step,
                   unsigned seed,
                   MplObserver* graphics,
-                  utl::Logger* logger);
+                  utl::Logger* logger,
+                  odb::dbBlock* block);
 
   void run() override;
 
diff --git a/src/mpl/src/SACoreSoftMacro.cpp b/src/mpl/src/SACoreSoftMacro.cpp
index d174e607525..9a99d86ff20 100644
--- a/src/mpl/src/SACoreSoftMacro.cpp
+++ b/src/mpl/src/SACoreSoftMacro.cpp
@@ -42,7 +42,8 @@ SACoreSoftMacro::SACoreSoftMacro(PhysicalHierarchy* tree,
                                  int num_perturb_per_step,
                                  unsigned seed,
                                  MplObserver* graphics,
-                                 utl::Logger* logger)
+                                 utl::Logger* logger,
+                                 odb::dbBlock* block)
     : SimulatedAnnealingCore<SoftMacro>(tree,
                                         outline,
                                         macros,
@@ -56,7 +57,8 @@ SACoreSoftMacro::SACoreSoftMacro(PhysicalHierarchy* tree,
                                         num_perturb_per_step,
                                         seed,
                                         graphics,
-                                        logger),
+                                        logger,
+                                        block),
       root_(tree->root.get())
 {
   boundary_weight_ = boundary_weight;
diff --git a/src/mpl/src/SACoreSoftMacro.h b/src/mpl/src/SACoreSoftMacro.h
index b8d8c4f26fa..8e4fef39701 100644
--- a/src/mpl/src/SACoreSoftMacro.h
+++ b/src/mpl/src/SACoreSoftMacro.h
@@ -42,7 +42,8 @@ class SACoreSoftMacro : public SimulatedAnnealingCore<SoftMacro>
                   int num_perturb_per_step,
                   unsigned seed,
                   MplObserver* graphics,
-                  utl::Logger* logger);
+                  utl::Logger* logger,
+                  odb::dbBlock* block);
 
   void run() override;
 
diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp
index 9b2d63e4592..dd63d37b8be 100644
--- a/src/mpl/src/SimulatedAnnealingCore.cpp
+++ b/src/mpl/src/SimulatedAnnealingCore.cpp
@@ -36,10 +36,9 @@ SimulatedAnnealingCore<T>::SimulatedAnnealingCore(PhysicalHierarchy* tree,
                                                   int num_perturb_per_step,
                                                   unsigned seed,
                                                   MplObserver* graphics,
-                                                  utl::Logger* logger)
-    : outline_(outline),
-      blocked_boundaries_(tree->blocked_boundaries),
-      graphics_(graphics)
+                                                  utl::Logger* logger,
+                                                  odb::dbBlock* block)
+    : outline_(outline), graphics_(graphics), block_(block)
 {
   core_weights_ = weights;
 
@@ -62,7 +61,10 @@ SimulatedAnnealingCore<T>::SimulatedAnnealingCore(PhysicalHierarchy* tree,
   macros_ = macros;
 
   setDieArea(tree->die_area);
-  setBlockedBoundariesForIOs();
+  setAvailableRegionsForUnconstrainedPins(
+      tree->available_regions_for_unconstrained_pins);
+
+  io_cluster_to_constraint_ = tree->io_cluster_to_constraint;
 }
 
 template <class T>
@@ -74,22 +76,14 @@ void SimulatedAnnealingCore<T>::setDieArea(const Rect& die_area)
 }
 
 template <class T>
-void SimulatedAnnealingCore<T>::setBlockedBoundariesForIOs()
+void SimulatedAnnealingCore<T>::setAvailableRegionsForUnconstrainedPins(
+    const BoundaryRegionList& regions)
 {
-  if (blocked_boundaries_.find(Boundary::L) != blocked_boundaries_.end()) {
-    left_is_blocked_ = true;
-  }
-
-  if (blocked_boundaries_.find(Boundary::R) != blocked_boundaries_.end()) {
-    right_is_blocked_ = true;
-  }
+  available_regions_for_unconstrained_pins_ = regions;
 
-  if (blocked_boundaries_.find(Boundary::B) != blocked_boundaries_.end()) {
-    bottom_is_blocked_ = true;
-  }
-
-  if (blocked_boundaries_.find(Boundary::T) != blocked_boundaries_.end()) {
-    top_is_blocked_ = true;
+  for (BoundaryRegion& region : available_regions_for_unconstrained_pins_) {
+    region.line.addX(-block_->micronsToDbu(outline_.xMin()));
+    region.line.addY(-block_->micronsToDbu(outline_.yMin()));
   }
 }
 
@@ -284,7 +278,7 @@ void SimulatedAnnealingCore<T>::calWirelength()
     T& target = macros_[net.terminals.second];
 
     if (target.isClusterOfUnplacedIOPins()) {
-      addBoundaryDistToWirelength(source, target, net.weight);
+      computeWLForClusterOfUnplacedIOPins(source, target, net.weight);
       continue;
     }
 
@@ -308,7 +302,7 @@ void SimulatedAnnealingCore<T>::calWirelength()
 }
 
 template <class T>
-void SimulatedAnnealingCore<T>::addBoundaryDistToWirelength(
+void SimulatedAnnealingCore<T>::computeWLForClusterOfUnplacedIOPins(
     const T& macro,
     const T& unplaced_ios,
     const float net_weight)
@@ -321,46 +315,27 @@ void SimulatedAnnealingCore<T>::addBoundaryDistToWirelength(
     return;
   }
 
-  const float x1 = macro.getPinX();
-  const float y1 = macro.getPinY();
-
-  Boundary constraint_boundary
-      = unplaced_ios.getCluster()->getConstraintBoundary();
-
-  if (constraint_boundary == NONE) {
-    float dist_to_left = max_dist;
-    if (!left_is_blocked_) {
-      dist_to_left = std::abs(x1 - die_area_.xMin());
+  const odb::Point macro_location(block_->micronsToDbu(macro.getPinX()),
+                                  block_->micronsToDbu(macro.getPinY()));
+  double smallest_distance;
+  if (unplaced_ios.getCluster()->isClusterOfUnconstrainedIOPins()) {
+    if (available_regions_for_unconstrained_pins_.empty()) {
+      logger_->critical(
+          utl::MPL,
+          47,
+          "There's no available region for the unconstrained pins!");
     }
 
-    float dist_to_right = max_dist;
-    if (!right_is_blocked_) {
-      dist_to_right = std::abs(x1 - die_area_.xMax());
-    }
-
-    float dist_to_bottom = max_dist;
-    if (!bottom_is_blocked_) {
-      dist_to_right = std::abs(y1 - die_area_.yMin());
-    }
-
-    float dist_to_top = max_dist;
-    if (!top_is_blocked_) {
-      dist_to_top = std::abs(y1 - die_area_.yMax());
-    }
-
-    wirelength_
-        += net_weight
-           * std::min(
-               {dist_to_left, dist_to_right, dist_to_bottom, dist_to_top});
-  } else if (constraint_boundary == Boundary::L
-             || constraint_boundary == Boundary::R) {
-    const float x2 = unplaced_ios.getPinX();
-    wirelength_ += net_weight * std::abs(x2 - x1);
-  } else if (constraint_boundary == Boundary::T
-             || constraint_boundary == Boundary::B) {
-    const float y2 = unplaced_ios.getPinY();
-    wirelength_ += net_weight * std::abs(y2 - y1);
+    smallest_distance = computeDistToNearestRegion(
+        macro_location, available_regions_for_unconstrained_pins_, nullptr);
+  } else {
+    Cluster* cluster = unplaced_ios.getCluster();
+    const BoundaryRegion& constraint = io_cluster_to_constraint_.at(cluster);
+    smallest_distance
+        = computeDistToNearestRegion(macro_location, {constraint}, nullptr);
   }
+
+  wirelength_ += net_weight * block_->dbuToMicrons(smallest_distance);
 }
 
 // We consider the macro outside the outline based on the location of
diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h
index d823f4cdadf..1f14018cb81 100644
--- a/src/mpl/src/SimulatedAnnealingCore.h
+++ b/src/mpl/src/SimulatedAnnealingCore.h
@@ -52,7 +52,8 @@ class SimulatedAnnealingCore
                          int num_perturb_per_step,
                          unsigned seed,
                          MplObserver* graphics,
-                         utl::Logger* logger);
+                         utl::Logger* logger,
+                         odb::dbBlock* block);
 
   virtual ~SimulatedAnnealingCore() = default;
 
@@ -97,9 +98,10 @@ class SimulatedAnnealingCore
 
   void fastSA();
 
+  void setAvailableRegionsForUnconstrainedPins(
+      const BoundaryRegionList& regions);
   void initSequencePair();
   void setDieArea(const Rect& die_area);
-  void setBlockedBoundariesForIOs();
   void updateBestValidResult();
   void useBestValidResult();
 
@@ -107,9 +109,9 @@ class SimulatedAnnealingCore
   virtual void calPenalty() = 0;
   void calOutlinePenalty();
   void calWirelength();
-  void addBoundaryDistToWirelength(const T& macro,
-                                   const T& unplaced_ios,
-                                   float net_weight);
+  void computeWLForClusterOfUnplacedIOPins(const T& macro,
+                                           const T& unplaced_ios,
+                                           float net_weight);
   bool isOutsideTheOutline(const T& macro) const;
   void calGuidancePenalty();
   void calFencePenalty();
@@ -136,8 +138,8 @@ class SimulatedAnnealingCore
   Rect outline_;
   Rect die_area_;  // Offset to the current outline.
 
-  // Boundaries blocked for IO pins
-  std::set<Boundary> blocked_boundaries_;
+  BoundaryRegionList available_regions_for_unconstrained_pins_;
+  ClusterToBoundaryRegionMap io_cluster_to_constraint_;
 
   // Number of macros that will actually be part of the sequence pair
   int macros_to_place_ = 0;
@@ -203,6 +205,7 @@ class SimulatedAnnealingCore
 
   utl::Logger* logger_ = nullptr;
   MplObserver* graphics_ = nullptr;
+  odb::dbBlock* block_;
 
   Result best_valid_result_;
 
@@ -213,13 +216,6 @@ class SimulatedAnnealingCore
   static constexpr float acc_tolerance_ = 0.001;
 
   bool has_initial_sequence_pair_ = false;
-
-  // Blocked boundaries data is kept in bools to avoid overhead
-  // during SA steps.
-  bool left_is_blocked_ = false;
-  bool right_is_blocked_ = false;
-  bool bottom_is_blocked_ = false;
-  bool top_is_blocked_ = false;
 };
 
 // SACore wrapper function
diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp
index 640dd5bb43e..ba819fe3bc0 100644
--- a/src/mpl/src/clusterEngine.cpp
+++ b/src/mpl/src/clusterEngine.cpp
@@ -12,6 +12,7 @@
 #include <utility>
 #include <vector>
 
+#include "MplObserver.h"
 #include "db_sta/dbNetwork.hh"
 #include "par/PartitionMgr.h"
 #include "sta/Liberty.hh"
@@ -22,11 +23,13 @@ using utl::MPL;
 ClusteringEngine::ClusteringEngine(odb::dbBlock* block,
                                    sta::dbNetwork* network,
                                    utl::Logger* logger,
-                                   par::PartitionMgr* triton_part)
+                                   par::PartitionMgr* triton_part,
+                                   MplObserver* graphics)
     : block_(block),
       network_(network),
       logger_(logger),
-      triton_part_(triton_part)
+      triton_part_(triton_part),
+      graphics_(graphics)
 {
 }
 
@@ -44,9 +47,7 @@ void ClusteringEngine::run()
 
   mapIOPinsAndPads();
   createDataFlow();
-
   createIOClusters();
-  classifyBoundariesStateForIOs();
 
   if (design_metrics_->getNumStdCell() == 0) {
     logger_->warn(MPL, 25, "Design has no standard cells!");
@@ -349,10 +350,11 @@ void ClusteringEngine::setBaseThresholds()
 // 1. A Group of Unplaced Pins;
 // 2. An IO Pad.
 //
-// For the former, we group IO pins with the same constraints based on:
-// - If an IO pin has a constraint region in a certain boundary,
-//   it is constrained to that entire boundary;
-// - If an IO pin has no constraints, it is constrained to all boundaries.
+// For 1:
+// We group IO pins that are constrained to the same region - the cluster's
+// shape is the constraint region. If a pin has no constraints, we consider
+// it constrained to all edges of the die area - for this case, the cluster's
+// shape is the die area.
 void ClusteringEngine::createIOClusters()
 {
   if (!tree_->maps.pad_to_bterm.empty()) {
@@ -360,151 +362,74 @@ void ClusteringEngine::createIOClusters()
     return;
   }
 
-  // Boundary with constrained IOs -> cluster
-  std::map<Boundary, Cluster*> boundary_to_cluster;
-  const odb::Rect die = block_->getDieArea();
-
-  for (odb::dbBTerm* bterm : block_->getBTerms()) {
-    Boundary constraint_boundary = NONE;
-
-    auto constraint_region = bterm->getConstraintRegion();
-    if (constraint_region) {
-      constraint_boundary
-          = getConstraintBoundary(die, constraint_region.value());
-    }
-
-    const auto itr = boundary_to_cluster.find(constraint_boundary);
-    if (itr != boundary_to_cluster.end()) {
-      Cluster* io_cluster = itr->second;
-      tree_->maps.bterm_to_cluster_id[bterm] = io_cluster->getId();
-    } else {
-      createIOCluster(die, constraint_boundary, boundary_to_cluster, bterm);
-    }
-  }
-
-  if (tree_->maps.id_to_cluster.size() == 1) {
+  if (block_->getBTerms().empty()) {
     logger_->warn(MPL, 26, "Design has no IO pins!");
     tree_->has_io_clusters = false;
   }
-}
 
-Boundary ClusteringEngine::getConstraintBoundary(
-    const odb::Rect& die,
-    const odb::Rect& constraint_region)
-{
-  Boundary constraint_boundary = NONE;
-  if (constraint_region.xMin() == constraint_region.xMax()) {
-    if (constraint_region.xMin() == die.xMin()) {
-      constraint_boundary = L;
-    } else {
-      constraint_boundary = R;
-    }
-  } else {
-    if (constraint_region.yMin() == die.yMin()) {
-      constraint_boundary = B;
+  for (odb::dbBTerm* bterm : block_->getBTerms()) {
+    Cluster* same_constraint_cluster = findIOClusterWithSameConstraint(bterm);
+    if (same_constraint_cluster) {
+      tree_->maps.bterm_to_cluster_id[bterm] = same_constraint_cluster->getId();
     } else {
-      constraint_boundary = T;
+      createClusterOfUnplacedIOs(bterm);
     }
   }
-  return constraint_boundary;
-}
 
-void ClusteringEngine::createIOCluster(
-    const odb::Rect& die,
-    const Boundary constraint_boundary,
-    std::map<Boundary, Cluster*>& boundary_to_cluster,
-    odb::dbBTerm* bterm)
-{
-  auto cluster
-      = std::make_unique<Cluster>(id_, toString(constraint_boundary), logger_);
-  tree_->maps.bterm_to_cluster_id[bterm] = id_;
-  tree_->maps.id_to_cluster[id_++] = cluster.get();
-
-  boundary_to_cluster[constraint_boundary] = cluster.get();
-
-  int x = die.xMin(), y = die.yMin();
-  int width = die.dx(), height = die.dy();
-
-  if (constraint_boundary != NONE) {
-    setIOClusterDimensions(die, constraint_boundary, x, y, width, height);
+  if (graphics_) {
+    graphics_->setIOConstraintsMap(tree_->io_cluster_to_constraint);
   }
-
-  cluster->setAsClusterOfUnplacedIOPins(
-      std::pair<float, float>(block_->dbuToMicrons(x), block_->dbuToMicrons(y)),
-      block_->dbuToMicrons(width),
-      block_->dbuToMicrons(height),
-      constraint_boundary);
-  tree_->root->addChild(std::move(cluster));
 }
 
-void ClusteringEngine::classifyBoundariesStateForIOs()
+Cluster* ClusteringEngine::findIOClusterWithSameConstraint(
+    odb::dbBTerm* bterm) const
 {
-  const float blocked_boundary_threshold = 0.7;
-  std::map<Boundary, float> blockage_extension_map
-      = computeBlockageExtensionMap();
-
-  for (const auto [boundary, blockage_extension] : blockage_extension_map) {
-    if (blockage_extension >= blocked_boundary_threshold) {
-      tree_->blocked_boundaries.insert(boundary);
-    } else {
-      tree_->unblocked_boundaries.insert(boundary);
-    }
+  const auto& bterm_constraint = bterm->getConstraintRegion();
+  if (!bterm_constraint) {
+    return cluster_of_unconstrained_io_pins_;
   }
-}
-
-// Computes how much blocked each boundary is for IOs base on PPL exclude
-// contraints.
-std::map<Boundary, float> ClusteringEngine::computeBlockageExtensionMap()
-{
-  std::map<Boundary, float> blockage_extension_map;
 
-  blockage_extension_map[L] = 0.0;
-  blockage_extension_map[R] = 0.0;
-  blockage_extension_map[B] = 0.0;
-  blockage_extension_map[T] = 0.0;
-
-  const odb::Rect die = block_->getDieArea();
-  for (const odb::Rect& blocked_region : block_->getBlockedRegionsForPins()) {
-    Boundary blocked_region_boundary
-        = getConstraintBoundary(die, blocked_region);
-    float blockage_extension = 0.0;
-
-    if (blocked_region_boundary == L || blocked_region_boundary == R) {
-      blockage_extension = blocked_region.dy() / static_cast<float>(die.dy());
-    } else if (blocked_region_boundary == B || blocked_region_boundary == T) {
-      blockage_extension = blocked_region.dx() / static_cast<float>(die.dx());
+  for (const auto& [cluster, constraint_region] :
+       tree_->io_cluster_to_constraint) {
+    if (bterm_constraint == lineToRect(constraint_region.line)) {
+      return cluster;
     }
-
-    blockage_extension_map[blocked_region_boundary] += blockage_extension;
   }
 
-  return blockage_extension_map;
+  return nullptr;
 }
 
-void ClusteringEngine::setIOClusterDimensions(const odb::Rect& die,
-                                              const Boundary boundary,
-                                              int& x,
-                                              int& y,
-                                              int& width,
-                                              int& height)
+void ClusteringEngine::createClusterOfUnplacedIOs(odb::dbBTerm* bterm)
 {
-  if (boundary == L) {
-    x = die.xMin();
-    y = die.yMin();
-    width = 0;
-  } else if (boundary == T) {
-    x = die.xMin();
-    y = die.yMax();
-    height = 0;
-  } else if (boundary == R) {
-    x = die.xMax();
-    y = die.yMin();
-    width = 0;
-  } else {  // Bottom
-    x = die.xMin();
-    y = die.yMin();
-    height = 0;
+  auto cluster
+      = std::make_unique<Cluster>(id_, "ios_" + std::to_string(id_), logger_);
+  cluster->setParent(tree_->root.get());
+
+  bool is_cluster_of_unconstrained_io_pins = false;
+  odb::Rect constraint_shape;
+  const auto& bterm_constraint = bterm->getConstraintRegion();
+  if (bterm_constraint) {
+    constraint_shape = *bterm_constraint;
+    BoundaryRegion constraint_region(
+        rectToLine(block_, constraint_shape, logger_),
+        getBoundary(block_, constraint_shape));
+    tree_->io_cluster_to_constraint[cluster.get()] = constraint_region;
+  } else {
+    constraint_shape = block_->getDieArea();
+    is_cluster_of_unconstrained_io_pins = true;
+    cluster_of_unconstrained_io_pins_ = cluster.get();
   }
+
+  cluster->setAsClusterOfUnplacedIOPins(
+      {block_->dbuToMicrons(constraint_shape.xMin()),
+       block_->dbuToMicrons(constraint_shape.yMin())},
+      block_->dbuToMicrons(constraint_shape.dx()),
+      block_->dbuToMicrons(constraint_shape.dy()),
+      is_cluster_of_unconstrained_io_pins);
+
+  tree_->maps.bterm_to_cluster_id[bterm] = id_;
+  tree_->maps.id_to_cluster[id_++] = cluster.get();
+  tree_->root->addChild(std::move(cluster));
 }
 
 void ClusteringEngine::mapIOPinsAndPads()
@@ -2210,14 +2135,7 @@ void ClusteringEngine::printPhysicalHierarchyTree(Cluster* parent, int level)
                       parent->getClusterTypeString());
 
   if (parent->isClusterOfUnplacedIOPins()) {
-    int number_of_pins = 0;
-    for (const auto [pin, cluster_id] : tree_->maps.bterm_to_cluster_id) {
-      if (cluster_id == parent->getId()) {
-        ++number_of_pins;
-      }
-    }
-
-    line += fmt::format(" Pins: {}", number_of_pins);
+    line += fmt::format(" Pins: {}", getNumberOfIOs(parent));
   } else if (!parent->isIOPadCluster()) {
     line += fmt::format(" {}, StdCells: {} ({} μ²), Macros: {} ({} μ²)",
                         parent->getIsLeafString(),
@@ -2275,4 +2193,15 @@ void ClusteringEngine::clearTempMacroClusterMapping(
   }
 }
 
+int ClusteringEngine::getNumberOfIOs(Cluster* target) const
+{
+  int number_of_ios = 0;
+  for (const auto& [pin, io_cluster_id] : tree_->maps.bterm_to_cluster_id) {
+    if (io_cluster_id == target->getId()) {
+      ++number_of_ios;
+    }
+  }
+  return number_of_ios;
+}
+
 }  // namespace mpl
diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h
index 698d21034b9..d7d58f11383 100644
--- a/src/mpl/src/clusterEngine.h
+++ b/src/mpl/src/clusterEngine.h
@@ -12,6 +12,7 @@
 #include <vector>
 
 #include "object.h"
+#include "util.h"
 
 namespace par {
 class PartitionMgr;
@@ -26,6 +27,7 @@ class dbNetwork;
 }
 
 namespace mpl {
+class MplObserver;
 
 using InstToHardMap = std::map<odb::dbInst*, std::unique_ptr<HardMacro>>;
 using ModuleToMetricsMap = std::map<odb::dbModule*, std::unique_ptr<Metrics>>;
@@ -88,14 +90,18 @@ struct PhysicalHierarchy
   std::unique_ptr<Cluster> root;
   PhysicalHierarchyMaps maps;
 
-  // This is set according to the ppl -exclude constraints
-  std::set<Boundary> blocked_boundaries;
-  std::set<Boundary> unblocked_boundaries;  // For orientation improvement.
+  BoundaryRegionList available_regions_for_unconstrained_pins;
+  ClusterToBoundaryRegionMap io_cluster_to_constraint;
 
   float halo_width{0.0f};
   float halo_height{0.0f};
   float macro_with_halo_area{0.0f};
+
+  // The constraint set by the user.
   Rect global_fence;
+
+  // The actual area used by MPL - computed using the dimensions
+  // of the core versus the global fence set by the user.
   Rect floorplan_shape;
   Rect die_area;
 
@@ -127,7 +133,8 @@ class ClusteringEngine
   ClusteringEngine(odb::dbBlock* block,
                    sta::dbNetwork* network,
                    utl::Logger* logger,
-                   par::PartitionMgr* triton_part);
+                   par::PartitionMgr* triton_part,
+                   MplObserver* graphics);
 
   void run();
 
@@ -149,6 +156,8 @@ class ClusteringEngine
                                std::set<odb::dbMaster*>& masters);
   void clearTempMacroClusterMapping(const UniqueClusterVector& macro_clusters);
 
+  int getNumberOfIOs(Cluster* target) const;
+
   static bool isIgnoredInst(odb::dbInst* inst);
 
  private:
@@ -166,22 +175,10 @@ class ClusteringEngine
   void createRoot();
   void setBaseThresholds();
   void createIOClusters();
+  Cluster* findIOClusterWithSameConstraint(odb::dbBTerm* bterm) const;
+  void createClusterOfUnplacedIOs(odb::dbBTerm* bterm);
   void createIOPadClusters();
   void createIOPadCluster(odb::dbInst* pad, odb::dbBTerm* bterm);
-  void classifyBoundariesStateForIOs();
-  std::map<Boundary, float> computeBlockageExtensionMap();
-  Boundary getConstraintBoundary(const odb::Rect& die,
-                                 const odb::Rect& constraint_region);
-  void createIOCluster(const odb::Rect& die,
-                       Boundary constraint_boundary,
-                       std::map<Boundary, Cluster*>& boundary_to_cluster,
-                       odb::dbBTerm* bterm);
-  void setIOClusterDimensions(const odb::Rect& die,
-                              Boundary boundary,
-                              int& x,
-                              int& y,
-                              int& width,
-                              int& height);
   void mapIOPinsAndPads();
   void treatEachMacroAsSingleCluster();
   void incorporateNewCluster(std::unique_ptr<Cluster> cluster, Cluster* parent);
@@ -262,10 +259,14 @@ class ClusteringEngine
   sta::dbNetwork* network_;
   utl::Logger* logger_;
   par::PartitionMgr* triton_part_;
+  MplObserver* graphics_;
 
   Metrics* design_metrics_{nullptr};
   PhysicalHierarchy* tree_{nullptr};
 
+  // Keep this pointer to avoid searching for it when creating IO clusters.
+  Cluster* cluster_of_unconstrained_io_pins_{nullptr};
+
   int level_{0};  // Current level
   int id_{0};     // Current "highest" id
 
diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp
index 9b4f15bafcf..37b0e256863 100644
--- a/src/mpl/src/graphics.cpp
+++ b/src/mpl/src/graphics.cpp
@@ -286,43 +286,16 @@ void Graphics::setMaxLevel(const int max_level)
 void Graphics::finishedClustering(PhysicalHierarchy* tree)
 {
   root_ = tree->root.get();
-  setXMarksSizeAndPosition(tree->blocked_boundaries);
+  setXMarksSize();
 }
 
-void Graphics::setXMarksSizeAndPosition(
-    const std::set<Boundary>& blocked_boundaries)
+// Mark to indicate blocked regions for pins.
+void Graphics::setXMarksSize()
 {
-  const odb::Rect die = block_->getDieArea();
+  const odb::Rect& die = block_->getDieArea();
 
   // Not too big/small
-  x_mark_size_ = (die.dx() + die.dy()) * 0.03;
-
-  for (Boundary boundary : blocked_boundaries) {
-    odb::Point x_mark_point;
-
-    switch (boundary) {
-      case L: {
-        x_mark_point = odb::Point(die.xMin(), die.yCenter());
-        break;
-      }
-      case R: {
-        x_mark_point = odb::Point(die.xMax(), die.yCenter());
-        break;
-      }
-      case B: {
-        x_mark_point = odb::Point(die.xCenter(), die.yMin());
-        break;
-      }
-      case T: {
-        x_mark_point = odb::Point(die.xCenter(), die.yMax());
-        break;
-      }
-      case NONE:
-        break;
-    }
-
-    blocked_boundary_to_mark_[boundary] = x_mark_point;
-  }
+  x_mark_size_ = (die.dx() + die.dy()) * 0.02;
 }
 
 void Graphics::drawCluster(Cluster* cluster, gui::Painter& painter)
@@ -522,7 +495,7 @@ void Graphics::drawObjects(gui::Painter& painter)
     }
   }
 
-  drawBlockedBoundariesIndication(painter);
+  drawBlockedRegionsIndication(painter);
 
   painter.setBrush(gui::Painter::transparent);
   if (only_final_result_) {
@@ -568,13 +541,13 @@ void Graphics::drawGuides(gui::Painter& painter)
   }
 }
 
-void Graphics::drawBlockedBoundariesIndication(gui::Painter& painter)
+void Graphics::drawBlockedRegionsIndication(gui::Painter& painter)
 {
   painter.setPen(gui::Painter::red, true);
   painter.setBrush(gui::Painter::transparent);
 
-  for (const auto [boundary, x_mark_point] : blocked_boundary_to_mark_) {
-    painter.drawX(x_mark_point.getX(), x_mark_point.getY(), x_mark_size_);
+  for (const odb::Rect& region : blocked_regions_for_pins_) {
+    painter.drawX(region.xCenter(), region.yCenter(), x_mark_size_);
   }
 }
 
@@ -587,7 +560,7 @@ void Graphics::drawBundledNets(gui::Painter& painter,
     const T& target = macros[bundled_net.terminals.second];
 
     if (target.isClusterOfUnplacedIOPins()) {
-      drawDistToIoConstraintBoundary(painter, source, target);
+      drawDistToRegion(painter, source, target);
       continue;
     }
 
@@ -605,51 +578,31 @@ void Graphics::drawBundledNets(gui::Painter& painter,
 }
 
 template <typename T>
-void Graphics::drawDistToIoConstraintBoundary(gui::Painter& painter,
-                                              const T& macro,
-                                              const T& io)
+void Graphics::drawDistToRegion(gui::Painter& painter,
+                                const T& macro,
+                                const T& io)
 {
   if (isOutsideTheOutline(macro)) {
     return;
   }
 
-  const int x1 = block_->micronsToDbu(macro.getPinX());
-  const int y1 = block_->micronsToDbu(macro.getPinY());
-  odb::Point from(x1, y1);
+  odb::Point from(block_->micronsToDbu(macro.getPinX()),
+                  block_->micronsToDbu(macro.getPinY()));
+  from.addX(outline_.xMin());
+  from.addY(outline_.yMin());
 
   odb::Point to;
-  Boundary constraint_boundary = io.getCluster()->getConstraintBoundary();
-
-  if (constraint_boundary == Boundary::L
-      || constraint_boundary == Boundary::R) {
-    const int x2 = block_->micronsToDbu(io.getPinX());
-    const int y2 = block_->micronsToDbu(macro.getPinY());
-    to.setX(x2);
-    to.setY(y2);
-  } else if (constraint_boundary == Boundary::B
-             || constraint_boundary == Boundary::T) {
-    const int x2 = block_->micronsToDbu(macro.getPinX());
-    const int y2 = block_->micronsToDbu(io.getPinY());
-    to.setX(x2);
-    to.setY(y2);
+  if (io.getCluster()->isClusterOfUnconstrainedIOPins()) {
+    computeDistToNearestRegion(
+        from, available_regions_for_unconstrained_pins_, &to);
   } else {
-    // We need to use the bbox of the SoftMacro to get the necessary
-    // offset compensation (the cluster bbox is the bbox w.r.t. to the
-    // actual die area).
-    const Rect offset_die = io.getBBox();
-    Boundary closest_unblocked_boundary
-        = getClosestUnblockedBoundary(macro, offset_die);
-
-    to = getClosestBoundaryPoint(macro, offset_die, closest_unblocked_boundary);
+    computeDistToNearestRegion(
+        from, {io_cluster_to_constraint_.at(io.getCluster())}, &to);
   }
 
-  addOutlineOffsetToLine(from, to);
-
   painter.drawLine(from, to);
-  painter.drawString(to.getX(),
-                     to.getY(),
-                     gui::Painter::CENTER,
-                     toString(constraint_boundary));
+  painter.drawString(
+      to.getX(), to.getY(), gui::Painter::CENTER, "Unconstrained IOs");
 }
 
 template <typename T>
@@ -659,32 +612,6 @@ bool Graphics::isOutsideTheOutline(const T& macro) const
          || block_->micronsToDbu(macro.getPinY()) > outline_.dy();
 }
 
-// Here, we have to manually decompensate the offset of the
-// coordinates that come from the cluster.
-template <typename T>
-odb::Point Graphics::getClosestBoundaryPoint(const T& macro,
-                                             const Rect& die,
-                                             Boundary closest_boundary)
-{
-  odb::Point to;
-
-  if (closest_boundary == Boundary::L) {
-    to.setX(block_->micronsToDbu(die.xMin()));
-    to.setY(block_->micronsToDbu(macro.getPinY()));
-  } else if (closest_boundary == Boundary::R) {
-    to.setX(block_->micronsToDbu(die.xMax()));
-    to.setY(block_->micronsToDbu(macro.getPinY()));
-  } else if (closest_boundary == Boundary::B) {
-    to.setX(block_->micronsToDbu(macro.getPinX()));
-    to.setY(block_->micronsToDbu(die.yMin()));
-  } else {  // Top
-    to.setX(block_->micronsToDbu(macro.getPinX()));
-    to.setY(block_->micronsToDbu(die.yMax()));
-  }
-
-  return to;
-}
-
 void Graphics::addOutlineOffsetToLine(odb::Point& from, odb::Point& to)
 {
   from.addX(outline_.xMin());
@@ -693,55 +620,6 @@ void Graphics::addOutlineOffsetToLine(odb::Point& from, odb::Point& to)
   to.addY(outline_.yMin());
 }
 
-template <typename T>
-Boundary Graphics::getClosestUnblockedBoundary(const T& macro, const Rect& die)
-{
-  const float macro_x = macro.getPinX();
-  const float macro_y = macro.getPinY();
-
-  float shortest_distance = std::numeric_limits<float>::max();
-  Boundary closest_boundary = Boundary::NONE;
-
-  if (!isBlockedBoundary(Boundary::L)) {
-    const float dist_to_left = std::abs(macro_x - die.xMin());
-    if (dist_to_left < shortest_distance) {
-      shortest_distance = dist_to_left;
-      closest_boundary = Boundary::L;
-    }
-  }
-
-  if (!isBlockedBoundary(Boundary::R)) {
-    const float dist_to_right = std::abs(macro_x - die.xMax());
-    if (dist_to_right < shortest_distance) {
-      shortest_distance = dist_to_right;
-      closest_boundary = Boundary::R;
-    }
-  }
-
-  if (!isBlockedBoundary(Boundary::B)) {
-    const float dist_to_bottom = std::abs(macro_y - die.yMin());
-    if (dist_to_bottom < shortest_distance) {
-      shortest_distance = dist_to_bottom;
-      closest_boundary = Boundary::B;
-    }
-  }
-
-  if (!isBlockedBoundary(Boundary::T)) {
-    const float dist_to_top = std::abs(macro_y - die.yMax());
-    if (dist_to_top < shortest_distance) {
-      closest_boundary = Boundary::T;
-    }
-  }
-
-  return closest_boundary;
-}
-
-bool Graphics::isBlockedBoundary(Boundary boundary)
-{
-  return blocked_boundary_to_mark_.find(boundary)
-         != blocked_boundary_to_mark_.end();
-}
-
 // Give some transparency to mixed and hard so we can see overlap with
 // macro blockages.
 void Graphics::setSoftMacroBrush(gui::Painter& painter,
@@ -830,6 +708,24 @@ void Graphics::setFences(const std::map<int, Rect>& fences)
   fences_ = fences;
 }
 
+void Graphics::setIOConstraintsMap(
+    const ClusterToBoundaryRegionMap& io_cluster_to_constraint)
+{
+  io_cluster_to_constraint_ = io_cluster_to_constraint;
+}
+
+void Graphics::setBlockedRegionsForPins(
+    const std::vector<odb::Rect>& blocked_regions_for_pins)
+{
+  blocked_regions_for_pins_ = blocked_regions_for_pins;
+}
+
+void Graphics::setAvailableRegionsForUnconstrainedPins(
+    const BoundaryRegionList& regions)
+{
+  available_regions_for_unconstrained_pins_ = regions;
+}
+
 void Graphics::eraseDrawing()
 {
   // Ensure we don't try to access the clusters after they were deleted
@@ -842,7 +738,7 @@ void Graphics::eraseDrawing()
   bundled_nets_.clear();
   outline_.reset(0, 0, 0, 0);
   outlines_.clear();
-  blocked_boundary_to_mark_.clear();
+  blocked_regions_for_pins_.clear();
   guides_.clear();
 }
 
diff --git a/src/mpl/src/graphics.h b/src/mpl/src/graphics.h
index 9269b8e8980..230c2b19a15 100644
--- a/src/mpl/src/graphics.h
+++ b/src/mpl/src/graphics.h
@@ -61,14 +61,20 @@ class Graphics : public gui::Renderer, public MplObserver
   void setCurrentCluster(Cluster* current_cluster) override;
   void setGuides(const std::map<int, Rect>& guides) override;
   void setFences(const std::map<int, Rect>& fences) override;
+  void setIOConstraintsMap(
+      const ClusterToBoundaryRegionMap& io_cluster_to_constraint) override;
+  void setBlockedRegionsForPins(
+      const std::vector<odb::Rect>& blocked_regions_for_pins) override;
+  void setAvailableRegionsForUnconstrainedPins(
+      const BoundaryRegionList& regions) override;
 
   void eraseDrawing() override;
 
  private:
-  void setXMarksSizeAndPosition(const std::set<Boundary>& blocked_boundaries);
+  void setXMarksSize();
   void resetPenalties();
   void drawCluster(Cluster* cluster, gui::Painter& painter);
-  void drawBlockedBoundariesIndication(gui::Painter& painter);
+  void drawBlockedRegionsIndication(gui::Painter& painter);
   void drawAllBlockages(gui::Painter& painter);
   void drawOffsetRect(const Rect& rect,
                       const std::string& center_text,
@@ -78,18 +84,9 @@ class Graphics : public gui::Renderer, public MplObserver
   template <typename T>
   void drawBundledNets(gui::Painter& painter, const std::vector<T>& macros);
   template <typename T>
-  void drawDistToIoConstraintBoundary(gui::Painter& painter,
-                                      const T& macro,
-                                      const T& io);
+  void drawDistToRegion(gui::Painter& painter, const T& macro, const T& io);
   template <typename T>
   bool isOutsideTheOutline(const T& macro) const;
-  template <typename T>
-  odb::Point getClosestBoundaryPoint(const T& macro,
-                                     const Rect& die,
-                                     Boundary closest_boundary);
-  template <typename T>
-  Boundary getClosestUnblockedBoundary(const T& macro, const Rect& die);
-  bool isBlockedBoundary(Boundary boundary);
   void addOutlineOffsetToLine(odb::Point& from, odb::Point& to);
   void setSoftMacroBrush(gui::Painter& painter, const SoftMacro& soft_macro);
   void fetchSoftAndHard(Cluster* parent,
@@ -111,7 +108,9 @@ class Graphics : public gui::Renderer, public MplObserver
   odb::Rect outline_;
   int target_cluster_id_{-1};
   std::vector<std::vector<odb::Rect>> outlines_;
-  std::map<Boundary, odb::Point> blocked_boundary_to_mark_;
+  std::vector<odb::Rect> blocked_regions_for_pins_;
+  BoundaryRegionList available_regions_for_unconstrained_pins_;
+  ClusterToBoundaryRegionMap io_cluster_to_constraint_;
 
   // In Soft SA, we're shaping/placing the children of a certain parent,
   // so for this case, the current cluster is actually the current parent.
@@ -119,7 +118,7 @@ class Graphics : public gui::Renderer, public MplObserver
   std::map<int, Rect> guides_;  // Id -> Guidance Region
   std::map<int, Rect> fences_;  // Id -> Fence
 
-  int x_mark_size_{0};  // For blocked boundaries.
+  int x_mark_size_{0};  // For blocked regions.
 
   bool active_ = true;
   bool coarse_;
diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp
index c8f04e3ea18..a1ef8cb115d 100644
--- a/src/mpl/src/hier_rtlmp.cpp
+++ b/src/mpl/src/hier_rtlmp.cpp
@@ -232,7 +232,7 @@ void HierRTLMP::run()
     graphics_->drawResult();
   }
 
-  Pusher pusher(logger_, tree_->root.get(), block_, boundary_to_io_blockage_);
+  Pusher pusher(logger_, tree_->root.get(), block_, io_blockages_);
   pusher.pushMacrosToCoreBoundaries();
 
   updateMacrosOnDb();
@@ -259,7 +259,7 @@ void HierRTLMP::init()
 void HierRTLMP::runMultilevelAutoclustering()
 {
   clustering_engine_ = std::make_unique<ClusteringEngine>(
-      block_, network_, logger_, tritonpart_);
+      block_, network_, logger_, tritonpart_, graphics_.get());
 
   // Set target structure
   clustering_engine_->setTree(tree_.get());
@@ -317,7 +317,8 @@ void HierRTLMP::runCoarseShaping()
 
   calculateChildrenTilings(tree_->root.get());
 
-  setPinAccessBlockages();
+  searchAvailableRegionsForUnconstrainedPins();
+  createPinAccessBlockages();
   setPlacementBlockages();
 }
 
@@ -481,7 +482,8 @@ void HierRTLMP::calculateChildrenTilings(Cluster* parent)
                                               num_perturb_per_step,
                                               random_seed_,
                                               graphics_.get(),
-                                              logger_);
+                                              logger_,
+                                              block_);
       sa_batch.push_back(std::move(sa));
     }
     if (sa_batch.size() == 1) {
@@ -540,7 +542,8 @@ void HierRTLMP::calculateChildrenTilings(Cluster* parent)
                                               num_perturb_per_step,
                                               random_seed_,
                                               graphics_.get(),
-                                              logger_);
+                                              logger_,
+                                              block_);
       sa_batch.push_back(std::move(sa));
     }
     if (sa_batch.size() == 1) {
@@ -720,7 +723,8 @@ void HierRTLMP::calculateMacroTilings(Cluster* cluster)
                                               num_perturb_per_step,
                                               random_seed_ + run_id,
                                               graphics_.get(),
-                                              logger_);
+                                              logger_,
+                                              block_);
       sa_batch.push_back(std::move(sa));
     }
     if (sa_batch.size() == 1) {
@@ -774,7 +778,8 @@ void HierRTLMP::calculateMacroTilings(Cluster* cluster)
                                               num_perturb_per_step,
                                               random_seed_ + run_id,
                                               graphics_.get(),
-                                              logger_);
+                                              logger_,
+                                              block_);
       sa_batch.push_back(std::move(sa));
     }
     if (sa_batch.size() == 1) {
@@ -867,12 +872,49 @@ void HierRTLMP::setTightPackingTilings(Cluster* macro_array)
   macro_array->setTilings(tight_packing_tilings);
 }
 
-void HierRTLMP::setPinAccessBlockages()
+void HierRTLMP::searchAvailableRegionsForUnconstrainedPins()
+{
+  if (treeHasConstrainedIOs()) {
+    return;
+  }
+
+  const std::vector<odb::Rect>& blocked_regions_for_pins
+      = block_->getBlockedRegionsForPins();
+
+  BoundaryToRegionsMap boundary_to_blocked_regions
+      = getBoundaryToBlockedRegionsMap(blocked_regions_for_pins);
+  std::vector<odb::Rect> available_regions
+      = computeAvailableRegions(boundary_to_blocked_regions);
+
+  tree_->available_regions_for_unconstrained_pins.reserve(
+      available_regions.size());
+  for (const odb::Rect& region : available_regions) {
+    tree_->available_regions_for_unconstrained_pins.emplace_back(
+        rectToLine(block_, region, logger_), getBoundary(block_, region));
+  }
+
+  if (graphics_) {
+    graphics_->setBlockedRegionsForPins(blocked_regions_for_pins);
+    graphics_->setAvailableRegionsForUnconstrainedPins(
+        tree_->available_regions_for_unconstrained_pins);
+  }
+}
+
+void HierRTLMP::createPinAccessBlockages()
 {
   if (!tree_->maps.pad_to_bterm.empty()) {
     return;
   }
 
+  if (!treeHasConstrainedIOs() && block_->getBlockedRegionsForPins().empty()) {
+    // If there are no constraints at all, we give freedom to SA so it
+    // doesn't have to deal with pin access blockages across the entire
+    // extension of all edges of the die area. This should help SA not
+    // relying on extreme utilizations to converge for designs such as
+    // sky130hd/uW.
+    return;
+  }
+
   const Metrics* top_module_metrics
       = tree_->maps.module_to_metrics.at(block_->getTopModule()).get();
 
@@ -881,107 +923,224 @@ void HierRTLMP::setPinAccessBlockages()
     return;
   }
 
-  std::vector<Cluster*> clusters_of_unplaced_io_pins
-      = getClustersOfUnplacedIOPins();
+  computePinAccessDepthLimits();
+
+  if (!tree_->available_regions_for_unconstrained_pins.empty()) {
+    createBlockagesForAvailableRegions();
+  } else {
+    createBlockagesForConstraintRegions();
+  }
+}
+
+void HierRTLMP::computePinAccessDepthLimits()
+{
   const Rect die = dbuToMicrons(block_->getDieArea());
+  constexpr float max_depth_proportion = 0.20;
 
-  const float depth
-      = computePinAccessBlockagesDepth(clusters_of_unplaced_io_pins, die);
+  pin_access_depth_limits_.horizontal = max_depth_proportion * die.getWidth();
+  pin_access_depth_limits_.vertical = max_depth_proportion * die.getHeight();
+}
 
-  for (Cluster* cluster_of_unplaced_io_pins : clusters_of_unplaced_io_pins) {
-    Boundary constraint_boundary
-        = cluster_of_unplaced_io_pins->getConstraintBoundary();
-    if (constraint_boundary != NONE) {
-      createPinAccessBlockage(constraint_boundary, depth, die);
+bool HierRTLMP::treeHasConstrainedIOs() const
+{
+  std::vector<Cluster*> io_clusters = getClustersOfUnplacedIOPins();
+  for (Cluster* io_cluster : io_clusters) {
+    if (!io_cluster->isClusterOfUnconstrainedIOPins()) {
+      return true;
     }
   }
+  return false;
+}
 
-  if (boundary_to_io_blockage_.empty()) {
-    // If there are no constraints at all, give freedom to SA so it
-    // doesn't have to deal with pin access blockages in all boundaries.
-    // This will help SA not relying on extreme utilizations to
-    // converge for designs such as sky130hd/uW.
-    if (tree_->blocked_boundaries.empty()) {
-      return;
-    }
+void HierRTLMP::createBlockagesForAvailableRegions()
+{
+  double io_span = 0.0;
+  for (const BoundaryRegion& region :
+       tree_->available_regions_for_unconstrained_pins) {
+    io_span += std::sqrt(
+        odb::Point::squaredDistance(region.line.pt0(), region.line.pt1()));
+  }
 
-    // There are only -exclude constraints, so we create pin access
-    // blockages based on the boundaries that are not blocked.
-    if (tree_->blocked_boundaries.find(L) == tree_->blocked_boundaries.end()) {
-      createPinAccessBlockage(L, depth, die);
-    }
+  const float depth = computePinAccessBaseDepth(block_->dbuToMicrons(io_span));
 
-    if (tree_->blocked_boundaries.find(R) == tree_->blocked_boundaries.end()) {
-      createPinAccessBlockage(R, depth, die);
-    }
+  for (const BoundaryRegion region :
+       tree_->available_regions_for_unconstrained_pins) {
+    createPinAccessBlockage(region, depth);
+  }
+}
 
-    if (tree_->blocked_boundaries.find(B) == tree_->blocked_boundaries.end()) {
-      createPinAccessBlockage(B, depth, die);
+void HierRTLMP::createBlockagesForConstraintRegions()
+{
+  float io_span = 0.0f;
+  std::vector<Cluster*> clusters_of_unplaced_ios
+      = getClustersOfUnplacedIOPins();
+
+  for (Cluster* cluster_of_unplaced_ios : clusters_of_unplaced_ios) {
+    if (cluster_of_unplaced_ios->isClusterOfUnconstrainedIOPins()) {
+      continue;
     }
 
-    if (tree_->blocked_boundaries.find(T) == tree_->blocked_boundaries.end()) {
-      createPinAccessBlockage(T, depth, die);
+    // Reminder: the region rect is always a line for a cluster
+    // of constrained pins.
+    const Rect region = cluster_of_unplaced_ios->getBBox();
+    io_span += region.getPerimeter() / 2;
+  }
+
+  const float base_depth = computePinAccessBaseDepth(io_span);
+  const int total_ios = static_cast<int>(block_->getBTerms().size());
+
+  for (Cluster* cluster_of_unplaced_ios : clusters_of_unplaced_ios) {
+    if (cluster_of_unplaced_ios->isClusterOfUnconstrainedIOPins()) {
+      continue;
     }
+
+    const float cluster_number_of_ios = static_cast<float>(
+        clustering_engine_->getNumberOfIOs(cluster_of_unplaced_ios));
+
+    const float io_density_factor = cluster_number_of_ios / total_ios;
+    const float depth = base_depth * io_density_factor;
+
+    const odb::Rect region_rect
+        = micronsToDbu(cluster_of_unplaced_ios->getBBox());
+    const odb::Line region_line = rectToLine(block_, region_rect, logger_);
+    const BoundaryRegion region(region_line, getBoundary(block_, region_rect));
+    createPinAccessBlockage(region, depth);
   }
 }
 
-void HierRTLMP::createPinAccessBlockage(Boundary constraint_boundary,
-                                        const float depth,
-                                        const Rect& die)
+BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap(
+    const std::vector<odb::Rect>& blocked_regions_for_pins) const
 {
-  Rect blockage = die;
-  if (constraint_boundary == L) {
-    blockage.setXMax(blockage.xMin() + depth);
-  } else if (constraint_boundary == T) {
-    blockage.setYMin(blockage.yMax() - depth);
-  } else if (constraint_boundary == R) {
-    blockage.setXMin(blockage.xMax() - depth);
-  } else {  // Bottom
-    blockage.setYMax(blockage.yMin() + depth);
+  BoundaryToRegionsMap boundary_to_blocked_regions;
+  std::queue<odb::Rect> blocked_regions;
+
+  boundary_to_blocked_regions[Boundary::L] = blocked_regions;
+  boundary_to_blocked_regions[Boundary::R] = blocked_regions;
+  boundary_to_blocked_regions[Boundary::B] = blocked_regions;
+  boundary_to_blocked_regions[Boundary::T] = blocked_regions;
+
+  for (const odb::Rect& blocked_region : blocked_regions_for_pins) {
+    Boundary boundary = getBoundary(block_, blocked_region);
+    boundary_to_blocked_regions.at(boundary).push(blocked_region);
+
+    debugPrint(logger_,
+               MPL,
+               "coarse_shaping",
+               1,
+               "Found blocked region {} in {} boundary.",
+               blocked_region,
+               toString(boundary));
   }
 
-  boundary_to_io_blockage_[constraint_boundary] = blockage;
-  macro_blockages_.push_back(blockage);
+  return boundary_to_blocked_regions;
 }
 
-std::vector<Cluster*> HierRTLMP::getClustersOfUnplacedIOPins()
+std::vector<odb::Rect> HierRTLMP::computeAvailableRegions(
+    BoundaryToRegionsMap& boundary_to_blocked_regions) const
 {
-  std::vector<Cluster*> clusters_of_unplaced_io_pins;
+  std::vector<odb::Rect> available_regions;
 
-  for (const auto& child : tree_->root->getChildren()) {
-    if (child->isClusterOfUnplacedIOPins()) {
-      clusters_of_unplaced_io_pins.push_back(child.get());
+  for (auto& [boundary, blocked_regions] : boundary_to_blocked_regions) {
+    // The initial available region is the entire edge of the die area.
+    std::vector<odb::Rect> boundary_available_regions = {getRect(boundary)};
+
+    while (!blocked_regions.empty()) {
+      odb::Rect blocked_region = blocked_regions.front();
+      blocked_regions.pop();
+
+      std::vector<odb::Rect> new_boundary_available_regions;
+      for (const odb::Rect& boundary_available_region :
+           boundary_available_regions) {
+        if (!boundary_available_region.contains(blocked_region)) {
+          new_boundary_available_regions.push_back(boundary_available_region);
+          continue;
+        }
+
+        std::vector<odb::Rect> subtraction_result
+            = subtractOverlapRegion(boundary_available_region, blocked_region);
+        new_boundary_available_regions.insert(
+            new_boundary_available_regions.end(),
+            subtraction_result.begin(),
+            subtraction_result.end());
+      }
+
+      boundary_available_regions = new_boundary_available_regions;
     }
+
+    available_regions.insert(available_regions.end(),
+                             boundary_available_regions.begin(),
+                             boundary_available_regions.end());
   }
 
-  return clusters_of_unplaced_io_pins;
+  return available_regions;
 }
 
-// The depth of pin access blockages is computed based on:
-// 1) Amount of std cell area in the design.
-// 2) Extension of the IO clusters across the design's boundaries.
-float HierRTLMP::computePinAccessBlockagesDepth(
-    const std::vector<Cluster*>& io_clusters,
-    const Rect& die)
+void HierRTLMP::createPinAccessBlockage(const BoundaryRegion& region,
+                                        const float depth)
 {
-  float io_clusters_extension = 0.0;
+  float blockage_depth;
+  if (isVertical(region.boundary)) {
+    blockage_depth = depth > pin_access_depth_limits_.horizontal
+                         ? pin_access_depth_limits_.horizontal
+                         : depth;
+  } else {
+    blockage_depth = depth > pin_access_depth_limits_.vertical
+                         ? pin_access_depth_limits_.vertical
+                         : depth;
+  }
 
-  for (Cluster* io_cluster : io_clusters) {
-    if (io_cluster->getConstraintBoundary() == NONE) {
-      const Rect die = io_cluster->getBBox();
-      io_clusters_extension = die.getPerimeter();
+  debugPrint(logger_,
+             MPL,
+             "coarse_shaping",
+             1,
+             "Creating pin access blockage in {} -> Region line = ({}) ({}) , "
+             "Depth = {}",
+             toString(region.boundary),
+             region.line.pt0(),
+             region.line.pt1(),
+             blockage_depth);
+
+  Rect blockage = dbuToMicrons(lineToRect(region.line));
+  switch (region.boundary) {
+    case (Boundary::L): {
+      blockage.setXMax(blockage.xMin() + blockage_depth);
+      break;
+    }
+    case (Boundary::R): {
+      blockage.setXMin(blockage.xMax() - blockage_depth);
+      break;
+    }
+    case (Boundary::B): {
+      blockage.setYMax(blockage.yMin() + blockage_depth);
+      break;
+    }
+    case (Boundary::T): {
+      blockage.setYMin(blockage.yMax() - blockage_depth);
       break;
     }
+  }
 
-    Boundary constraint_boundary = io_cluster->getConstraintBoundary();
+  macro_blockages_.push_back(blockage);
+  io_blockages_.push_back(blockage);
+}
 
-    if (constraint_boundary == L || constraint_boundary == R) {
-      io_clusters_extension += die.getWidth();
-    } else {  // Bottom or Top
-      io_clusters_extension += die.getHeight();
+std::vector<Cluster*> HierRTLMP::getClustersOfUnplacedIOPins() const
+{
+  std::vector<Cluster*> clusters_of_unplaced_io_pins;
+  for (const auto& child : tree_->root->getChildren()) {
+    if (child->isClusterOfUnplacedIOPins()) {
+      clusters_of_unplaced_io_pins.push_back(child.get());
     }
   }
+  return clusters_of_unplaced_io_pins;
+}
 
+// The base depth of pin access blockages is computed based on:
+// 1) Amount of std cell area in the design.
+// 2) Extension of IO span.
+// 3) Macro dominance quadratic factor.
+float HierRTLMP::computePinAccessBaseDepth(const double io_span) const
+{
   float std_cell_area = 0.0;
   for (auto& cluster : tree_->root->getChildren()) {
     if (cluster->getClusterType() == StdCellCluster) {
@@ -1000,17 +1159,17 @@ float HierRTLMP::computePinAccessBlockagesDepth(
   const float macro_dominance_factor
       = tree_->macro_with_halo_area
         / (tree_->root->getWidth() * tree_->root->getHeight());
-  const float depth = (std_cell_area / io_clusters_extension)
-                      * std::pow((1 - macro_dominance_factor), 2);
+  const float base_depth
+      = (std_cell_area / io_span) * std::pow((1 - macro_dominance_factor), 2);
 
   debugPrint(logger_,
              MPL,
              "coarse_shaping",
              1,
-             "Pin access blockages depth = {}",
-             depth);
+             "Base pin access depth: {} μm",
+             base_depth);
 
-  return depth;
+  return base_depth;
 }
 
 void HierRTLMP::setPlacementBlockages()
@@ -1382,7 +1541,8 @@ void HierRTLMP::placeChildren(Cluster* parent)
                                               num_perturb_per_step,
                                               random_seed_,
                                               graphics_.get(),
-                                              logger_);
+                                              logger_,
+                                              block_);
       sa->setNumberOfMacrosToPlace(num_of_macros_to_place);
       sa->setCentralizationAttemptOn(true);
       sa->setFences(fences);
@@ -1771,7 +1931,8 @@ void HierRTLMP::placeChildrenUsingMinimumTargetUtil(Cluster* parent)
                                               num_perturb_per_step,
                                               random_seed_,
                                               graphics_.get(),
-                                              logger_);
+                                              logger_,
+                                              block_);
       sa->setNumberOfMacrosToPlace(macros_to_place);
       sa->setCentralizationAttemptOn(true);
       sa->setFences(fences);
@@ -2294,7 +2455,8 @@ void HierRTLMP::placeMacros(Cluster* cluster)
                                               num_perturb_per_step,
                                               random_seed_ + run_id,
                                               graphics_.get(),
-                                              logger_);
+                                              logger_,
+                                              block_);
       sa->setNumberOfMacrosToPlace(macros_to_place);
       sa->setNets(nets);
       sa->setFences(fences);
@@ -2587,32 +2749,22 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro)
       }
 
       for (odb::dbBTerm* bterm : net->getBTerms()) {
-        auto constraint_region = bterm->getConstraintRegion();
+        const auto& constraint_region = bterm->getConstraintRegion();
+        odb::Point nearest_point;
         if (constraint_region) {
-          int x = constraint_region->xCenter();
-          int y = constraint_region->yCenter();
-          odb::Rect region_rect(x, y, x, y);
-          net_box.merge(region_rect);
+          BoundaryRegion constraint(
+              rectToLine(block_, *constraint_region, logger_),
+              getBoundary(block_, *constraint_region));
+          computeDistToNearestRegion(
+              macro_pin->getBBox().center(), {constraint}, &nearest_point);
         } else {
-          odb::Point macro_pin_location(macro_pin->getBBox().xCenter(),
-                                        macro_pin->getBBox().yCenter());
-          Boundary closest_boundary = getClosestBoundary(
-              macro_pin_location, tree_->unblocked_boundaries);
-
-          // As we classify the blocked/unblocked state of the boundary based on
-          // the extension of the -exclude constraint, it's possible to have
-          // all boundaries blocked for IOs even though there are small
-          // unblocked spaces in those boundaries. For this situation, we just
-          // skip IOs without constraint regions.
-          if (closest_boundary == NONE) {
-            continue;
-          }
-
-          odb::Point closest_point
-              = getClosestBoundaryPoint(macro_pin_location, closest_boundary);
-          odb::Rect closest_point_rect(closest_point, closest_point);
-          net_box.merge(closest_point_rect);
+          computeDistToNearestRegion(
+              macro_pin->getBBox().center(),
+              tree_->available_regions_for_unconstrained_pins,
+              &nearest_point);
         }
+        odb::Rect point_rect(nearest_point, nearest_point);
+        net_box.merge(point_rect);
       }
 
       wirelength += block_->dbuToMicrons(net_box.dx() + net_box.dy());
@@ -2622,65 +2774,6 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro)
   return wirelength;
 }
 
-// Search the given boundaries list for the closest boundary to the point.
-Boundary HierRTLMP::getClosestBoundary(const odb::Point& from,
-                                       const std::set<Boundary>& boundaries)
-{
-  Boundary closest_boundary = NONE;
-  int shortest_distance = std::numeric_limits<int>::max();
-
-  for (const Boundary boundary : boundaries) {
-    const int dist_to_boundary = getDistanceToBoundary(from, boundary);
-    if (dist_to_boundary < shortest_distance) {
-      shortest_distance = dist_to_boundary;
-      closest_boundary = boundary;
-    }
-  }
-
-  return closest_boundary;
-}
-
-int HierRTLMP::getDistanceToBoundary(const odb::Point& from,
-                                     const Boundary boundary)
-{
-  int distance = 0;
-
-  if (boundary == L) {
-    distance = from.x() - block_->getDieArea().xMin();
-  } else if (boundary == R) {
-    distance = from.x() - block_->getDieArea().xMax();
-  } else if (boundary == B) {
-    distance = from.y() - block_->getDieArea().yMin();
-  } else if (boundary == T) {
-    distance = from.y() - block_->getDieArea().yMax();
-  }
-
-  return std::abs(distance);
-}
-
-odb::Point HierRTLMP::getClosestBoundaryPoint(const odb::Point& from,
-                                              const Boundary boundary)
-{
-  odb::Point closest_boundary_point;
-  const odb::Rect& die = block_->getDieArea();
-
-  if (boundary == L) {
-    closest_boundary_point.setX(die.xMin());
-    closest_boundary_point.setY(from.y());
-  } else if (boundary == R) {
-    closest_boundary_point.setX(die.xMax());
-    closest_boundary_point.setY(from.y());
-  } else if (boundary == B) {
-    closest_boundary_point.setX(from.x());
-    closest_boundary_point.setY(die.yMin());
-  } else {  // Top
-    closest_boundary_point.setX(from.x());
-    closest_boundary_point.setY(die.yMax());
-  }
-
-  return closest_boundary_point;
-}
-
 void HierRTLMP::flipRealMacro(odb::dbInst* macro, const bool& is_vertical_flip)
 {
   if (is_vertical_flip) {
@@ -2852,6 +2945,82 @@ Rect HierRTLMP::dbuToMicrons(const odb::Rect& dbu_rect)
               block_->dbuToMicrons(dbu_rect.yMax()));
 }
 
+// Example for a vertical region:
+//  Base - Overlay = Result
+//   |                  |
+//   |                  | "b"
+//   |                  |
+//   |        |
+//   |        |
+//   |        |
+//   |                  |
+//   |                  | "a"
+//   |                  |
+std::vector<odb::Rect> HierRTLMP::subtractOverlapRegion(
+    const odb::Rect& base,
+    const odb::Rect& overlay) const
+{
+  Boundary base_boundary = getBoundary(block_, base);
+
+  if (base_boundary != getBoundary(block_, overlay)) {
+    logger_->critical(
+        MPL, 46, "Attempting to subtract regions from different boundaries.");
+  }
+
+  std::vector<odb::Rect> result;
+  odb::Rect a = base;
+  odb::Rect b = base;
+
+  if (isVertical(base_boundary)) {
+    a.set_yhi(overlay.yMin());
+    b.set_ylo(overlay.yMax());
+  } else {
+    a.set_xhi(overlay.xMin());
+    b.set_xlo(overlay.xMax());
+  }
+
+  if (a.dx() != 0 || a.dy() != 0) {
+    result.push_back(a);
+  }
+
+  if (b.dx() != 0 || b.dy() != 0) {
+    result.push_back(b);
+  }
+
+  return result;
+}
+
+bool HierRTLMP::isVertical(Boundary boundary) const
+{
+  return boundary == Boundary::L || boundary == Boundary::R;
+}
+
+odb::Rect HierRTLMP::getRect(Boundary boundary) const
+{
+  odb::Rect boundary_rect = block_->getDieArea();
+
+  switch (boundary) {
+    case (Boundary::L): {
+      boundary_rect.set_xhi(boundary_rect.xMin());
+      break;
+    }
+    case (Boundary::R): {
+      boundary_rect.set_xlo(boundary_rect.xMax());
+      break;
+    }
+    case (Boundary::T): {
+      boundary_rect.set_ylo(boundary_rect.yMax());
+      break;
+    }
+    case (Boundary::B): {
+      boundary_rect.set_yhi(boundary_rect.yMin());
+      break;
+    }
+  }
+
+  return boundary_rect;
+}
+
 template <typename SACore>
 void HierRTLMP::printPlacementResult(Cluster* parent,
                                      const Rect& outline,
@@ -2871,22 +3040,20 @@ void HierRTLMP::printPlacementResult(Cluster* parent,
 Pusher::Pusher(utl::Logger* logger,
                Cluster* root,
                odb::dbBlock* block,
-               const std::map<Boundary, Rect>& boundary_to_io_blockage)
+               const std::vector<Rect>& io_blockages)
     : logger_(logger), root_(root), block_(block)
 {
   core_ = block_->getCoreArea();
-  setIOBlockages(boundary_to_io_blockage);
+  setIOBlockages(io_blockages);
 }
 
-void Pusher::setIOBlockages(
-    const std::map<Boundary, Rect>& boundary_to_io_blockage)
+void Pusher::setIOBlockages(const std::vector<Rect>& io_blockages)
 {
-  for (const auto& [boundary, box] : boundary_to_io_blockage) {
-    boundary_to_io_blockage_[boundary]
-        = odb::Rect(block_->micronsToDbu(box.xMin()),
-                    block_->micronsToDbu(box.yMin()),
-                    block_->micronsToDbu(box.xMax()),
-                    block_->micronsToDbu(box.yMax()));
+  for (const Rect& blockage : io_blockages) {
+    io_blockages_.emplace_back(block_->micronsToDbu(blockage.xMin()),
+                               block_->micronsToDbu(blockage.yMin()),
+                               block_->micronsToDbu(blockage.xMax()),
+                               block_->micronsToDbu(blockage.yMax()));
   }
 }
 
@@ -2996,10 +3163,10 @@ std::map<Boundary, int> Pusher::getDistanceToCloseBoundaries(
   int smaller_hor_distance = 0;
 
   if (distance_to_left < distance_to_right) {
-    hor_boundary_to_push = L;
+    hor_boundary_to_push = Boundary::L;
     smaller_hor_distance = distance_to_left;
   } else {
-    hor_boundary_to_push = R;
+    hor_boundary_to_push = Boundary::R;
     smaller_hor_distance = distance_to_right;
   }
 
@@ -3014,10 +3181,10 @@ std::map<Boundary, int> Pusher::getDistanceToCloseBoundaries(
   int smaller_ver_distance = 0;
 
   if (distance_to_bottom < distance_to_top) {
-    ver_boundary_to_push = B;
+    ver_boundary_to_push = Boundary::B;
     smaller_ver_distance = distance_to_bottom;
   } else {
-    ver_boundary_to_push = T;
+    ver_boundary_to_push = Boundary::T;
     smaller_ver_distance = distance_to_top;
   }
 
@@ -3068,7 +3235,7 @@ void Pusher::pushMacroClusterToCoreBoundaries(
     // Check based on the shape of the macro cluster to avoid iterating each
     // of its HardMacros.
     if (overlapsWithHardMacro(cluster_box, hard_macros)
-        || overlapsWithIOBlockage(cluster_box, boundary)) {
+        || overlapsWithIOBlockage(cluster_box)) {
       // Move back to original position.
       for (HardMacro* hard_macro : hard_macros) {
         moveHardMacro(hard_macro, boundary, (-distance));
@@ -3082,21 +3249,19 @@ void Pusher::moveMacroClusterBox(odb::Rect& cluster_box,
                                  const int distance)
 {
   switch (boundary) {
-    case NONE:
-      return;
-    case L: {
+    case (Boundary::L): {
       cluster_box.moveDelta(-distance, 0);
       break;
     }
-    case R: {
+    case (Boundary::R): {
       cluster_box.moveDelta(distance, 0);
       break;
     }
-    case T: {
+    case (Boundary::T): {
       cluster_box.moveDelta(0, distance);
       break;
     }
-    case B: {
+    case (Boundary::B): {
       cluster_box.moveDelta(0, -distance);
       break;
     }
@@ -3108,21 +3273,19 @@ void Pusher::moveHardMacro(HardMacro* hard_macro,
                            const int distance)
 {
   switch (boundary) {
-    case NONE:
-      return;
-    case L: {
+    case (Boundary::L): {
       hard_macro->setXDBU(hard_macro->getXDBU() - distance);
       break;
     }
-    case R: {
+    case (Boundary::R): {
       hard_macro->setXDBU(hard_macro->getXDBU() + distance);
       break;
     }
-    case T: {
+    case (Boundary::T): {
       hard_macro->setYDBU(hard_macro->getYDBU() + distance);
       break;
     }
-    case B: {
+    case (Boundary::B): {
       hard_macro->setYDBU(hard_macro->getYDBU() - distance);
       break;
     }
@@ -3164,25 +3327,18 @@ bool Pusher::overlapsWithHardMacro(
   return false;
 }
 
-bool Pusher::overlapsWithIOBlockage(const odb::Rect& cluster_box,
-                                    const Boundary boundary)
+bool Pusher::overlapsWithIOBlockage(const odb::Rect& cluster_box) const
 {
-  if (boundary_to_io_blockage_.find(boundary)
-      == boundary_to_io_blockage_.end()) {
-    return false;
-  }
-
-  const odb::Rect box = boundary_to_io_blockage_.at(boundary);
-
-  if (cluster_box.xMin() < box.xMax() && cluster_box.yMin() < box.yMax()
-      && cluster_box.xMax() > box.xMin() && cluster_box.yMax() > box.yMin()) {
-    debugPrint(logger_,
-               MPL,
-               "boundary_push",
-               1,
-               "\tFound overlap with IO blockage {}. Push will be reverted.",
-               box);
-    return true;
+  for (const odb::Rect& io_blockage : io_blockages_) {
+    if (cluster_box.overlaps(io_blockage)) {
+      debugPrint(logger_,
+                 MPL,
+                 "boundary_push",
+                 1,
+                 "\tFound overlap with IO blockage {}. Push will be reverted.",
+                 io_blockage);
+      return true;
+    }
   }
 
   return false;
diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h
index df9184846e4..1d350cde183 100644
--- a/src/mpl/src/hier_rtlmp.h
+++ b/src/mpl/src/hier_rtlmp.h
@@ -45,6 +45,8 @@ class Snapper;
 class SACoreSoftMacro;
 class SACoreHardMacro;
 
+using BoundaryToRegionsMap = std::map<Boundary, std::queue<odb::Rect>>;
+
 // The parameters necessary to compute one coordinate of the new
 // origin for aligning the macros' pins to the track-grid
 struct PatternParameters
@@ -120,6 +122,12 @@ class HierRTLMP
   void writeMacroPlacement(const std::string& file_name);
 
  private:
+  struct PinAccessDepthLimits
+  {
+    float vertical{0.0f};
+    float horizontal{0.0f};
+  };
+
   using SoftSAVector = std::vector<std::unique_ptr<SACoreSoftMacro>>;
   using HardSAVector = std::vector<std::unique_ptr<SACoreHardMacro>>;
 
@@ -140,13 +148,19 @@ class HierRTLMP
   void calculateMacroTilings(Cluster* cluster);
   IntervalList computeWidthIntervals(const TilingList& tilings);
   void setTightPackingTilings(Cluster* macro_array);
-  void setPinAccessBlockages();
-  std::vector<Cluster*> getClustersOfUnplacedIOPins();
-  float computePinAccessBlockagesDepth(const std::vector<Cluster*>& io_clusters,
-                                       const Rect& die);
-  void createPinAccessBlockage(Boundary constraint_boundary,
-                               float depth,
-                               const Rect& die);
+  void searchAvailableRegionsForUnconstrainedPins();
+  BoundaryToRegionsMap getBoundaryToBlockedRegionsMap(
+      const std::vector<odb::Rect>& blocked_regions_for_pins) const;
+  std::vector<odb::Rect> computeAvailableRegions(
+      BoundaryToRegionsMap& boundary_to_blocked_regions) const;
+  void createPinAccessBlockages();
+  void computePinAccessDepthLimits();
+  bool treeHasConstrainedIOs() const;
+  std::vector<Cluster*> getClustersOfUnplacedIOPins() const;
+  void createPinAccessBlockage(const BoundaryRegion& region, float depth);
+  float computePinAccessBaseDepth(double io_span) const;
+  void createBlockagesForAvailableRegions();
+  void createBlockagesForConstraintRegions();
   void setPlacementBlockages();
 
   // Fine Shaping
@@ -203,10 +217,6 @@ class HierRTLMP
 
   void correctAllMacrosOrientation();
   float calculateRealMacroWirelength(odb::dbInst* macro);
-  Boundary getClosestBoundary(const odb::Point& from,
-                              const std::set<Boundary>& boundaries);
-  int getDistanceToBoundary(const odb::Point& from, Boundary boundary);
-  odb::Point getClosestBoundaryPoint(const odb::Point& from, Boundary boundary);
   void adjustRealMacroOrientation(const bool& is_vertical_flip);
   void flipRealMacro(odb::dbInst* macro, const bool& is_vertical_flip);
 
@@ -219,6 +229,12 @@ class HierRTLMP
                            const Rect& outline,
                            std::vector<Macro>& macros);
 
+  odb::Rect getRect(Boundary boundary) const;
+  bool isVertical(Boundary boundary) const;
+
+  std::vector<odb::Rect> subtractOverlapRegion(const odb::Rect& base,
+                                               const odb::Rect& overlay) const;
+
   // For debugging
   template <typename SACore>
   void printPlacementResult(Cluster* parent,
@@ -276,7 +292,9 @@ class HierRTLMP
   std::map<odb::dbInst*, Rect> guides_;  // Macro -> Guidance Region
   std::vector<Rect> placement_blockages_;
   std::vector<Rect> macro_blockages_;
-  std::map<Boundary, Rect> boundary_to_io_blockage_;
+  std::vector<Rect> io_blockages_;
+
+  PinAccessDepthLimits pin_access_depth_limits_;
 
   // Fast SA hyperparameter
   float init_prob_ = 0.9;
@@ -307,12 +325,12 @@ class Pusher
   Pusher(utl::Logger* logger,
          Cluster* root,
          odb::dbBlock* block,
-         const std::map<Boundary, Rect>& boundary_to_io_blockage);
+         const std::vector<Rect>& io_blockages);
 
   void pushMacrosToCoreBoundaries();
 
  private:
-  void setIOBlockages(const std::map<Boundary, Rect>& boundary_to_io_blockage);
+  void setIOBlockages(const std::vector<Rect>& io_blockages);
   bool designHasSingleCentralizedMacroArray();
   void pushMacroClusterToCoreBoundaries(
       Cluster* macro_cluster,
@@ -327,7 +345,7 @@ class Pusher
   bool overlapsWithHardMacro(
       const odb::Rect& cluster_box,
       const std::vector<HardMacro*>& cluster_hard_macros);
-  bool overlapsWithIOBlockage(const odb::Rect& cluster_box, Boundary boundary);
+  bool overlapsWithIOBlockage(const odb::Rect& cluster_box) const;
 
   utl::Logger* logger_;
 
@@ -335,7 +353,7 @@ class Pusher
   odb::dbBlock* block_;
   odb::Rect core_;
 
-  std::map<Boundary, odb::Rect> boundary_to_io_blockage_;
+  std::vector<odb::Rect> io_blockages_;
   std::vector<HardMacro*> hard_macros_;
 };
 
diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp
index 780afe700bd..37362c16c5f 100644
--- a/src/mpl/src/object.cpp
+++ b/src/mpl/src/object.cpp
@@ -18,41 +18,6 @@
 namespace mpl {
 using utl::MPL;
 
-///////////////////////////////////////////////////////////////////////
-// Basic utility functions
-
-std::string toString(const Boundary& pin_access)
-{
-  switch (pin_access) {
-    case L:
-      return std::string("L");
-    case T:
-      return std::string("T");
-    case R:
-      return std::string("R");
-    case B:
-      return std::string("B");
-    default:
-      return std::string("NONE");
-  }
-}
-
-Boundary opposite(const Boundary& pin_access)
-{
-  switch (pin_access) {
-    case L:
-      return R;
-    case T:
-      return B;
-    case R:
-      return L;
-    case B:
-      return T;
-    default:
-      return NONE;
-  }
-}
-
 ///////////////////////////////////////////////////////////////////////
 // Metrics Class
 Metrics::Metrics(unsigned int num_std_cell,
@@ -233,8 +198,12 @@ std::string Cluster::getClusterTypeString() const
 {
   std::string cluster_type;
 
+  if (is_cluster_of_unconstrained_io_pins_) {
+    return "Unconstrained IOs";
+  }
+
   if (is_cluster_of_unplaced_io_pins_) {
-    return "Unplaced IO Pins";
+    return "Unplaced IOs";
   }
 
   if (is_io_pad_cluster_) {
@@ -300,13 +269,14 @@ void Cluster::copyInstances(const Cluster& cluster)
   }
 }
 
-void Cluster::setAsClusterOfUnplacedIOPins(const std::pair<float, float>& pos,
-                                           const float width,
-                                           const float height,
-                                           const Boundary constraint_boundary)
+void Cluster::setAsClusterOfUnplacedIOPins(
+    const std::pair<float, float>& pos,
+    const float width,
+    const float height,
+    const bool is_cluster_of_unconstrained_io_pins)
 {
   is_cluster_of_unplaced_io_pins_ = true;
-  constraint_boundary_ = constraint_boundary;
+  is_cluster_of_unconstrained_io_pins_ = is_cluster_of_unconstrained_io_pins;
   soft_macro_ = std::make_unique<SoftMacro>(pos, name_, width, height, this);
 }
 
@@ -323,6 +293,16 @@ bool Cluster::isIOCluster() const
   return is_cluster_of_unplaced_io_pins_ || is_io_pad_cluster_;
 }
 
+bool Cluster::isClusterOfUnconstrainedIOPins() const
+{
+  return is_cluster_of_unconstrained_io_pins_;
+}
+
+bool Cluster::isClusterOfUnplacedIOPins() const
+{
+  return is_cluster_of_unplaced_io_pins_;
+}
+
 void Cluster::setAsArrayOfInterconnectedMacros()
 {
   is_array_of_interconnected_macros = true;
@@ -813,9 +793,15 @@ bool HardMacro::isClusterOfUnplacedIOPins() const
   return cluster_->isClusterOfUnplacedIOPins();
 }
 
-Rect HardMacro::getBBox() const
+// Cluster support to identify if a fixed terminal correponds
+// to the cluster of unconstrained IO pins when running HardMacro SA.
+bool HardMacro::isClusterOfUnconstrainedIOPins() const
 {
-  return Rect(x_, y_, x_ + width_, y_ + height_);
+  if (!cluster_) {
+    return false;
+  }
+
+  return cluster_->isClusterOfUnconstrainedIOPins();
 }
 
 // Get Physical Information
@@ -1293,6 +1279,8 @@ bool SoftMacro::isMixedCluster() const
   return (cluster_->getClusterType() == MixedCluster);
 }
 
+// Cluster support to identify if a fixed terminal correponds
+// to a cluster of unplaced IO pins when running SoftMacro SA.
 bool SoftMacro::isClusterOfUnplacedIOPins() const
 {
   if (!cluster_) {
@@ -1302,6 +1290,17 @@ bool SoftMacro::isClusterOfUnplacedIOPins() const
   return cluster_->isClusterOfUnplacedIOPins();
 }
 
+// Cluster support to identify if a fixed terminal correponds
+// to the cluster of unconstrained IO pins when running SoftMacro SA.
+bool SoftMacro::isClusterOfUnconstrainedIOPins() const
+{
+  if (!cluster_) {
+    return false;
+  }
+
+  return cluster_->isClusterOfUnconstrainedIOPins();
+}
+
 void SoftMacro::setLocationF(float x, float y)
 {
   x_ = x;
diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h
index f4c4b046b64..95be2a0bcec 100644
--- a/src/mpl/src/object.h
+++ b/src/mpl/src/object.h
@@ -18,10 +18,10 @@
 #include "odb/dbTypes.h"
 #include "odb/odb.h"
 #include "shapes.h"
+#include "util.h"
 
 namespace odb {
 class Rect;
-class Point;
 class dbInst;
 class dbModule;
 class dbDatabase;
@@ -75,24 +75,6 @@ using Point = std::pair<float, float>;
 // we do not accept pre-placed std cells as our inputs.
 //*****************************************************************************
 
-// Define the position of pin access blockage
-// It can be {bottom, left, top, right} boundary of the cluster
-// Each pin access blockage is modeled by a movable hard macro
-// along the corresponding { B, L, T, R } boundary
-// The size of the hard macro blockage is determined the by the
-// size of that cluster
-enum Boundary
-{
-  NONE,
-  B,
-  L,
-  T,
-  R
-};
-
-std::string toString(const Boundary& pin_access);
-Boundary opposite(const Boundary& pin_access);
-
 // Define the type for clusters
 // StdCellCluster only has std cells. In the cluster type, it
 // only has leaf_std_cells_ and dbModules_
@@ -180,17 +162,12 @@ class Cluster
   void copyInstances(const Cluster& cluster);  // only based on cluster type
 
   bool isIOCluster() const;
-
-  bool isClusterOfUnplacedIOPins() const
-  {
-    return is_cluster_of_unplaced_io_pins_;
-  }
+  bool isClusterOfUnconstrainedIOPins() const;
+  bool isClusterOfUnplacedIOPins() const;
   void setAsClusterOfUnplacedIOPins(const std::pair<float, float>& pos,
                                     float width,
                                     float height,
-                                    Boundary constraint_boundary);
-  Boundary getConstraintBoundary() const { return constraint_boundary_; }
-
+                                    bool is_cluster_of_unconstrained_io_pins);
   bool isIOPadCluster() const { return is_io_pad_cluster_; }
   void setAsIOPadCluster(const std::pair<float, float>& pos,
                          float width,
@@ -282,8 +259,8 @@ class Cluster
   std::vector<HardMacro*> hard_macros_;
 
   bool is_cluster_of_unplaced_io_pins_{false};
+  bool is_cluster_of_unconstrained_io_pins_{false};
   bool is_io_pad_cluster_{false};
-  Boundary constraint_boundary_ = NONE;
 
   bool is_array_of_interconnected_macros = false;
 
@@ -347,7 +324,7 @@ class HardMacro
   void setCluster(Cluster* cluster) { cluster_ = cluster; }
   Cluster* getCluster() const { return cluster_; }
   bool isClusterOfUnplacedIOPins() const;
-  Rect getBBox() const;
+  bool isClusterOfUnconstrainedIOPins() const;
 
   // Get Physical Information
   // Note that the default X and Y include halo_width
@@ -514,6 +491,7 @@ class SoftMacro
   bool isStdCellCluster() const;
   bool isMixedCluster() const;
   bool isClusterOfUnplacedIOPins() const;
+  bool isClusterOfUnconstrainedIOPins() const;
   void setLocationF(float x, float y);
   void setShapeF(float width, float height);
   int getNumMacro() const;
diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h
index 20a9e3a776b..ddfb6b5b86f 100644
--- a/src/mpl/src/util.h
+++ b/src/mpl/src/util.h
@@ -3,12 +3,55 @@
 
 #pragma once
 
+#include <map>
 #include <string>
 #include <utility>
 
+#include "odb/db.h"
+#include "odb/geom.h"
 #include "shapes.h"
 
 namespace mpl {
+struct BoundaryRegion;
+class Cluster;
+
+using ClusterToBoundaryRegionMap = std::map<Cluster*, BoundaryRegion>;
+using BoundaryRegionList = std::vector<BoundaryRegion>;
+
+// One of the edges of the die area.
+enum class Boundary
+{
+  B,
+  L,
+  T,
+  R
+};
+
+inline std::string toString(const Boundary& boundary)
+{
+  std::string string;
+
+  switch (boundary) {
+    case (Boundary::L): {
+      string = 'L';
+      break;
+    }
+    case (Boundary::T): {
+      string = 'T';
+      break;
+    }
+    case (Boundary::R): {
+      string = 'R';
+      break;
+    }
+    case (Boundary::B): {
+      string = 'B';
+      break;
+    }
+  }
+
+  return string;
+}
 
 struct SACoreWeights
 {
@@ -35,6 +78,19 @@ struct PenaltyData
   float normalization_factor{0.0f};
 };
 
+// Object to help handling available regions and constraint regions for pins.
+struct BoundaryRegion
+{
+  BoundaryRegion() = default;
+  BoundaryRegion(const odb::Line& line, const Boundary boundary)
+      : line(line), boundary(boundary)
+  {
+  }
+
+  odb::Line line;
+  Boundary boundary = Boundary::L;
+};
+
 // Utility to help sorting width intervals.
 inline bool isMinWidthSmaller(const Interval& width_interval_a,
                               const Interval& width_interval_b)
@@ -52,4 +108,92 @@ inline bool isAreaSmaller(const Tiling& tiling_a, const Tiling& tiling_b)
   return tiling_a.width() < tiling_b.width();
 }
 
+inline Boundary getBoundary(odb::dbBlock* block, const odb::Rect& region)
+{
+  const odb::Rect& die = block->getDieArea();
+
+  if (region.dx() == 0) {
+    if (region.xMin() == die.xMin()) {
+      return Boundary::L;
+    }
+
+    return Boundary::R;
+  }
+
+  if (region.yMin() == die.yMin()) {
+    return Boundary::B;
+  }
+
+  return Boundary::T;
+}
+
+inline odb::Rect lineToRect(const odb::Line line)
+{
+  return odb::Rect(line.pt0(), line.pt1());
+}
+
+inline odb::Line rectToLine(odb::dbBlock* block,
+                            const odb::Rect& rect,
+                            utl::Logger* logger)
+{
+  if (rect.dx() != 0 && rect.dy() != 0) {
+    logger->error(utl::MPL,
+                  60,
+                  "Coundn't convert rect {} to line. The region is not a line.",
+                  rect);
+  }
+
+  return {rect.ll(), rect.ur()};
+}
+
+inline odb::Point computeNearestPointInRegion(const BoundaryRegion& region,
+                                              const odb::Point& target)
+{
+  const odb::Line& line = region.line;
+  if (region.boundary == Boundary::L || region.boundary == Boundary::R) {
+    if (target.y() >= line.pt1().y()) {
+      return line.pt1();
+    }
+    if (target.y() <= line.pt0().y()) {
+      return line.pt0();
+    }
+    return {line.pt0().x(), target.y()};
+  }
+
+  // Top or Bottom
+  if (target.x() >= line.pt1().x()) {
+    return line.pt1();
+  }
+  if (target.x() <= line.pt0().x()) {
+    return line.pt0();
+  }
+  return {target.x(), line.pt0().y()};
+}
+
+// The distance in DBU from the source to the nearest point of the nearest
+// region.
+inline double computeDistToNearestRegion(
+    const odb::Point& source,
+    const std::vector<BoundaryRegion>& regions,
+    odb::Point* nearest_point)
+{
+  int64_t smallest_distance = std::numeric_limits<int64_t>::max();
+
+  for (const BoundaryRegion& region : regions) {
+    const odb::Point nearest_point_in_region
+        = computeNearestPointInRegion(region, source);
+    const int64_t dist_to_nearest_point
+        = odb::Point::squaredDistance(source, nearest_point_in_region);
+
+    if (dist_to_nearest_point < smallest_distance) {
+      smallest_distance = dist_to_nearest_point;
+      if (nearest_point) {
+        *nearest_point = nearest_point_in_region;
+      }
+    }
+  }
+
+  return std::sqrt(smallest_distance);
+}
+
 }  // namespace mpl
diff --git a/src/mpl/test/BUILD b/src/mpl/test/BUILD
index edea651bad1..62bc209c1dc 100644
--- a/src/mpl/test/BUILD
+++ b/src/mpl/test/BUILD
@@ -10,6 +10,12 @@ COMPULSORY_TESTS = [
     "guides2",
     "io_constraints1",
     "io_constraints2",
+    "io_constraints3",
+    "io_constraints4",
+    "io_constraints5",
+    "io_constraints6",
+    "io_constraints7",
+    "io_constraints8",
     "io_pads1",
     "orientation_improve1",
     "orientation_improve2",
diff --git a/src/mpl/test/CMakeLists.txt b/src/mpl/test/CMakeLists.txt
index e38411b1861..6c65e0dde4c 100644
--- a/src/mpl/test/CMakeLists.txt
+++ b/src/mpl/test/CMakeLists.txt
@@ -7,6 +7,12 @@ or_integration_tests(
     guides2
     io_constraints1
     io_constraints2
+    io_constraints3
+    io_constraints4
+    io_constraints5
+    io_constraints6
+    io_constraints7
+    io_constraints8
     io_pads1
     orientation_improve1
     orientation_improve2
diff --git a/src/mpl/test/boundary_push2.defok b/src/mpl/test/boundary_push2.defok
index 1ebf92c2099..4974b643a37 100644
--- a/src/mpl/test/boundary_push2.defok
+++ b/src/mpl/test/boundary_push2.defok
@@ -183,9 +183,9 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
 TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
 TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
 COMPONENTS 54 ;
-    - MACRO_1 HM_100x100_1x1 + FIXED ( 600 20770 ) S ;
-    - MACRO_2 HM_100x100_1x1 + FIXED ( 239440 221810 ) FS ;
-    - MACRO_3 HM_100x100_1x1 + FIXED ( 600 221810 ) FS ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 600 221810 ) S ;
+    - MACRO_2 HM_100x100_1x1 + FIXED ( 600 20770 ) FS ;
+    - MACRO_3 HM_100x100_1x1 + FIXED ( 239440 221810 ) FS ;
     - MACRO_4 HM_100x100_1x1 + FIXED ( 239440 20770 ) FS ;
     - _001_ DFF_X1 + PLACED ( 15591 18600 ) N ;
     - _002_ DFF_X1 + PLACED ( 15591 18600 ) N ;
diff --git a/src/mpl/test/boundary_push3.defok b/src/mpl/test/boundary_push3.defok
index b8b404ab058..1b279a1ab94 100644
--- a/src/mpl/test/boundary_push3.defok
+++ b/src/mpl/test/boundary_push3.defok
@@ -183,9 +183,9 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
 TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
 TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
 COMPONENTS 54 ;
-    - MACRO_1 HM_100x100_1x1 + FIXED ( 19420 610 ) S ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 220620 610 ) S ;
     - MACRO_2 HM_100x100_1x1 + FIXED ( 19420 241970 ) FS ;
-    - MACRO_3 HM_100x100_1x1 + FIXED ( 220620 610 ) FS ;
+    - MACRO_3 HM_100x100_1x1 + FIXED ( 19420 610 ) FS ;
     - MACRO_4 HM_100x100_1x1 + FIXED ( 220620 241970 ) FS ;
     - _001_ DFF_X1 + PLACED ( 15590 18601 ) N ;
     - _002_ DFF_X1 + PLACED ( 15590 18601 ) N ;
diff --git a/src/mpl/test/io_constraints2.tcl b/src/mpl/test/io_constraints2.tcl
index f48b7bfe18b..090c6c4b544 100644
--- a/src/mpl/test/io_constraints2.tcl
+++ b/src/mpl/test/io_constraints2.tcl
@@ -1,5 +1,5 @@
 # Test if pin access blockage is generated correctly for a case
-# with all boundaries blocked except one.
+# with all boundaries entirely blocked except one.
 source "helpers.tcl"
 
 # We're not interested in the connections, so don't include the lib.
diff --git a/src/mpl/test/io_constraints3.defok b/src/mpl/test/io_constraints3.defok
new file mode 100644
index 00000000000..49acd7a712a
--- /dev/null
+++ b/src/mpl/test/io_constraints3.defok
@@ -0,0 +1,529 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 300000 250000 ) ;
+ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 401 ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 41330 ) FS ;
+    - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _004_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _005_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _006_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _007_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _008_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _009_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _010_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _011_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _012_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _013_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _014_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _015_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _016_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _017_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _018_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _019_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _020_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _021_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _022_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _023_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _024_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _025_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _026_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _027_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _028_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _029_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _030_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _031_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _032_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _033_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _034_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _035_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _036_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _037_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _038_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _039_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _040_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _041_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _042_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _043_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _044_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _045_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _046_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _047_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _048_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _049_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _050_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _051_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _052_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _053_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _054_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _055_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _056_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _057_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _058_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _059_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _060_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _061_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _062_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _063_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _064_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _065_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _066_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _067_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _068_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _069_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _070_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _071_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _072_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _073_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _074_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _075_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _076_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _077_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _078_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _079_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _080_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _081_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _082_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _083_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _084_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _085_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _086_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _087_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _088_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _089_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _090_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _091_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _092_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _093_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _094_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _095_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _096_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _097_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _098_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _099_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _100_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _101_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _102_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _103_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _104_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _105_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _106_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _107_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _108_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _109_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _110_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _111_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _112_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _113_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _114_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _115_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _116_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _117_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _118_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _119_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _120_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _121_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _122_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _123_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _124_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _125_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _126_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _127_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _128_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _129_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _130_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _131_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _132_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _133_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _134_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _135_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _136_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _137_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _138_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _139_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _140_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _141_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _142_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _143_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _144_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _145_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _146_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _147_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _148_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _149_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _150_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _151_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _152_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _153_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _154_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _155_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _156_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _157_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _158_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _159_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _160_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _161_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _162_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _163_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _164_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _165_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _166_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _167_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _168_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _169_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _170_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _171_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _172_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _173_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _174_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _175_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _176_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _177_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _178_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _179_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _180_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _181_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _182_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _183_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _184_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _185_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _186_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _187_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _188_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _189_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _190_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _191_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _192_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _193_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _194_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _195_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _196_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _197_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _198_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _199_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _200_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _201_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _202_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _203_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _204_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _205_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _206_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _207_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _208_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _209_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _210_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _211_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _212_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _213_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _214_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _215_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _216_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _217_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _218_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _219_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _220_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _221_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _222_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _223_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _224_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _225_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _226_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _227_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _228_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _229_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _230_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _231_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _232_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _233_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _234_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _235_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _236_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _237_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _238_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _239_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _240_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _241_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _242_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _243_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _244_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _245_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _246_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _247_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _248_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _249_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _250_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _251_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _252_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _253_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _254_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _255_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _256_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _257_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _258_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _259_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _260_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _261_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _262_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _263_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _264_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _265_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _266_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _267_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _268_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _269_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _270_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _271_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _272_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _273_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _274_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _275_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _276_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _277_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _278_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _279_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _280_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _281_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _282_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _283_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _284_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _285_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _286_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _287_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _288_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _289_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _290_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _291_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _292_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _293_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _294_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _295_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _296_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _297_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _298_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _299_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _300_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _301_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _302_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _303_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _304_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _305_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _306_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _307_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _308_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _309_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _310_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _311_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _312_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _313_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _314_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _315_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _316_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _317_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _318_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _319_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _320_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _321_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _322_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _323_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _324_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _325_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _326_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _327_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _328_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _329_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _330_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _331_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _332_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _333_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _334_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _335_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _336_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _337_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _338_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _339_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _340_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _341_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _342_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _343_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _344_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _345_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _346_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _347_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _348_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _349_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _350_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _351_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _352_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _353_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _354_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _355_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _356_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _357_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _358_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _359_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _360_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _361_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _362_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _363_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _364_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _365_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _366_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _367_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _368_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _369_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _370_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _371_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _372_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _373_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _374_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _375_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _376_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _377_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _378_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _379_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _380_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _381_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _382_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _383_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _384_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _385_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _386_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _387_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _388_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _389_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _390_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _391_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _392_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _393_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _394_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _395_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _396_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _397_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _398_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _399_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _400_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+END COMPONENTS
+PINS 3 ;
+    - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ;
+    - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL ;
+    - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL ;
+END PINS
+NETS 3 ;
+    - io_1 ( PIN io_1 ) + USE SIGNAL ;
+    - io_2 ( PIN io_2 ) + USE SIGNAL ;
+    - io_3 ( PIN io_3 ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/mpl/test/io_constraints3.ok b/src/mpl/test/io_constraints3.ok
new file mode 100644
index 00000000000..07a50199eed
--- /dev/null
+++ b/src/mpl/test/io_constraints3.ok
@@ -0,0 +1,23 @@
+[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: ./testcases/macro_only.lef, created 9 library cells
+[WARNING STA-1171] ./testcases/macro_only.lib line 32, default_max_transition is 0.0.
+[WARNING ORD-2011] LEF master DFF_X1 has no liberty cell.
+[INFO ODB-0128] Design: io_constraints1
+[INFO ODB-0252]     Updated 3 pins.
+[INFO ODB-0253]     Updated 401 components.
+Die Area: (0.00, 0.00) (150.00, 125.00),  Floorplan Area: (0.00, 0.00) (149.91, 124.60)
+	Number of std cell instances: 400
+	Area of std cell instances: 1808.79
+	Number of macros: 1
+	Area of macros: 10000.00
+	Halo width: 4.00
+	Halo height: 4.00
+	Area of macros with halos: 11664.00
+	Area of std cell instances + Area of macros: 11808.79
+	Floorplan area: 18678.79
+	Design Utilization: 0.63
+	Floorplan Utilization: 0.21
+	Manufacturing Grid: 10
+
+[WARNING MPL-0014] No Liberty data found for std cells. Continuing without dataflow.
+No differences found.
diff --git a/src/mpl/test/io_constraints3.tcl b/src/mpl/test/io_constraints3.tcl
new file mode 100644
index 00000000000..94cd6b9bc64
--- /dev/null
+++ b/src/mpl/test/io_constraints3.tcl
@@ -0,0 +1,23 @@
+# Test if pin access blockages are generated correctly for a case
+# with two blocked regions for pins.
+source "helpers.tcl"
+
+# We're not interested in the connections, so don't include the lib.
+read_lef "./Nangate45/Nangate45.lef"
+
+read_lef "./testcases/macro_only.lef"
+read_liberty "./testcases/macro_only.lib"
+
+read_verilog "./testcases/io_constraints1.v"
+link_design "io_constraints1"
+read_def "./testcases/io_constraints1.def" -floorplan_initialize
+
+exclude_io_pin_region -region right:10-125 -region top:10-150
+
+set_thread_count 0
+rtl_macro_placer -report_directory results/io_constraints3 -halo_width 4.0
+
+set def_file [make_result_file io_constraints3.def]
+write_def $def_file
+
+diff_files io_constraints3.defok $def_file
\ No newline at end of file
diff --git a/src/mpl/test/io_constraints4.defok b/src/mpl/test/io_constraints4.defok
new file mode 100644
index 00000000000..75142f8a994
--- /dev/null
+++ b/src/mpl/test/io_constraints4.defok
@@ -0,0 +1,529 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 300000 250000 ) ;
+ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 401 ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8010 ) FS ;
+    - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _004_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _005_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _006_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _007_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _008_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _009_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _010_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _011_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _012_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _013_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _014_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _015_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _016_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _017_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _018_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _019_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _020_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _021_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _022_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _023_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _024_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _025_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _026_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _027_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _028_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _029_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _030_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _031_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _032_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _033_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _034_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _035_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _036_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _037_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _038_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _039_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _040_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _041_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _042_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _043_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _044_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _045_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _046_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _047_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _048_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _049_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _050_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _051_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _052_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _053_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _054_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _055_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _056_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _057_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _058_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _059_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _060_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _061_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _062_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _063_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _064_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _065_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _066_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _067_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _068_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _069_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _070_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _071_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _072_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _073_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _074_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _075_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _076_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _077_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _078_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _079_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _080_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _081_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _082_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _083_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _084_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _085_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _086_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _087_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _088_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _089_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _090_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _091_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _092_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _093_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _094_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _095_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _096_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _097_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _098_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _099_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _100_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _101_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _102_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _103_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _104_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _105_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _106_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _107_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _108_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _109_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _110_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _111_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _112_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _113_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _114_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _115_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _116_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _117_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _118_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _119_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _120_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _121_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _122_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _123_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _124_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _125_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _126_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _127_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _128_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _129_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _130_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _131_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _132_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _133_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _134_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _135_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _136_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _137_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _138_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _139_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _140_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _141_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _142_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _143_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _144_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _145_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _146_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _147_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _148_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _149_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _150_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _151_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _152_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _153_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _154_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _155_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _156_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _157_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _158_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _159_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _160_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _161_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _162_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _163_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _164_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _165_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _166_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _167_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _168_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _169_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _170_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _171_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _172_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _173_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _174_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _175_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _176_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _177_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _178_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _179_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _180_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _181_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _182_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _183_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _184_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _185_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _186_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _187_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _188_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _189_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _190_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _191_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _192_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _193_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _194_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _195_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _196_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _197_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _198_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _199_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _200_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _201_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _202_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _203_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _204_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _205_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _206_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _207_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _208_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _209_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _210_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _211_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _212_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _213_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _214_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _215_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _216_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _217_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _218_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _219_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _220_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _221_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _222_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _223_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _224_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _225_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _226_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _227_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _228_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _229_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _230_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _231_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _232_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _233_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _234_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _235_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _236_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _237_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _238_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _239_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _240_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _241_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _242_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _243_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _244_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _245_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _246_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _247_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _248_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _249_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _250_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _251_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _252_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _253_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _254_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _255_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _256_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _257_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _258_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _259_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _260_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _261_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _262_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _263_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _264_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _265_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _266_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _267_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _268_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _269_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _270_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _271_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _272_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _273_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _274_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _275_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _276_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _277_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _278_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _279_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _280_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _281_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _282_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _283_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _284_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _285_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _286_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _287_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _288_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _289_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _290_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _291_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _292_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _293_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _294_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _295_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _296_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _297_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _298_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _299_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _300_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _301_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _302_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _303_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _304_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _305_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _306_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _307_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _308_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _309_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _310_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _311_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _312_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _313_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _314_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _315_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _316_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _317_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _318_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _319_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _320_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _321_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _322_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _323_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _324_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _325_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _326_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _327_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _328_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _329_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _330_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _331_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _332_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _333_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _334_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _335_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _336_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _337_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _338_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _339_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _340_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _341_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _342_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _343_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _344_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _345_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _346_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _347_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _348_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _349_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _350_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _351_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _352_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _353_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _354_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _355_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _356_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _357_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _358_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _359_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _360_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _361_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _362_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _363_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _364_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _365_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _366_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _367_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _368_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _369_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _370_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _371_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _372_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _373_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _374_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _375_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _376_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _377_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _378_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _379_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _380_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _381_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _382_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _383_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _384_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _385_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _386_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _387_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _388_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _389_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _390_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _391_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _392_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _393_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _394_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _395_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _396_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _397_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _398_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _399_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _400_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+END COMPONENTS
+PINS 3 ;
+    - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ;
+    - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL ;
+    - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL ;
+END PINS
+NETS 3 ;
+    - io_1 ( PIN io_1 ) + USE SIGNAL ;
+    - io_2 ( PIN io_2 ) + USE SIGNAL ;
+    - io_3 ( PIN io_3 ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/mpl/test/io_constraints4.ok b/src/mpl/test/io_constraints4.ok
new file mode 100644
index 00000000000..07a50199eed
--- /dev/null
+++ b/src/mpl/test/io_constraints4.ok
@@ -0,0 +1,23 @@
+[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: ./testcases/macro_only.lef, created 9 library cells
+[WARNING STA-1171] ./testcases/macro_only.lib line 32, default_max_transition is 0.0.
+[WARNING ORD-2011] LEF master DFF_X1 has no liberty cell.
+[INFO ODB-0128] Design: io_constraints1
+[INFO ODB-0252]     Updated 3 pins.
+[INFO ODB-0253]     Updated 401 components.
+Die Area: (0.00, 0.00) (150.00, 125.00),  Floorplan Area: (0.00, 0.00) (149.91, 124.60)
+	Number of std cell instances: 400
+	Area of std cell instances: 1808.79
+	Number of macros: 1
+	Area of macros: 10000.00
+	Halo width: 4.00
+	Halo height: 4.00
+	Area of macros with halos: 11664.00
+	Area of std cell instances + Area of macros: 11808.79
+	Floorplan area: 18678.79
+	Design Utilization: 0.63
+	Floorplan Utilization: 0.21
+	Manufacturing Grid: 10
+
+[WARNING MPL-0014] No Liberty data found for std cells. Continuing without dataflow.
+No differences found.
diff --git a/src/mpl/test/io_constraints4.tcl b/src/mpl/test/io_constraints4.tcl
new file mode 100644
index 00000000000..f9c10156d84
--- /dev/null
+++ b/src/mpl/test/io_constraints4.tcl
@@ -0,0 +1,26 @@
+# Test if pin access blockages are generated correctly for a case
+# with pins with different constraint regions. The region on the left
+# edge has more pins and should have a larger blockage.
+# The macro should be placed closer to the right edge.
+source "helpers.tcl"
+
+# We're not interested in the connections, so don't include the lib.
+read_lef "./Nangate45/Nangate45.lef"
+
+read_lef "./testcases/macro_only.lef"
+read_liberty "./testcases/macro_only.lib"
+
+read_verilog "./testcases/io_constraints1.v"
+link_design "io_constraints1"
+read_def "./testcases/io_constraints1.def" -floorplan_initialize
+
+set_io_pin_constraint -pin_names {io_1 io_2} -region left:70-90
+set_io_pin_constraint -pin_names {io_3} -region right:70-90
+
+set_thread_count 0
+rtl_macro_placer -report_directory results/io_constraints4 -halo_width 4.0
+
+set def_file [make_result_file io_constraints4.def]
+write_def $def_file
+
+diff_files io_constraints4.defok $def_file
\ No newline at end of file
diff --git a/src/mpl/test/io_constraints5.defok b/src/mpl/test/io_constraints5.defok
new file mode 100644
index 00000000000..d0c4895431b
--- /dev/null
+++ b/src/mpl/test/io_constraints5.defok
@@ -0,0 +1,529 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 300000 250000 ) ;
+ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 401 ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8010 ) FS ;
+    - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _004_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _005_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _006_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _007_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _008_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _009_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _010_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _011_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _012_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _013_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _014_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _015_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _016_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _017_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _018_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _019_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _020_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _021_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _022_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _023_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _024_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _025_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _026_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _027_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _028_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _029_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _030_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _031_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _032_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _033_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _034_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _035_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _036_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _037_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _038_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _039_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _040_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _041_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _042_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _043_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _044_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _045_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _046_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _047_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _048_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _049_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _050_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _051_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _052_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _053_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _054_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _055_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _056_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _057_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _058_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _059_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _060_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _061_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _062_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _063_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _064_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _065_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _066_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _067_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _068_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _069_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _070_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _071_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _072_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _073_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _074_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _075_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _076_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _077_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _078_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _079_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _080_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _081_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _082_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _083_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _084_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _085_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _086_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _087_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _088_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _089_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _090_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _091_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _092_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _093_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _094_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _095_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _096_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _097_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _098_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _099_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _100_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _101_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _102_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _103_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _104_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _105_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _106_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _107_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _108_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _109_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _110_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _111_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _112_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _113_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _114_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _115_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _116_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _117_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _118_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _119_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _120_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _121_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _122_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _123_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _124_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _125_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _126_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _127_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _128_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _129_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _130_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _131_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _132_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _133_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _134_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _135_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _136_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _137_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _138_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _139_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _140_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _141_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _142_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _143_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _144_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _145_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _146_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _147_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _148_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _149_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _150_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _151_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _152_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _153_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _154_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _155_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _156_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _157_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _158_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _159_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _160_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _161_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _162_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _163_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _164_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _165_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _166_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _167_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _168_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _169_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _170_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _171_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _172_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _173_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _174_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _175_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _176_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _177_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _178_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _179_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _180_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _181_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _182_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _183_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _184_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _185_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _186_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _187_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _188_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _189_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _190_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _191_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _192_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _193_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _194_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _195_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _196_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _197_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _198_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _199_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _200_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _201_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _202_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _203_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _204_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _205_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _206_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _207_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _208_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _209_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _210_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _211_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _212_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _213_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _214_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _215_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _216_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _217_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _218_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _219_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _220_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _221_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _222_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _223_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _224_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _225_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _226_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _227_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _228_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _229_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _230_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _231_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _232_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _233_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _234_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _235_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _236_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _237_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _238_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _239_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _240_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _241_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _242_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _243_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _244_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _245_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _246_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _247_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _248_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _249_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _250_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _251_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _252_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _253_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _254_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _255_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _256_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _257_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _258_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _259_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _260_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _261_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _262_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _263_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _264_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _265_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _266_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _267_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _268_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _269_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _270_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _271_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _272_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _273_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _274_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _275_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _276_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _277_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _278_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _279_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _280_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _281_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _282_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _283_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _284_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _285_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _286_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _287_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _288_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _289_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _290_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _291_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _292_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _293_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _294_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _295_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _296_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _297_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _298_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _299_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _300_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _301_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _302_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _303_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _304_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _305_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _306_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _307_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _308_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _309_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _310_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _311_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _312_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _313_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _314_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _315_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _316_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _317_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _318_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _319_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _320_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _321_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _322_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _323_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _324_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _325_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _326_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _327_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _328_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _329_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _330_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _331_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _332_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _333_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _334_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _335_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _336_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _337_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _338_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _339_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _340_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _341_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _342_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _343_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _344_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _345_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _346_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _347_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _348_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _349_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _350_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _351_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _352_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _353_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _354_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _355_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _356_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _357_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _358_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _359_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _360_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _361_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _362_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _363_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _364_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _365_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _366_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _367_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _368_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _369_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _370_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _371_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _372_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _373_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _374_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _375_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _376_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _377_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _378_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _379_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _380_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _381_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _382_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _383_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _384_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _385_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _386_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _387_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _388_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _389_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _390_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _391_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _392_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _393_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _394_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _395_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _396_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _397_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _398_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _399_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _400_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+END COMPONENTS
+PINS 3 ;
+    - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ;
+    - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL ;
+    - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL ;
+END PINS
+NETS 3 ;
+    - io_1 ( PIN io_1 ) + USE SIGNAL ;
+    - io_2 ( PIN io_2 ) + USE SIGNAL ;
+    - io_3 ( PIN io_3 ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/mpl/test/io_constraints5.ok b/src/mpl/test/io_constraints5.ok
new file mode 100644
index 00000000000..07a50199eed
--- /dev/null
+++ b/src/mpl/test/io_constraints5.ok
@@ -0,0 +1,23 @@
+[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: ./testcases/macro_only.lef, created 9 library cells
+[WARNING STA-1171] ./testcases/macro_only.lib line 32, default_max_transition is 0.0.
+[WARNING ORD-2011] LEF master DFF_X1 has no liberty cell.
+[INFO ODB-0128] Design: io_constraints1
+[INFO ODB-0252]     Updated 3 pins.
+[INFO ODB-0253]     Updated 401 components.
+Die Area: (0.00, 0.00) (150.00, 125.00),  Floorplan Area: (0.00, 0.00) (149.91, 124.60)
+	Number of std cell instances: 400
+	Area of std cell instances: 1808.79
+	Number of macros: 1
+	Area of macros: 10000.00
+	Halo width: 4.00
+	Halo height: 4.00
+	Area of macros with halos: 11664.00
+	Area of std cell instances + Area of macros: 11808.79
+	Floorplan area: 18678.79
+	Design Utilization: 0.63
+	Floorplan Utilization: 0.21
+	Manufacturing Grid: 10
+
+[WARNING MPL-0014] No Liberty data found for std cells. Continuing without dataflow.
+No differences found.
diff --git a/src/mpl/test/io_constraints5.tcl b/src/mpl/test/io_constraints5.tcl
new file mode 100644
index 00000000000..babed5b84fb
--- /dev/null
+++ b/src/mpl/test/io_constraints5.tcl
@@ -0,0 +1,25 @@
+# Test if pin access blockages are generated correctly for a case
+# with pins with different constraint regions. Both regions are
+# in the same boundary, but have different IO density.
+source "helpers.tcl"
+
+# We're not interested in the connections, so don't include the lib.
+read_lef "./Nangate45/Nangate45.lef"
+
+read_lef "./testcases/macro_only.lef"
+read_liberty "./testcases/macro_only.lib"
+
+read_verilog "./testcases/io_constraints1.v"
+link_design "io_constraints1"
+read_def "./testcases/io_constraints1.def" -floorplan_initialize
+
+set_io_pin_constraint -pin_names {io_1 io_2} -region right:70-90
+set_io_pin_constraint -pin_names {io_3} -region right:10-50
+
+set_thread_count 0
+rtl_macro_placer -report_directory results/io_constraints5 -halo_width 4.0
+
+set def_file [make_result_file io_constraints5.def]
+write_def $def_file
+
+diff_files io_constraints5.defok $def_file
\ No newline at end of file
diff --git a/src/mpl/test/io_constraints6.defok b/src/mpl/test/io_constraints6.defok
new file mode 100644
index 00000000000..8652f21d6b8
--- /dev/null
+++ b/src/mpl/test/io_constraints6.defok
@@ -0,0 +1,525 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 300000 250000 ) ;
+ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 401 ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8010 ) S ;
+    - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _004_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _005_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _006_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _007_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _008_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _009_ DFF_X1 + PLACED ( 254680 123252 ) N ;
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+    - _321_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _322_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _323_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _324_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _325_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _326_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _327_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _328_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _329_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _330_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _331_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _332_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _333_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _334_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _335_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _336_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _337_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _338_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _339_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _340_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _341_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _342_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _343_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _344_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _345_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _346_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _347_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _348_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _349_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _350_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _351_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _352_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _353_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _354_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _355_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _356_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _357_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _358_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _359_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _360_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _361_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _362_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _363_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _364_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _365_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _366_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _367_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _368_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _369_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _370_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _371_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _372_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _373_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _374_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _375_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _376_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _377_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _378_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _379_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _380_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _381_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _382_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _383_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _384_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _385_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _386_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _387_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _388_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _389_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _390_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _391_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _392_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _393_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _394_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _395_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _396_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _397_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _398_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _399_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+    - _400_ DFF_X1 + PLACED ( 254680 123252 ) N ;
+END COMPONENTS
+PINS 1 ;
+    - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ;
+END PINS
+NETS 1 ;
+    - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/mpl/test/io_constraints6.ok b/src/mpl/test/io_constraints6.ok
new file mode 100644
index 00000000000..b84e5c61fe4
--- /dev/null
+++ b/src/mpl/test/io_constraints6.ok
@@ -0,0 +1,21 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: testcases/macro_only.lef, created 9 library cells
+[INFO ODB-0128] Design: io_constraints1
+[INFO ODB-0130]     Created 1 pins.
+[INFO ODB-0131]     Created 401 components and 2402 component-terminals.
+[INFO ODB-0133]     Created 1 nets and 1 connections.
+Die Area: (0.00, 0.00) (150.00, 125.00),  Floorplan Area: (0.00, 0.00) (149.91, 124.60)
+	Number of std cell instances: 400
+	Area of std cell instances: 1808.79
+	Number of macros: 1
+	Area of macros: 10000.00
+	Halo width: 4.00
+	Halo height: 4.00
+	Area of macros with halos: 11664.00
+	Area of std cell instances + Area of macros: 11808.79
+	Floorplan area: 18678.79
+	Design Utilization: 0.63
+	Floorplan Utilization: 0.21
+	Manufacturing Grid: 10
+
+No differences found.
diff --git a/src/mpl/test/io_constraints6.tcl b/src/mpl/test/io_constraints6.tcl
new file mode 100644
index 00000000000..aa77f892fad
--- /dev/null
+++ b/src/mpl/test/io_constraints6.tcl
@@ -0,0 +1,21 @@
+# Test if the bundled nets inside annealing are correct for a block with
+# two blocked regions for pins and Macro -> IO connections.
+source "helpers.tcl"
+
+read_lef Nangate45/Nangate45.lef
+read_lef testcases/macro_only.lef
+
+read_liberty Nangate45/Nangate45_fast.lib
+
+read_def testcases/io_constraints6.def
+
+exclude_io_pin_region -region bottom:* -region left:* \
+                      -region top:40-150 -region right:40-125
+
+set_thread_count 0
+rtl_macro_placer -report_directory results/io_constraints6 -halo_width 4.0
+
+set def_file [make_result_file "io_constraints6.def"]
+write_def $def_file
+diff_files $def_file "io_constraints6.defok"
+
diff --git a/src/mpl/test/io_constraints7.defok b/src/mpl/test/io_constraints7.defok
new file mode 100644
index 00000000000..20b7f648129
--- /dev/null
+++ b/src/mpl/test/io_constraints7.defok
@@ -0,0 +1,525 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 300000 250000 ) ;
+ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 401 ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8150 ) N ;
+    - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _004_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _005_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _006_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _007_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _008_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _009_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _010_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _011_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _012_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _013_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _014_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _015_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _016_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _017_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _018_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _019_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _020_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _021_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _022_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _023_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _024_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _025_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _026_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _027_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _028_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _029_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _030_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _031_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _032_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _033_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _034_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _035_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _036_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _037_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _038_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _039_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _040_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _041_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _042_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _043_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _044_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _045_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _046_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _047_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _048_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _049_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _050_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _051_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _052_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _053_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _054_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _055_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _056_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _057_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _058_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _059_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _060_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _061_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _062_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _063_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _064_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _065_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _066_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _067_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _068_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _069_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _070_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _071_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _072_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _073_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _074_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _075_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _076_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _077_ DFF_X1 + PLACED ( 38680 123252 ) N ;
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+    - _080_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _081_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _082_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _083_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _084_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _085_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _086_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _087_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _088_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _089_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _090_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _091_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _092_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _093_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _094_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _095_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _096_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _097_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _098_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _099_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _100_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _101_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _102_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _103_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _104_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _105_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _106_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _107_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _108_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _109_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _110_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _111_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _112_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _113_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _114_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _115_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _116_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _117_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _118_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _119_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _120_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _121_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _122_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _123_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _124_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _125_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _126_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _127_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _128_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _129_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _130_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _131_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _132_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _133_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _134_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _135_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _136_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _137_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _138_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _139_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _140_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _141_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _142_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _143_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _144_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _145_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _146_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _147_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _148_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _149_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _150_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _151_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _152_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _153_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _154_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _155_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _156_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _157_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _158_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _159_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _160_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _161_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _162_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _163_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _164_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _165_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _166_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _167_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _168_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _169_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _170_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _171_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _172_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _173_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _174_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _175_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _176_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _177_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _178_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _179_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _180_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _181_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _182_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _183_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _184_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _185_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _186_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _187_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _188_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _189_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _190_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _191_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _192_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _193_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _194_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _195_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _196_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _197_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _198_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _199_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _200_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _201_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _202_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _203_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _204_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _205_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _206_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _207_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _208_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _209_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _210_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _211_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _212_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _213_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _214_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _215_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _216_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _217_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _218_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _219_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _220_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _221_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _222_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _223_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _224_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _225_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _226_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _227_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _228_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _229_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _230_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _231_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _232_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _233_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _234_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _235_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _236_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _237_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _238_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _239_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _240_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _241_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _242_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _243_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _244_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _245_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _246_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _247_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _248_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _249_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _250_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _251_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _252_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _253_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _254_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _255_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _256_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _257_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _258_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _259_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _260_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _261_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _262_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _263_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _264_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _265_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _266_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _267_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _268_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _269_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _270_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _271_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _272_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _273_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _274_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _275_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _276_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _277_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _278_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _279_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _280_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _281_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _282_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _283_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _284_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _285_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _286_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _287_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _288_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _289_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _290_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _291_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _292_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _293_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _294_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _295_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _296_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _297_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _298_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _299_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _300_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _301_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _302_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _303_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _304_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _305_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _306_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _307_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _308_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _309_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _310_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _311_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _312_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _313_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _314_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _315_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _316_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _317_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _318_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _319_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _320_ DFF_X1 + PLACED ( 38680 123252 ) N ;
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+    - _325_ DFF_X1 + PLACED ( 38680 123252 ) N ;
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+    - _328_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _329_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _330_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _331_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _332_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _333_ DFF_X1 + PLACED ( 38680 123252 ) N ;
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+    - _335_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _336_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _337_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _338_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _339_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _340_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _341_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _342_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _343_ DFF_X1 + PLACED ( 38680 123252 ) N ;
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+    - _345_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _346_ DFF_X1 + PLACED ( 38680 123252 ) N ;
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+    - _348_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _349_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _350_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _351_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _352_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _353_ DFF_X1 + PLACED ( 38680 123252 ) N ;
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+    - _356_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _357_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _358_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _359_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _360_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _361_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _362_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _363_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _364_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _365_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _366_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _367_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _368_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _369_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _370_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _371_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _372_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _373_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _374_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _375_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _376_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _377_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _378_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _379_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _380_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _381_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _382_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _383_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _384_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _385_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _386_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _387_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _388_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _389_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _390_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _391_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _392_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _393_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _394_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _395_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _396_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _397_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _398_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _399_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _400_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+END COMPONENTS
+PINS 1 ;
+    - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ;
+END PINS
+NETS 1 ;
+    - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/mpl/test/io_constraints7.ok b/src/mpl/test/io_constraints7.ok
new file mode 100644
index 00000000000..b84e5c61fe4
--- /dev/null
+++ b/src/mpl/test/io_constraints7.ok
@@ -0,0 +1,21 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: testcases/macro_only.lef, created 9 library cells
+[INFO ODB-0128] Design: io_constraints1
+[INFO ODB-0130]     Created 1 pins.
+[INFO ODB-0131]     Created 401 components and 2402 component-terminals.
+[INFO ODB-0133]     Created 1 nets and 1 connections.
+Die Area: (0.00, 0.00) (150.00, 125.00),  Floorplan Area: (0.00, 0.00) (149.91, 124.60)
+	Number of std cell instances: 400
+	Area of std cell instances: 1808.79
+	Number of macros: 1
+	Area of macros: 10000.00
+	Halo width: 4.00
+	Halo height: 4.00
+	Area of macros with halos: 11664.00
+	Area of std cell instances + Area of macros: 11808.79
+	Floorplan area: 18678.79
+	Design Utilization: 0.63
+	Floorplan Utilization: 0.21
+	Manufacturing Grid: 10
+
+No differences found.
diff --git a/src/mpl/test/io_constraints7.tcl b/src/mpl/test/io_constraints7.tcl
new file mode 100644
index 00000000000..23e511980bd
--- /dev/null
+++ b/src/mpl/test/io_constraints7.tcl
@@ -0,0 +1,20 @@
+# Test if the bundled nets inside annealing are correct for a block with
+# pins with different constraint regions and Macro -> IO connections.
+source "helpers.tcl"
+
+read_lef Nangate45/Nangate45.lef
+read_lef testcases/macro_only.lef
+
+read_liberty Nangate45/Nangate45_fast.lib
+
+read_def testcases/io_constraints6.def
+
+set_io_pin_constraint -pin_names {io_1} -region left:70-90
+
+set_thread_count 0
+rtl_macro_placer -report_directory results/io_constraints6 -halo_width 4.0
+
+set def_file [make_result_file "io_constraints7.def"]
+write_def $def_file
+diff_files $def_file "io_constraints7.defok"
+
diff --git a/src/mpl/test/io_constraints8.defok b/src/mpl/test/io_constraints8.defok
new file mode 100644
index 00000000000..5c4706fea61
--- /dev/null
+++ b/src/mpl/test/io_constraints8.defok
@@ -0,0 +1,525 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 300000 250000 ) ;
+ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 401 ;
+    - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8010 ) S ;
+    - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _004_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _005_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _006_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _007_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _008_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _009_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _010_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _011_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _012_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _013_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _014_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _015_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _016_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _017_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _018_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _019_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _020_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _021_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _022_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _023_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _024_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _025_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _026_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _027_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _028_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _029_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _030_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _031_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _032_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _033_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _034_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _035_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _036_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _037_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _038_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _039_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _040_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _041_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _042_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _043_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _044_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _045_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _046_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _047_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _048_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _049_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _050_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _051_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _052_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _053_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _054_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _055_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _056_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _057_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _058_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _059_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _060_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _061_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _062_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _063_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _064_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _065_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _066_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _067_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _068_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _069_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _070_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _071_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _072_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _073_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _074_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _075_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _076_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _077_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _078_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _079_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _080_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _081_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _082_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _083_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _084_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _085_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _086_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _087_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _088_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _089_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _090_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _091_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _092_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _093_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _094_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _095_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _096_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _097_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _098_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _099_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _100_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _101_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _102_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _103_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _104_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _105_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _106_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _107_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _108_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _109_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _110_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _111_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _112_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _113_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _114_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _115_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _116_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _117_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _118_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _119_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _120_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _121_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _122_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _123_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _124_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _125_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _126_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _127_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _128_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _129_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _130_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _131_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _132_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _133_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _134_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _135_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _136_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _137_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _138_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _139_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _140_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _141_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _142_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _143_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _144_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _145_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _146_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _147_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _148_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _149_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _150_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _151_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _152_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _153_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _154_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _155_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _156_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _157_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _158_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _159_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _160_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _161_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _162_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _163_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _164_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _165_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _166_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _167_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _168_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _169_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _170_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _171_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _172_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _173_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _174_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _175_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _176_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _177_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _178_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _179_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _180_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _181_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _182_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _183_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _184_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _185_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _186_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _187_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _188_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _189_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _190_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _191_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _192_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _193_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _194_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _195_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _196_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _197_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _198_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _199_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _200_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _201_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _202_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _203_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _204_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _205_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _206_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _207_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _208_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _209_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _210_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _211_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _212_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _213_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _214_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _215_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _216_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _217_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _218_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _219_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _220_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _221_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _222_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _223_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _224_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _225_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _226_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _227_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _228_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _229_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _230_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _231_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _232_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _233_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _234_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _235_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _236_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _237_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _238_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _239_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _240_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _241_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _242_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _243_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _244_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _245_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _246_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _247_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _248_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _249_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _250_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _251_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _252_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _253_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _254_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _255_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _256_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _257_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _258_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _259_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _260_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _261_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _262_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _263_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _264_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _265_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _266_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _267_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _268_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _269_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _270_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _271_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _272_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _273_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _274_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _275_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _276_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _277_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _278_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _279_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _280_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _281_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _282_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _283_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _284_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _285_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _286_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _287_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _288_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _289_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _290_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _291_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _292_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _293_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _294_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _295_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _296_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _297_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _298_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _299_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _300_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _301_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _302_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _303_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _304_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _305_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _306_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _307_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _308_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _309_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _310_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _311_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _312_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _313_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _314_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _315_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _316_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _317_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _318_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _319_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _320_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _321_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _322_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _323_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _324_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _325_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _326_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _327_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _328_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _329_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _330_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _331_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _332_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _333_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _334_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _335_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _336_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _337_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _338_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _339_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _340_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _341_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _342_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _343_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _344_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _345_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _346_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _347_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _348_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _349_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _350_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _351_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _352_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _353_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _354_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _355_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _356_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _357_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _358_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _359_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _360_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _361_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _362_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _363_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _364_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _365_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _366_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _367_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _368_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _369_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _370_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _371_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _372_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _373_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _374_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _375_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _376_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _377_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _378_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _379_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _380_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _381_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _382_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _383_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _384_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _385_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _386_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _387_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _388_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _389_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _390_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _391_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _392_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _393_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _394_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _395_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _396_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _397_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _398_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _399_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+    - _400_ DFF_X1 + PLACED ( 38680 123252 ) N ;
+END COMPONENTS
+PINS 1 ;
+    - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ;
+END PINS
+NETS 1 ;
+    - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/src/mpl/test/io_constraints8.ok b/src/mpl/test/io_constraints8.ok
new file mode 100644
index 00000000000..b84e5c61fe4
--- /dev/null
+++ b/src/mpl/test/io_constraints8.ok
@@ -0,0 +1,21 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0227] LEF file: testcases/macro_only.lef, created 9 library cells
+[INFO ODB-0128] Design: io_constraints1
+[INFO ODB-0130]     Created 1 pins.
+[INFO ODB-0131]     Created 401 components and 2402 component-terminals.
+[INFO ODB-0133]     Created 1 nets and 1 connections.
+Die Area: (0.00, 0.00) (150.00, 125.00),  Floorplan Area: (0.00, 0.00) (149.91, 124.60)
+	Number of std cell instances: 400
+	Area of std cell instances: 1808.79
+	Number of macros: 1
+	Area of macros: 10000.00
+	Halo width: 4.00
+	Halo height: 4.00
+	Area of macros with halos: 11664.00
+	Area of std cell instances + Area of macros: 11808.79
+	Floorplan area: 18678.79
+	Design Utilization: 0.63
+	Floorplan Utilization: 0.21
+	Manufacturing Grid: 10
+
+No differences found.
diff --git a/src/mpl/test/io_constraints8.tcl b/src/mpl/test/io_constraints8.tcl
new file mode 100644
index 00000000000..73961c1bbe8
--- /dev/null
+++ b/src/mpl/test/io_constraints8.tcl
@@ -0,0 +1,20 @@
+# Test if the available regions created based on the blocked regions for pins
+# are correctly generated when there are no constraints at all. Connections
+# are needed so we trigger the closest available region distance computation
+# inside the annealer.
+source "helpers.tcl"
+
+read_lef Nangate45/Nangate45.lef
+read_lef testcases/macro_only.lef
+
+read_liberty Nangate45/Nangate45_fast.lib
+
+read_def testcases/io_constraints6.def
+
+set_thread_count 0
+rtl_macro_placer -report_directory results/io_constraints8 -halo_width 4.0
+
+set def_file [make_result_file "io_constraints8.def"]
+write_def $def_file
+diff_files $def_file "io_constraints8.defok"
+
diff --git a/src/mpl/test/testcases/io_constraints6.def b/src/mpl/test/testcases/io_constraints6.def
new file mode 100644
index 00000000000..4b392f74b9f
--- /dev/null
+++ b/src/mpl/test/testcases/io_constraints6.def
@@ -0,0 +1,528 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN io_constraints1 ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 300000 250000 ) ;
+ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ;
+ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ;
+ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ;
+TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ;
+TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ;
+TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ;
+TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ;
+TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ;
+TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ;
+COMPONENTS 401 ;
+  - MACRO_1 HM_100x100_1x1 ;
+  - _001_ DFF_X1 ;
+  - _002_ DFF_X1 ;
+  - _003_ DFF_X1 ;
+  - _004_ DFF_X1 ;
+  - _005_ DFF_X1 ;
+  - _006_ DFF_X1 ;
+  - _007_ DFF_X1 ;
+  - _008_ DFF_X1 ;
+  - _009_ DFF_X1 ;
+  - _010_ DFF_X1 ;
+  - _011_ DFF_X1 ;
+  - _012_ DFF_X1 ;
+  - _013_ DFF_X1 ;
+  - _014_ DFF_X1 ;
+  - _015_ DFF_X1 ;
+  - _016_ DFF_X1 ;
+  - _017_ DFF_X1 ;
+  - _018_ DFF_X1 ;
+  - _019_ DFF_X1 ;
+  - _020_ DFF_X1 ;
+  - _021_ DFF_X1 ;
+  - _022_ DFF_X1 ;
+  - _023_ DFF_X1 ;
+  - _024_ DFF_X1 ;
+  - _025_ DFF_X1 ;
+  - _026_ DFF_X1 ;
+  - _027_ DFF_X1 ;
+  - _028_ DFF_X1 ;
+  - _029_ DFF_X1 ;
+  - _030_ DFF_X1 ;
+  - _031_ DFF_X1 ;
+  - _032_ DFF_X1 ;
+  - _033_ DFF_X1 ;
+  - _034_ DFF_X1 ;
+  - _035_ DFF_X1 ;
+  - _036_ DFF_X1 ;
+  - _037_ DFF_X1 ;
+  - _038_ DFF_X1 ;
+  - _039_ DFF_X1 ;
+  - _040_ DFF_X1 ;
+  - _041_ DFF_X1 ;
+  - _042_ DFF_X1 ;
+  - _043_ DFF_X1 ;
+  - _044_ DFF_X1 ;
+  - _045_ DFF_X1 ;
+  - _046_ DFF_X1 ;
+  - _047_ DFF_X1 ;
+  - _048_ DFF_X1 ;
+  - _049_ DFF_X1 ;
+  - _050_ DFF_X1 ;
+  - _051_ DFF_X1 ;
+  - _052_ DFF_X1 ;
+  - _053_ DFF_X1 ;
+  - _054_ DFF_X1 ;
+  - _055_ DFF_X1 ;
+  - _056_ DFF_X1 ;
+  - _057_ DFF_X1 ;
+  - _058_ DFF_X1 ;
+  - _059_ DFF_X1 ;
+  - _060_ DFF_X1 ;
+  - _061_ DFF_X1 ;
+  - _062_ DFF_X1 ;
+  - _063_ DFF_X1 ;
+  - _064_ DFF_X1 ;
+  - _065_ DFF_X1 ;
+  - _066_ DFF_X1 ;
+  - _067_ DFF_X1 ;
+  - _068_ DFF_X1 ;
+  - _069_ DFF_X1 ;
+  - _070_ DFF_X1 ;
+  - _071_ DFF_X1 ;
+  - _072_ DFF_X1 ;
+  - _073_ DFF_X1 ;
+  - _074_ DFF_X1 ;
+  - _075_ DFF_X1 ;
+  - _076_ DFF_X1 ;
+  - _077_ DFF_X1 ;
+  - _078_ DFF_X1 ;
+  - _079_ DFF_X1 ;
+  - _080_ DFF_X1 ;
+  - _081_ DFF_X1 ;
+  - _082_ DFF_X1 ;
+  - _083_ DFF_X1 ;
+  - _084_ DFF_X1 ;
+  - _085_ DFF_X1 ;
+  - _086_ DFF_X1 ;
+  - _087_ DFF_X1 ;
+  - _088_ DFF_X1 ;
+  - _089_ DFF_X1 ;
+  - _090_ DFF_X1 ;
+  - _091_ DFF_X1 ;
+  - _092_ DFF_X1 ;
+  - _093_ DFF_X1 ;
+  - _094_ DFF_X1 ;
+  - _095_ DFF_X1 ;
+  - _096_ DFF_X1 ;
+  - _097_ DFF_X1 ;
+  - _098_ DFF_X1 ;
+  - _099_ DFF_X1 ;
+  - _100_ DFF_X1 ;
+  - _101_ DFF_X1 ;
+  - _102_ DFF_X1 ;
+  - _103_ DFF_X1 ;
+  - _104_ DFF_X1 ;
+  - _105_ DFF_X1 ;
+  - _106_ DFF_X1 ;
+  - _107_ DFF_X1 ;
+  - _108_ DFF_X1 ;
+  - _109_ DFF_X1 ;
+  - _110_ DFF_X1 ;
+  - _111_ DFF_X1 ;
+  - _112_ DFF_X1 ;
+  - _113_ DFF_X1 ;
+  - _114_ DFF_X1 ;
+  - _115_ DFF_X1 ;
+  - _116_ DFF_X1 ;
+  - _117_ DFF_X1 ;
+  - _118_ DFF_X1 ;
+  - _119_ DFF_X1 ;
+  - _120_ DFF_X1 ;
+  - _121_ DFF_X1 ;
+  - _122_ DFF_X1 ;
+  - _123_ DFF_X1 ;
+  - _124_ DFF_X1 ;
+  - _125_ DFF_X1 ;
+  - _126_ DFF_X1 ;
+  - _127_ DFF_X1 ;
+  - _128_ DFF_X1 ;
+  - _129_ DFF_X1 ;
+  - _130_ DFF_X1 ;
+  - _131_ DFF_X1 ;
+  - _132_ DFF_X1 ;
+  - _133_ DFF_X1 ;
+  - _134_ DFF_X1 ;
+  - _135_ DFF_X1 ;
+  - _136_ DFF_X1 ;
+  - _137_ DFF_X1 ;
+  - _138_ DFF_X1 ;
+  - _139_ DFF_X1 ;
+  - _140_ DFF_X1 ;
+  - _141_ DFF_X1 ;
+  - _142_ DFF_X1 ;
+  - _143_ DFF_X1 ;
+  - _144_ DFF_X1 ;
+  - _145_ DFF_X1 ;
+  - _146_ DFF_X1 ;
+  - _147_ DFF_X1 ;
+  - _148_ DFF_X1 ;
+  - _149_ DFF_X1 ;
+  - _150_ DFF_X1 ;
+  - _151_ DFF_X1 ;
+  - _152_ DFF_X1 ;
+  - _153_ DFF_X1 ;
+  - _154_ DFF_X1 ;
+  - _155_ DFF_X1 ;
+  - _156_ DFF_X1 ;
+  - _157_ DFF_X1 ;
+  - _158_ DFF_X1 ;
+  - _159_ DFF_X1 ;
+  - _160_ DFF_X1 ;
+  - _161_ DFF_X1 ;
+  - _162_ DFF_X1 ;
+  - _163_ DFF_X1 ;
+  - _164_ DFF_X1 ;
+  - _165_ DFF_X1 ;
+  - _166_ DFF_X1 ;
+  - _167_ DFF_X1 ;
+  - _168_ DFF_X1 ;
+  - _169_ DFF_X1 ;
+  - _170_ DFF_X1 ;
+  - _171_ DFF_X1 ;
+  - _172_ DFF_X1 ;
+  - _173_ DFF_X1 ;
+  - _174_ DFF_X1 ;
+  - _175_ DFF_X1 ;
+  - _176_ DFF_X1 ;
+  - _177_ DFF_X1 ;
+  - _178_ DFF_X1 ;
+  - _179_ DFF_X1 ;
+  - _180_ DFF_X1 ;
+  - _181_ DFF_X1 ;
+  - _182_ DFF_X1 ;
+  - _183_ DFF_X1 ;
+  - _184_ DFF_X1 ;
+  - _185_ DFF_X1 ;
+  - _186_ DFF_X1 ;
+  - _187_ DFF_X1 ;
+  - _188_ DFF_X1 ;
+  - _189_ DFF_X1 ;
+  - _190_ DFF_X1 ;
+  - _191_ DFF_X1 ;
+  - _192_ DFF_X1 ;
+  - _193_ DFF_X1 ;
+  - _194_ DFF_X1 ;
+  - _195_ DFF_X1 ;
+  - _196_ DFF_X1 ;
+  - _197_ DFF_X1 ;
+  - _198_ DFF_X1 ;
+  - _199_ DFF_X1 ;
+  - _200_ DFF_X1 ;
+  - _201_ DFF_X1 ;
+  - _202_ DFF_X1 ;
+  - _203_ DFF_X1 ;
+  - _204_ DFF_X1 ;
+  - _205_ DFF_X1 ;
+  - _206_ DFF_X1 ;
+  - _207_ DFF_X1 ;
+  - _208_ DFF_X1 ;
+  - _209_ DFF_X1 ;
+  - _210_ DFF_X1 ;
+  - _211_ DFF_X1 ;
+  - _212_ DFF_X1 ;
+  - _213_ DFF_X1 ;
+  - _214_ DFF_X1 ;
+  - _215_ DFF_X1 ;
+  - _216_ DFF_X1 ;
+  - _217_ DFF_X1 ;
+  - _218_ DFF_X1 ;
+  - _219_ DFF_X1 ;
+  - _220_ DFF_X1 ;
+  - _221_ DFF_X1 ;
+  - _222_ DFF_X1 ;
+  - _223_ DFF_X1 ;
+  - _224_ DFF_X1 ;
+  - _225_ DFF_X1 ;
+  - _226_ DFF_X1 ;
+  - _227_ DFF_X1 ;
+  - _228_ DFF_X1 ;
+  - _229_ DFF_X1 ;
+  - _230_ DFF_X1 ;
+  - _231_ DFF_X1 ;
+  - _232_ DFF_X1 ;
+  - _233_ DFF_X1 ;
+  - _234_ DFF_X1 ;
+  - _235_ DFF_X1 ;
+  - _236_ DFF_X1 ;
+  - _237_ DFF_X1 ;
+  - _238_ DFF_X1 ;
+  - _239_ DFF_X1 ;
+  - _240_ DFF_X1 ;
+  - _241_ DFF_X1 ;
+  - _242_ DFF_X1 ;
+  - _243_ DFF_X1 ;
+  - _244_ DFF_X1 ;
+  - _245_ DFF_X1 ;
+  - _246_ DFF_X1 ;
+  - _247_ DFF_X1 ;
+  - _248_ DFF_X1 ;
+  - _249_ DFF_X1 ;
+  - _250_ DFF_X1 ;
+  - _251_ DFF_X1 ;
+  - _252_ DFF_X1 ;
+  - _253_ DFF_X1 ;
+  - _254_ DFF_X1 ;
+  - _255_ DFF_X1 ;
+  - _256_ DFF_X1 ;
+  - _257_ DFF_X1 ;
+  - _258_ DFF_X1 ;
+  - _259_ DFF_X1 ;
+  - _260_ DFF_X1 ;
+  - _261_ DFF_X1 ;
+  - _262_ DFF_X1 ;
+  - _263_ DFF_X1 ;
+  - _264_ DFF_X1 ;
+  - _265_ DFF_X1 ;
+  - _266_ DFF_X1 ;
+  - _267_ DFF_X1 ;
+  - _268_ DFF_X1 ;
+  - _269_ DFF_X1 ;
+  - _270_ DFF_X1 ;
+  - _271_ DFF_X1 ;
+  - _272_ DFF_X1 ;
+  - _273_ DFF_X1 ;
+  - _274_ DFF_X1 ;
+  - _275_ DFF_X1 ;
+  - _276_ DFF_X1 ;
+  - _277_ DFF_X1 ;
+  - _278_ DFF_X1 ;
+  - _279_ DFF_X1 ;
+  - _280_ DFF_X1 ;
+  - _281_ DFF_X1 ;
+  - _282_ DFF_X1 ;
+  - _283_ DFF_X1 ;
+  - _284_ DFF_X1 ;
+  - _285_ DFF_X1 ;
+  - _286_ DFF_X1 ;
+  - _287_ DFF_X1 ;
+  - _288_ DFF_X1 ;
+  - _289_ DFF_X1 ;
+  - _290_ DFF_X1 ;
+  - _291_ DFF_X1 ;
+  - _292_ DFF_X1 ;
+  - _293_ DFF_X1 ;
+  - _294_ DFF_X1 ;
+  - _295_ DFF_X1 ;
+  - _296_ DFF_X1 ;
+  - _297_ DFF_X1 ;
+  - _298_ DFF_X1 ;
+  - _299_ DFF_X1 ;
+  - _300_ DFF_X1 ;
+  - _301_ DFF_X1 ;
+  - _302_ DFF_X1 ;
+  - _303_ DFF_X1 ;
+  - _304_ DFF_X1 ;
+  - _305_ DFF_X1 ;
+  - _306_ DFF_X1 ;
+  - _307_ DFF_X1 ;
+  - _308_ DFF_X1 ;
+  - _309_ DFF_X1 ;
+  - _310_ DFF_X1 ;
+  - _311_ DFF_X1 ;
+  - _312_ DFF_X1 ;
+  - _313_ DFF_X1 ;
+  - _314_ DFF_X1 ;
+  - _315_ DFF_X1 ;
+  - _316_ DFF_X1 ;
+  - _317_ DFF_X1 ;
+  - _318_ DFF_X1 ;
+  - _319_ DFF_X1 ;
+  - _320_ DFF_X1 ;
+  - _321_ DFF_X1 ;
+  - _322_ DFF_X1 ;
+  - _323_ DFF_X1 ;
+  - _324_ DFF_X1 ;
+  - _325_ DFF_X1 ;
+  - _326_ DFF_X1 ;
+  - _327_ DFF_X1 ;
+  - _328_ DFF_X1 ;
+  - _329_ DFF_X1 ;
+  - _330_ DFF_X1 ;
+  - _331_ DFF_X1 ;
+  - _332_ DFF_X1 ;
+  - _333_ DFF_X1 ;
+  - _334_ DFF_X1 ;
+  - _335_ DFF_X1 ;
+  - _336_ DFF_X1 ;
+  - _337_ DFF_X1 ;
+  - _338_ DFF_X1 ;
+  - _339_ DFF_X1 ;
+  - _340_ DFF_X1 ;
+  - _341_ DFF_X1 ;
+  - _342_ DFF_X1 ;
+  - _343_ DFF_X1 ;
+  - _344_ DFF_X1 ;
+  - _345_ DFF_X1 ;
+  - _346_ DFF_X1 ;
+  - _347_ DFF_X1 ;
+  - _348_ DFF_X1 ;
+  - _349_ DFF_X1 ;
+  - _350_ DFF_X1 ;
+  - _351_ DFF_X1 ;
+  - _352_ DFF_X1 ;
+  - _353_ DFF_X1 ;
+  - _354_ DFF_X1 ;
+  - _355_ DFF_X1 ;
+  - _356_ DFF_X1 ;
+  - _357_ DFF_X1 ;
+  - _358_ DFF_X1 ;
+  - _359_ DFF_X1 ;
+  - _360_ DFF_X1 ;
+  - _361_ DFF_X1 ;
+  - _362_ DFF_X1 ;
+  - _363_ DFF_X1 ;
+  - _364_ DFF_X1 ;
+  - _365_ DFF_X1 ;
+  - _366_ DFF_X1 ;
+  - _367_ DFF_X1 ;
+  - _368_ DFF_X1 ;
+  - _369_ DFF_X1 ;
+  - _370_ DFF_X1 ;
+  - _371_ DFF_X1 ;
+  - _372_ DFF_X1 ;
+  - _373_ DFF_X1 ;
+  - _374_ DFF_X1 ;
+  - _375_ DFF_X1 ;
+  - _376_ DFF_X1 ;
+  - _377_ DFF_X1 ;
+  - _378_ DFF_X1 ;
+  - _379_ DFF_X1 ;
+  - _380_ DFF_X1 ;
+  - _381_ DFF_X1 ;
+  - _382_ DFF_X1 ;
+  - _383_ DFF_X1 ;
+  - _384_ DFF_X1 ;
+  - _385_ DFF_X1 ;
+  - _386_ DFF_X1 ;
+  - _387_ DFF_X1 ;
+  - _388_ DFF_X1 ;
+  - _389_ DFF_X1 ;
+  - _390_ DFF_X1 ;
+  - _391_ DFF_X1 ;
+  - _392_ DFF_X1 ;
+  - _393_ DFF_X1 ;
+  - _394_ DFF_X1 ;
+  - _395_ DFF_X1 ;
+  - _396_ DFF_X1 ;
+  - _397_ DFF_X1 ;
+  - _398_ DFF_X1 ;
+  - _399_ DFF_X1 ;
+  - _400_ DFF_X1 ;
+END COMPONENTS
+
+PINS 1 ;
+  - io_1 + NET io_1 ;
+END PINS
+
+NETS 1 ;
+  - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ;
+END NETS
+
+END DESIGN
\ No newline at end of file
diff --git a/src/odb/include/odb/geom.h b/src/odb/include/odb/geom.h
index 03c6217ede8..fe26f30182e 100644
--- a/src/odb/include/odb/geom.h
+++ b/src/odb/include/odb/geom.h
@@ -356,6 +356,9 @@ class Line
   Point pt0() const;
   Point pt1() const;
 
+  void addX(int value);
+  void addY(int value);
+
   friend dbIStream& operator>>(dbIStream& stream, Line& l);
   friend dbOStream& operator<<(dbOStream& stream, const Line& l);
 
@@ -988,6 +991,18 @@ inline Point Line::pt1() const
   return pt1_;
 }
 
+inline void Line::addX(int value)
+{
+  pt0_.setX(pt0_.getX() + value);
+  pt1_.setX(pt1_.getX() + value);
+}
+
+inline void Line::addY(int value)
+{
+  pt0_.setY(pt0_.getY() + value);
+  pt1_.setY(pt1_.getY() + value);
+}
+
 inline bool Line::operator==(const Line& r) const
 {
   return pt0_ == r.pt0_ && pt1_ == r.pt1_;