From a9863280e29e1003b875791d423c22594241c806 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Thu, 6 Feb 2025 15:37:17 -0300 Subject: [PATCH 01/34] mpl: 1. Use constraint regions' shapes for clusters of unplaced ios and pin access blockages 2. Add regression tests for different cases of blockage generation Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.cpp | 96 ++--- src/mpl/src/clusterEngine.cpp | 203 +++------- src/mpl/src/clusterEngine.h | 26 +- src/mpl/src/graphics.cpp | 82 ++-- src/mpl/src/hier_rtlmp.cpp | 341 ++++++++++++---- src/mpl/src/hier_rtlmp.h | 22 +- src/mpl/src/object.cpp | 19 +- src/mpl/src/object.h | 16 +- src/mpl/test/CMakeLists.txt | 3 + src/mpl/test/io_constraints1.tcl | 3 +- src/mpl/test/io_constraints2.tcl | 2 +- src/mpl/test/io_constraints3.defok | 538 +++++++++++++++++++++++++ src/mpl/test/io_constraints3.ok | 30 ++ src/mpl/test/io_constraints3.tcl | 26 ++ src/mpl/test/io_constraints4.defok | 538 +++++++++++++++++++++++++ src/mpl/test/io_constraints4.ok | 32 ++ src/mpl/test/io_constraints4.tcl | 28 ++ src/mpl/test/io_constraints5.defok | 538 +++++++++++++++++++++++++ src/mpl/test/io_constraints5.ok | 32 ++ src/mpl/test/io_constraints5.tcl | 28 ++ 20 files changed, 2270 insertions(+), 333 deletions(-) create mode 100644 src/mpl/test/io_constraints3.defok create mode 100644 src/mpl/test/io_constraints3.ok create mode 100644 src/mpl/test/io_constraints3.tcl create mode 100644 src/mpl/test/io_constraints4.defok create mode 100644 src/mpl/test/io_constraints4.ok create mode 100644 src/mpl/test/io_constraints4.tcl create mode 100644 src/mpl/test/io_constraints5.defok create mode 100644 src/mpl/test/io_constraints5.ok create mode 100644 src/mpl/test/io_constraints5.tcl diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 9e4de3a2f4c..21c41b5d49c 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -328,54 +328,54 @@ void SimulatedAnnealingCore::addBoundaryDistToWirelength( const T& io, const float net_weight) { - Cluster* io_cluster = io.getCluster(); - const Rect die = io_cluster->getBBox(); - const float die_hpwl = die.getWidth() + die.getHeight(); - - if (isOutsideTheOutline(macro)) { - wirelength_ += net_weight * die_hpwl; - return; - } - - const float x1 = macro.getPinX(); - const float y1 = macro.getPinY(); - - Boundary constraint_boundary = io_cluster->getConstraintBoundary(); - - if (constraint_boundary == NONE) { - float dist_to_left = die_hpwl; - if (!left_is_blocked_) { - dist_to_left = std::abs(x1 - die.xMin()); - } - - float dist_to_right = die_hpwl; - if (!right_is_blocked_) { - dist_to_right = std::abs(x1 - die.xMax()); - } - - float dist_to_bottom = die_hpwl; - if (!bottom_is_blocked_) { - dist_to_right = std::abs(y1 - die.yMin()); - } - - float dist_to_top = die_hpwl; - if (!top_is_blocked_) { - dist_to_top = std::abs(y1 - die.yMax()); - } - - wirelength_ - += net_weight - * std::min( - {dist_to_left, dist_to_right, dist_to_bottom, dist_to_top}); - } else if (constraint_boundary == Boundary::L - || constraint_boundary == Boundary::R) { - const float x2 = io.getPinX(); - wirelength_ += net_weight * std::abs(x2 - x1); - } else if (constraint_boundary == Boundary::T - || constraint_boundary == Boundary::B) { - const float y2 = io.getPinY(); - wirelength_ += net_weight * std::abs(y2 - y1); - } + // Cluster* io_cluster = io.getCluster(); + // const Rect die = io_cluster->getBBox(); + // const float die_hpwl = die.getWidth() + die.getHeight(); + + // if (isOutsideTheOutline(macro)) { + // wirelength_ += net_weight * die_hpwl; + // return; + // } + + // const float x1 = macro.getPinX(); + // const float y1 = macro.getPinY(); + + // Boundary constraint_boundary = io_cluster->getConstraintBoundary(); + + // if (constraint_boundary == NONE) { + // float dist_to_left = die_hpwl; + // if (!left_is_blocked_) { + // dist_to_left = std::abs(x1 - die.xMin()); + // } + + // float dist_to_right = die_hpwl; + // if (!right_is_blocked_) { + // dist_to_right = std::abs(x1 - die.xMax()); + // } + + // float dist_to_bottom = die_hpwl; + // if (!bottom_is_blocked_) { + // dist_to_right = std::abs(y1 - die.yMin()); + // } + + // float dist_to_top = die_hpwl; + // if (!top_is_blocked_) { + // dist_to_top = std::abs(y1 - die.yMax()); + // } + + // wirelength_ + // += net_weight + // * std::min( + // {dist_to_left, dist_to_right, dist_to_bottom, dist_to_top}); + // } else if (constraint_boundary == Boundary::L + // || constraint_boundary == Boundary::R) { + // const float x2 = io.getPinX(); + // wirelength_ += net_weight * std::abs(x2 - x1); + // } else if (constraint_boundary == Boundary::T + // || constraint_boundary == Boundary::B) { + // const float y2 = io.getPinY(); + // wirelength_ += net_weight * std::abs(y2 - y1); + // } } // We consider the macro outside the outline based on the location of diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 68cf6c86383..81afeeaac0a 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -69,7 +69,7 @@ void ClusteringEngine::run() createDataFlow(); createIOClusters(); - classifyBoundariesStateForIOs(); + setBlockedRegionsForPins(); if (design_metrics_->getNumStdCell() == 0) { logger_->warn(MPL, 25, "Design has no standard cells!"); @@ -363,10 +363,11 @@ void ClusteringEngine::setBaseThresholds() // 1. A Group of Unplaced Pins; // 2. An IO Pad. // -// For the former, we group IO pins with the same constraints based on: -// - If an IO pin has a constraint region in a certain boundary, -// it is constrained to that entire boundary; -// - If an IO pin has no constraints, it is constrained to all boundaries. +// For the former, we group IO pins that are constrainted to the same region; +// the shape of the cluster is the shape of the constraint region. +// If a pin has no constraints, we consider it constrained to all edges of +// the die area - for this case, the shape of the IO cluster is the shape of +// the die area. void ClusteringEngine::createIOClusters() { if (!tree_->maps.pad_to_bterm.empty()) { @@ -374,151 +375,73 @@ void ClusteringEngine::createIOClusters() return; } - // Boundary with constrained IOs -> cluster - std::map boundary_to_cluster; - const odb::Rect die = block_->getDieArea(); - - for (odb::dbBTerm* bterm : block_->getBTerms()) { - Boundary constraint_boundary = NONE; - - auto constraint_region = bterm->getConstraintRegion(); - if (constraint_region) { - constraint_boundary - = getConstraintBoundary(die, constraint_region.value()); - } - - const auto itr = boundary_to_cluster.find(constraint_boundary); - if (itr != boundary_to_cluster.end()) { - Cluster* io_cluster = itr->second; - tree_->maps.bterm_to_cluster_id[bterm] = io_cluster->getId(); - } else { - createIOCluster(die, constraint_boundary, boundary_to_cluster, bterm); - } - } - - if (tree_->maps.id_to_cluster.size() == 1) { + odb::dbSet bterms = block_->getBTerms(); + if (bterms.empty()) { logger_->warn(MPL, 26, "Design has no IO pins!"); tree_->has_io_clusters = false; } -} -Boundary ClusteringEngine::getConstraintBoundary( - const odb::Rect& die, - const odb::Rect& constraint_region) -{ - Boundary constraint_boundary = NONE; - if (constraint_region.xMin() == constraint_region.xMax()) { - if (constraint_region.xMin() == die.xMin()) { - constraint_boundary = L; - } else { - constraint_boundary = R; - } - } else { - if (constraint_region.yMin() == die.yMin()) { - constraint_boundary = B; + bool design_has_only_unconstrained_ios = true; + std::vector cluster_and_region_list; + + for (odb::dbBTerm* bterm : block_->getBTerms()) { + auto bterm_constraint = bterm->getConstraintRegion(); + if (bterm_constraint) { + design_has_only_unconstrained_ios = false; + createIOCluster(cluster_and_region_list, bterm, bterm_constraint.value()); } else { - constraint_boundary = T; + createIOCluster(cluster_and_region_list, bterm, block_->getDieArea()); } } - return constraint_boundary; -} - -void ClusteringEngine::createIOCluster( - const odb::Rect& die, - const Boundary constraint_boundary, - std::map& boundary_to_cluster, - odb::dbBTerm* bterm) -{ - auto cluster - = std::make_unique(id_, toString(constraint_boundary), logger_); - tree_->maps.bterm_to_cluster_id[bterm] = id_; - tree_->maps.id_to_cluster[id_++] = cluster.get(); - - boundary_to_cluster[constraint_boundary] = cluster.get(); - int x = die.xMin(), y = die.yMin(); - int width = die.dx(), height = die.dy(); - - if (constraint_boundary != NONE) { - setIOClusterDimensions(die, constraint_boundary, x, y, width, height); + if (design_has_only_unconstrained_ios) { + tree_->has_only_unconstrained_ios = true; } - - cluster->setAsClusterOfUnplacedIOPins( - std::pair(block_->dbuToMicrons(x), block_->dbuToMicrons(y)), - block_->dbuToMicrons(width), - block_->dbuToMicrons(height), - constraint_boundary); - tree_->root->addChild(std::move(cluster)); } -void ClusteringEngine::classifyBoundariesStateForIOs() -{ - const float blocked_boundary_threshold = 0.7; - std::map blockage_extension_map - = computeBlockageExtensionMap(); - - for (const auto [boundary, blockage_extension] : blockage_extension_map) { - if (blockage_extension >= blocked_boundary_threshold) { - tree_->blocked_boundaries.insert(boundary); - } else { - tree_->unblocked_boundaries.insert(boundary); +// Isso pode ter um nome melhor +void ClusteringEngine::createIOCluster( + std::vector& cluster_and_region_list, + odb::dbBTerm* bterm, + const odb::Rect& bterm_constraint) +{ + bool found_cluster_with_same_constraint = false; + for (const auto& [cluster, cluster_constraint] : cluster_and_region_list) { + if (bterm_constraint == cluster_constraint) { + tree_->maps.bterm_to_cluster_id[bterm] = cluster->getId(); + found_cluster_with_same_constraint = true; + break; } } -} - -// Computes how much blocked each boundary is for IOs base on PPL exclude -// contraints. -std::map ClusteringEngine::computeBlockageExtensionMap() -{ - std::map blockage_extension_map; - blockage_extension_map[L] = 0.0; - blockage_extension_map[R] = 0.0; - blockage_extension_map[B] = 0.0; - blockage_extension_map[T] = 0.0; + if (found_cluster_with_same_constraint) { + return; + } - const odb::Rect die = block_->getDieArea(); - for (const odb::Rect& blocked_region : block_->getBlockedRegionsForPins()) { - Boundary blocked_region_boundary - = getConstraintBoundary(die, blocked_region); - float blockage_extension = 0.0; + auto cluster = std::make_unique(id_, "", logger_); + if (bterm_constraint == block_->getDieArea()) { + cluster->setName("unconstrained_ios"); + cluster->setAsClusterOfUnconstrainedIOPins(); + } else { + cluster->setName("ios_" + std::to_string(id_)); + } - if (blocked_region_boundary == L || blocked_region_boundary == R) { - blockage_extension = blocked_region.dy() / static_cast(die.dy()); - } else if (blocked_region_boundary == B || blocked_region_boundary == T) { - blockage_extension = blocked_region.dx() / static_cast(die.dx()); - } + cluster->setAsClusterOfUnplacedIOPins( + {block_->dbuToMicrons(bterm_constraint.xMin()), + block_->dbuToMicrons(bterm_constraint.yMin())}, + block_->dbuToMicrons(bterm_constraint.dx()), + block_->dbuToMicrons(bterm_constraint.dy())); - blockage_extension_map[blocked_region_boundary] += blockage_extension; - } + cluster_and_region_list.push_back({cluster.get(), bterm_constraint}); - return blockage_extension_map; + tree_->maps.bterm_to_cluster_id[bterm] = id_; + tree_->maps.id_to_cluster[id_++] = cluster.get(); + tree_->root->addChild(std::move(cluster)); } -void ClusteringEngine::setIOClusterDimensions(const odb::Rect& die, - const Boundary boundary, - int& x, - int& y, - int& width, - int& height) +void ClusteringEngine::setBlockedRegionsForPins() { - if (boundary == L) { - x = die.xMin(); - y = die.yMin(); - width = 0; - } else if (boundary == T) { - x = die.xMin(); - y = die.yMax(); - height = 0; - } else if (boundary == R) { - x = die.xMax(); - y = die.yMin(); - width = 0; - } else { // Bottom - x = die.xMin(); - y = die.yMin(); - height = 0; - } + tree_->blocked_regions_for_pins = block_->getBlockedRegionsForPins(); } void ClusteringEngine::mapIOPinsAndPads() @@ -2223,14 +2146,7 @@ void ClusteringEngine::printPhysicalHierarchyTree(Cluster* parent, int level) parent->getClusterTypeString()); if (parent->isClusterOfUnplacedIOPins()) { - int number_of_pins = 0; - for (const auto [pin, cluster_id] : tree_->maps.bterm_to_cluster_id) { - if (cluster_id == parent->getId()) { - ++number_of_pins; - } - } - - line += fmt::format(" Pins: {}", number_of_pins); + line += fmt::format(" Pins: {}", getNumberOfIOs(parent)); } else if (!parent->isIOPadCluster()) { line += fmt::format(" {}, StdCells: {} ({} μ²), Macros: {} ({} μ²)", parent->getIsLeafString(), @@ -2288,4 +2204,17 @@ void ClusteringEngine::clearTempMacroClusterMapping( } } +int ClusteringEngine::getNumberOfIOs(Cluster* target) +{ + int number_of_ios = 0; + + for (const auto [pin, io_cluster_id] : tree_->maps.bterm_to_cluster_id) { + if (io_cluster_id == target->getId()) { + ++number_of_ios; + } + } + + return number_of_ios; +} + } // namespace mpl diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 722a135bad8..56634fb739b 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -113,8 +113,8 @@ struct PhysicalHierarchy std::unique_ptr root; PhysicalHierarchyMaps maps; - // This is set according to the ppl -exclude constraints - std::set blocked_boundaries; + std::vector blocked_regions_for_pins; + std::set blocked_boundaries; // TODO: remove std::set unblocked_boundaries; // For orientation improvement. float halo_width{0.0f}; @@ -124,6 +124,7 @@ struct PhysicalHierarchy Rect floorplan_shape; bool has_io_clusters{true}; + bool has_only_unconstrained_ios{false}; bool has_only_macros{false}; bool has_std_cells{true}; bool has_unfixed_macros{true}; @@ -174,10 +175,13 @@ class ClusteringEngine std::set& masters); void clearTempMacroClusterMapping(const UniqueClusterVector& macro_clusters); + int getNumberOfIOs(Cluster* target); + static bool isIgnoredInst(odb::dbInst* inst); private: using UniqueClusterQueue = std::queue>; + using IOClusterAndRegion = std::pair; void init(); Metrics* computeModuleMetrics(odb::dbModule* module); @@ -190,22 +194,12 @@ class ClusteringEngine void createRoot(); void setBaseThresholds(); void createIOClusters(); + void createIOCluster(std::vector& cluster_and_region_list, + odb::dbBTerm* bterm, + const odb::Rect& bterm_constraint); void createIOPadClusters(); void createIOPadCluster(odb::dbInst* pad, odb::dbBTerm* bterm); - void classifyBoundariesStateForIOs(); - std::map computeBlockageExtensionMap(); - Boundary getConstraintBoundary(const odb::Rect& die, - const odb::Rect& constraint_region); - void createIOCluster(const odb::Rect& die, - Boundary constraint_boundary, - std::map& boundary_to_cluster, - odb::dbBTerm* bterm); - void setIOClusterDimensions(const odb::Rect& die, - Boundary boundary, - int& x, - int& y, - int& width, - int& height); + void setBlockedRegionsForPins(); void mapIOPinsAndPads(); void treatEachMacroAsSingleCluster(); void incorporateNewCluster(std::unique_ptr cluster, Cluster* parent); diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp index e56621a5e8b..3ab5b6e1545 100644 --- a/src/mpl/src/graphics.cpp +++ b/src/mpl/src/graphics.cpp @@ -633,47 +633,47 @@ void Graphics::drawDistToIoConstraintBoundary(gui::Painter& painter, const T& macro, const T& io) { - if (isOutsideTheOutline(macro)) { - return; - } - - Cluster* io_cluster = io.getCluster(); - - const int x1 = block_->micronsToDbu(macro.getPinX()); - const int y1 = block_->micronsToDbu(macro.getPinY()); - odb::Point from(x1, y1); - - odb::Point to; - Boundary constraint_boundary = io_cluster->getConstraintBoundary(); - - if (constraint_boundary == Boundary::L - || constraint_boundary == Boundary::R) { - const int x2 = block_->micronsToDbu(io.getPinX()); - const int y2 = block_->micronsToDbu(macro.getPinY()); - to.setX(x2); - to.setY(y2); - } else if (constraint_boundary == Boundary::B - || constraint_boundary == Boundary::T) { - const int x2 = block_->micronsToDbu(macro.getPinX()); - const int y2 = block_->micronsToDbu(io.getPinY()); - to.setX(x2); - to.setY(y2); - } else { - // For NONE, the shape of the io cluster is the die area. - const Rect die = io_cluster->getBBox(); - Boundary closest_unblocked_boundary - = getClosestUnblockedBoundary(macro, die); - - to = getClosestBoundaryPoint(macro, die, closest_unblocked_boundary); - } - - addOutlineOffsetToLine(from, to); - - painter.drawLine(from, to); - painter.drawString(to.getX(), - to.getY(), - gui::Painter::CENTER, - toString(constraint_boundary)); + // if (isOutsideTheOutline(macro)) { + // return; + // } + + // Cluster* io_cluster = io.getCluster(); + + // const int x1 = block_->micronsToDbu(macro.getPinX()); + // const int y1 = block_->micronsToDbu(macro.getPinY()); + // odb::Point from(x1, y1); + + // odb::Point to; + // Boundary constraint_boundary = io_cluster->getConstraintBoundary(); + + // if (constraint_boundary == Boundary::L + // || constraint_boundary == Boundary::R) { + // const int x2 = block_->micronsToDbu(io.getPinX()); + // const int y2 = block_->micronsToDbu(macro.getPinY()); + // to.setX(x2); + // to.setY(y2); + // } else if (constraint_boundary == Boundary::B + // || constraint_boundary == Boundary::T) { + // const int x2 = block_->micronsToDbu(macro.getPinX()); + // const int y2 = block_->micronsToDbu(io.getPinY()); + // to.setX(x2); + // to.setY(y2); + // } else { + // // For NONE, the shape of the io cluster is the die area. + // const Rect die = io_cluster->getBBox(); + // Boundary closest_unblocked_boundary + // = getClosestUnblockedBoundary(macro, die); + + // to = getClosestBoundaryPoint(macro, die, closest_unblocked_boundary); + // } + + // addOutlineOffsetToLine(from, to); + + // painter.drawLine(from, to); + // painter.drawString(to.getX(), + // to.getY(), + // gui::Painter::CENTER, + // toString(constraint_boundary)); } template diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 85c3d3b35ad..fca800a7f46 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -342,7 +342,7 @@ void HierRTLMP::runCoarseShaping() calculateChildrenTilings(tree_->root.get()); - setPinAccessBlockages(); + createPinAccessBlockages(); setPlacementBlockages(); } @@ -884,113 +884,231 @@ void HierRTLMP::setTightPackingTilings(Cluster* macro_array) macro_array->setMacroTilings(tight_packing_tilings); } -void HierRTLMP::setPinAccessBlockages() +void HierRTLMP::createPinAccessBlockages() { if (!tree_->maps.pad_to_bterm.empty()) { return; } - std::vector clusters_of_unplaced_io_pins - = getClustersOfUnplacedIOPins(); - const Rect die = dbuToMicrons(block_->getDieArea()); - - const float depth - = computePinAccessBlockagesDepth(clusters_of_unplaced_io_pins, die); - - for (Cluster* cluster_of_unplaced_io_pins : clusters_of_unplaced_io_pins) { - Boundary constraint_boundary - = cluster_of_unplaced_io_pins->getConstraintBoundary(); - if (constraint_boundary != NONE) { - createPinAccessBlockage(constraint_boundary, depth, die); - } + if (tree_->has_only_unconstrained_ios) { + createBlockagesForAvailableRegions(); + } else { + createBlockagesForConstraintRegions(); } +} - if (boundary_to_io_blockage_.empty()) { +void HierRTLMP::createBlockagesForAvailableRegions() +{ + if (tree_->blocked_regions_for_pins.empty()) { // If there are no constraints at all, give freedom to SA so it // doesn't have to deal with pin access blockages in all boundaries. // This will help SA not relying on extreme utilizations to // converge for designs such as sky130hd/uW. - if (tree_->blocked_boundaries.empty()) { - return; - } + return; + } - // There are only -exclude constraints, so we create pin access - // blockages based on the boundaries that are not blocked. - if (tree_->blocked_boundaries.find(L) == tree_->blocked_boundaries.end()) { - createPinAccessBlockage(L, depth, die); - } + BoundaryToRegionsMap boundary_to_blocked_regions + = getBoundaryToBlockedRegionsMap(); + std::vector available_regions + = computeAvailableRegions(boundary_to_blocked_regions); - if (tree_->blocked_boundaries.find(R) == tree_->blocked_boundaries.end()) { - createPinAccessBlockage(R, depth, die); - } + float io_span = 0.0f; + for (const odb::Rect& available_region : available_regions) { + const Rect region = dbuToMicrons(available_region); + io_span += region.getPerimeter() / 2; + } + + const float depth = computePinAccessBaseDepth(io_span); + + for (const odb::Rect& available_region : available_regions) { + createPinAccessBlockage(dbuToMicrons(available_region), depth); + } +} + +void HierRTLMP::createBlockagesForConstraintRegions() +{ + float io_span = 0.0f; + std::vector clusters_of_unplaced_ios + = getClustersOfUnplacedIOPins(); - if (tree_->blocked_boundaries.find(B) == tree_->blocked_boundaries.end()) { - createPinAccessBlockage(B, depth, die); + for (Cluster* cluster_of_unplaced_ios : clusters_of_unplaced_ios) { + if (cluster_of_unplaced_ios->isClusterOfUnconstrainedIOPins()) { + continue; } - if (tree_->blocked_boundaries.find(T) == tree_->blocked_boundaries.end()) { - createPinAccessBlockage(T, depth, die); + // Reminder: the region rect is always a line for a cluster + // of constrained pins. + const Rect region = cluster_of_unplaced_ios->getBBox(); + io_span += region.getPerimeter() / 2; + } + + const float base_depth = computePinAccessBaseDepth(io_span); + const int total_ios = static_cast(block_->getBTerms().size()); + + for (Cluster* cluster_of_unplaced_ios : clusters_of_unplaced_ios) { + if (cluster_of_unplaced_ios->isClusterOfUnconstrainedIOPins()) { + continue; } + + const float cluster_number_of_ios = static_cast( + clustering_engine_->getNumberOfIOs(cluster_of_unplaced_ios)); + + const float io_density_factor = cluster_number_of_ios / total_ios; + const float depth = base_depth * io_density_factor; + + createPinAccessBlockage(cluster_of_unplaced_ios->getBBox(), depth); } } -void HierRTLMP::createPinAccessBlockage(Boundary constraint_boundary, - const float depth, - const Rect& die) +BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap() { - Rect blockage = die; - if (constraint_boundary == L) { - blockage.setXMax(blockage.xMin() + depth); - } else if (constraint_boundary == T) { - blockage.setYMin(blockage.yMax() - depth); - } else if (constraint_boundary == R) { - blockage.setXMin(blockage.xMax() - depth); - } else { // Bottom - blockage.setYMax(blockage.yMin() + depth); + BoundaryToRegionsMap boundary_to_blocked_regions; + std::queue blocked_regions; + + boundary_to_blocked_regions[L] = blocked_regions; + boundary_to_blocked_regions[R] = blocked_regions; + boundary_to_blocked_regions[B] = blocked_regions; + boundary_to_blocked_regions[T] = blocked_regions; + + for (const odb::Rect& blocked_region : tree_->blocked_regions_for_pins) { + Boundary boundary = getRegionBoundary(blocked_region); + boundary_to_blocked_regions.at(boundary).push(blocked_region); + + debugPrint(logger_, + MPL, + "coarse_shaping", + 1, + "Found blocked region {} in {} boundary.", + blocked_region, + toString(boundary)); } - boundary_to_io_blockage_[constraint_boundary] = blockage; - macro_blockages_.push_back(blockage); + return boundary_to_blocked_regions; } -std::vector HierRTLMP::getClustersOfUnplacedIOPins() +std::vector HierRTLMP::computeAvailableRegions( + BoundaryToRegionsMap& boundary_to_blocked_regions) { - std::vector clusters_of_unplaced_io_pins; + std::vector available_regions; - for (const auto& child : tree_->root->getChildren()) { - if (child->isClusterOfUnplacedIOPins()) { - clusters_of_unplaced_io_pins.push_back(child.get()); + for (auto& [boundary, blocked_regions] : boundary_to_blocked_regions) { + // The initial available region is the entire edge of the die area. + std::vector boundary_available_regions = {getRect(boundary)}; + + while (!blocked_regions.empty()) { + odb::Rect blocked_region = blocked_regions.front(); + blocked_regions.pop(); + + std::vector new_boundary_available_regions; + for (const odb::Rect& boundary_available_region : + boundary_available_regions) { + if (!boundary_available_region.contains(blocked_region)) { + new_boundary_available_regions.push_back(boundary_available_region); + continue; + } + + std::vector subtraction_result + = subtractOverlapRegion(boundary_available_region, blocked_region); + new_boundary_available_regions.insert( + new_boundary_available_regions.end(), + subtraction_result.begin(), + subtraction_result.end()); + } + + boundary_available_regions = new_boundary_available_regions; } + + available_regions.insert(available_regions.end(), + boundary_available_regions.begin(), + boundary_available_regions.end()); } - return clusters_of_unplaced_io_pins; + return available_regions; } -// The depth of pin access blockages is computed based on: -// 1) Amount of std cell area in the design. -// 2) Extension of the IO clusters across the design's boundaries. -float HierRTLMP::computePinAccessBlockagesDepth( - const std::vector& io_clusters, - const Rect& die) +void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, + const float depth) { - float io_clusters_extension = 0.0; + Rect blockage = micron_region; + Boundary region_boundary = getRegionBoundary(micronsToDbu(micron_region)); - for (Cluster* io_cluster : io_clusters) { - if (io_cluster->getConstraintBoundary() == NONE) { - const Rect die = io_cluster->getBBox(); - io_clusters_extension = die.getPerimeter(); + debugPrint( + logger_, + MPL, + "coarse_shaping", + 1, + "Creating pin access blockage in {} -> Region shape = {} , Depth = {}", + toString(region_boundary), + micronsToDbu(micron_region), + depth); + + switch (region_boundary) { + case L: { + blockage.setXMax(blockage.xMin() + depth); + break; + } + case R: { + blockage.setXMin(blockage.xMax() - depth); + break; + } + case B: { + blockage.setYMax(blockage.yMin() + depth); + break; + } + case T: { + blockage.setYMin(blockage.yMax() - depth); break; } + case NONE: { + logger_->critical(MPL, + 48, + "Attempting to create pin access blockage for cluster " + "of unconstrained IOs!"); + } + } + + macro_blockages_.push_back(blockage); + io_blockages_.push_back(blockage); +} - Boundary constraint_boundary = io_cluster->getConstraintBoundary(); +// Isso aqui é melhor ser uma API do Cluster pq vai ser util no SA +Boundary HierRTLMP::getRegionBoundary(const odb::Rect& constraint_region) +{ + const odb::Rect& die = block_->getDieArea(); + Boundary constraint_boundary = NONE; + if (constraint_region.dx() == 0) { + if (constraint_region.xMin() == die.xMin()) { + constraint_boundary = L; + } else { + constraint_boundary = R; + } + } else { + if (constraint_region.yMin() == die.yMin()) { + constraint_boundary = B; + } else { + constraint_boundary = T; + } + } + return constraint_boundary; +} - if (constraint_boundary == L || constraint_boundary == R) { - io_clusters_extension += die.getWidth(); - } else { // Bottom or Top - io_clusters_extension += die.getHeight(); +std::vector HierRTLMP::getClustersOfUnplacedIOPins() +{ + std::vector clusters_of_unplaced_io_pins; + for (const auto& child : tree_->root->getChildren()) { + if (child->isClusterOfUnplacedIOPins()) { + clusters_of_unplaced_io_pins.push_back(child.get()); } } + return clusters_of_unplaced_io_pins; +} +// The base depth of pin access blockages is computed based on: +// 1) Amount of std cell area in the design. +// 2) Extension of IO span. +// 3) Macro dominance quadratic factor. +float HierRTLMP::computePinAccessBaseDepth(const float io_span) +{ float std_cell_area = 0.0; for (auto& cluster : tree_->root->getChildren()) { if (cluster->getClusterType() == StdCellCluster) { @@ -1009,17 +1127,17 @@ float HierRTLMP::computePinAccessBlockagesDepth( const float macro_dominance_factor = tree_->macro_with_halo_area / (tree_->root->getWidth() * tree_->root->getHeight()); - const float depth = (std_cell_area / io_clusters_extension) - * std::pow((1 - macro_dominance_factor), 2); + const float base_depth + = (std_cell_area / io_span) * std::pow((1 - macro_dominance_factor), 2); debugPrint(logger_, MPL, "coarse_shaping", 1, - "Pin access blockages depth = {}", - depth); + "Base pin access depth: {} μm", + base_depth); - return depth; + return base_depth; } void HierRTLMP::setPlacementBlockages() @@ -3057,6 +3175,85 @@ Rect HierRTLMP::dbuToMicrons(const odb::Rect& dbu_rect) block_->dbuToMicrons(dbu_rect.yMax())); } +// Example for a vertical region: +// Base - Overlay = Result +// | | +// | | "b" +// | | +// | | +// | | +// | | +// | | +// | | "a" +// | | +std::vector HierRTLMP::subtractOverlapRegion( + const odb::Rect& base, + const odb::Rect& overlay) +{ + Boundary base_boundary = getRegionBoundary(base); + + if (base_boundary != getRegionBoundary(overlay)) { + logger_->critical( + MPL, 46, "Attempting to subtract regions from different boundaries."); + } + + std::vector result; + odb::Rect a = base; + odb::Rect b = base; + + if (isHorizontal(base_boundary)) { + a.set_yhi(overlay.yMin()); + b.set_ylo(overlay.yMax()); + } else { + a.set_xhi(overlay.xMin()); + b.set_xlo(overlay.xMax()); + } + + if (a.dx() != 0 || a.dy() != 0) { + result.push_back(a); + } + + if (b.dx() != 0 || b.dy() != 0) { + result.push_back(b); + } + + return result; +} + +bool HierRTLMP::isHorizontal(Boundary boundary) +{ + return boundary == L || boundary == R; +} + +odb::Rect HierRTLMP::getRect(Boundary boundary) +{ + odb::Rect boundary_rect = block_->getDieArea(); + + switch (boundary) { + case NONE: + break; + case L: { + boundary_rect.set_xhi(boundary_rect.xMin()); + break; + } + case R: { + boundary_rect.set_xlo(boundary_rect.xMax()); + break; + } + case T: { + boundary_rect.set_ylo(boundary_rect.yMax()); + break; + } + case B: { + boundary_rect.set_yhi(boundary_rect.yMin()); + break; + } + } + + return boundary_rect; +} + + template void HierRTLMP::printPlacementResult(Cluster* parent, const Rect& outline, diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index fcf8aefb836..1375e6415fe 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -87,6 +87,7 @@ struct LayerParameters using LayersWithPinsMap = std::map; using LayerParametersMap = std::map; +using BoundaryToRegionsMap = std::map>; // Hierarchical RTL-MP // Support Multi-Level Clustering. @@ -177,13 +178,16 @@ class HierRTLMP void calculateChildrenTilings(Cluster* parent); void calculateMacroTilings(Cluster* cluster); void setTightPackingTilings(Cluster* macro_array); - void setPinAccessBlockages(); + void createPinAccessBlockages(); std::vector getClustersOfUnplacedIOPins(); - float computePinAccessBlockagesDepth(const std::vector& io_clusters, - const Rect& die); - void createPinAccessBlockage(Boundary constraint_boundary, - float depth, - const Rect& die); + void createPinAccessBlockage(const Rect& micron_region, const float depth); + float computePinAccessBaseDepth(const float io_span); + BoundaryToRegionsMap getBoundaryToBlockedRegionsMap(); + std::vector computeAvailableRegions( + BoundaryToRegionsMap& boundary_to_blocked_regions); + void createBlockagesForAvailableRegions(); + void createBlockagesForConstraintRegions(); + Boundary getRegionBoundary(const odb::Rect& constraint_region); void setPlacementBlockages(); // Fine Shaping @@ -251,6 +255,11 @@ class HierRTLMP odb::Rect micronsToDbu(const Rect& micron_rect); Rect dbuToMicrons(const odb::Rect& dbu_rect); + odb::Rect getRect(Boundary boundary); + bool isHorizontal(Boundary boundary); + std::vector subtractOverlapRegion(const odb::Rect& base, + const odb::Rect& overlay); + // For debugging template void printPlacementResult(Cluster* parent, @@ -315,6 +324,7 @@ class HierRTLMP std::map guides_; // Macro -> Guidance Region std::vector placement_blockages_; std::vector macro_blockages_; + std::vector io_blockages_; std::map boundary_to_io_blockage_; // Fast SA hyperparameter diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp index 7035f662877..6e0fbaf950f 100644 --- a/src/mpl/src/object.cpp +++ b/src/mpl/src/object.cpp @@ -333,11 +333,9 @@ void Cluster::copyInstances(const Cluster& cluster) void Cluster::setAsClusterOfUnplacedIOPins(const std::pair& pos, const float width, - const float height, - const Boundary constraint_boundary) + const float height) { is_cluster_of_unplaced_io_pins_ = true; - constraint_boundary_ = constraint_boundary; soft_macro_ = std::make_unique(pos, name_, width, height, this); } @@ -354,6 +352,21 @@ bool Cluster::isIOCluster() const return is_cluster_of_unplaced_io_pins_ || is_io_pad_cluster_; } +void Cluster::setAsClusterOfUnconstrainedIOPins() +{ + is_cluster_of_unconstrained_io_pins_ = true; +} + +bool Cluster::isClusterOfUnconstrainedIOPins() const +{ + return is_cluster_of_unconstrained_io_pins_; +} + +bool Cluster::isClusterOfUnplacedIOPins() const +{ + return is_cluster_of_unplaced_io_pins_; +} + void Cluster::setAsArrayOfInterconnectedMacros() { is_array_of_interconnected_macros = true; diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index 95544e63b56..78ec5fa024b 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -202,15 +202,14 @@ class Cluster bool isIOCluster() const; - bool isClusterOfUnplacedIOPins() const - { - return is_cluster_of_unplaced_io_pins_; - } + // The cluster of unplaced IOs with unconstrained pins. + void setAsClusterOfUnconstrainedIOPins(); + bool isClusterOfUnconstrainedIOPins() const; + + bool isClusterOfUnplacedIOPins() const; void setAsClusterOfUnplacedIOPins(const std::pair& pos, float width, - float height, - Boundary constraint_boundary); - Boundary getConstraintBoundary() const { return constraint_boundary_; } + float height); bool isIOPadCluster() const { return is_io_pad_cluster_; } void setAsIOPadCluster(const std::pair& pos, @@ -298,9 +297,10 @@ class Cluster // all the macros in the cluster std::vector hard_macros_; + int io_pins_count_{0}; bool is_cluster_of_unplaced_io_pins_{false}; + bool is_cluster_of_unconstrained_io_pins_{false}; bool is_io_pad_cluster_{false}; - Boundary constraint_boundary_ = NONE; bool is_array_of_interconnected_macros = false; diff --git a/src/mpl/test/CMakeLists.txt b/src/mpl/test/CMakeLists.txt index cc0427c9313..0a97aa50ed1 100644 --- a/src/mpl/test/CMakeLists.txt +++ b/src/mpl/test/CMakeLists.txt @@ -7,6 +7,9 @@ or_integration_tests( guides2 io_constraints1 io_constraints2 + io_constraints3 + io_constraints4 + io_constraints5 io_pads1 orientation_improve1 orientation_improve2 diff --git a/src/mpl/test/io_constraints1.tcl b/src/mpl/test/io_constraints1.tcl index b5f31c91ba0..a2a8cd97936 100644 --- a/src/mpl/test/io_constraints1.tcl +++ b/src/mpl/test/io_constraints1.tcl @@ -12,8 +12,9 @@ read_verilog "./testcases/io_constraints1.v" link_design "io_constraints1" read_def "./testcases/io_constraints1.def" -floorplan_initialize -# Run random PPL to incorporate the constraints into ODB set_io_pin_constraint -direction INPUT -region left:* + +# Run random PPL to incorporate the constraints into ODB place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 set_thread_count 0 diff --git a/src/mpl/test/io_constraints2.tcl b/src/mpl/test/io_constraints2.tcl index 17e7fbe7cb5..e6ef2065006 100644 --- a/src/mpl/test/io_constraints2.tcl +++ b/src/mpl/test/io_constraints2.tcl @@ -1,5 +1,5 @@ # Test if pin access blockage is generated correctly for a case -# with all boundaries blocked except one. +# with all boundaries entirely blocked except one. source "helpers.tcl" # We're not interested in the connections, so don't include the lib. diff --git a/src/mpl/test/io_constraints3.defok b/src/mpl/test/io_constraints3.defok new file mode 100644 index 00000000000..aeac6e85033 --- /dev/null +++ b/src/mpl/test/io_constraints3.defok @@ -0,0 +1,538 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN io_constraints1 ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 300000 250000 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; +COMPONENTS 401 ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 41330 ) FS ; + - _001_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _002_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _003_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _004_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _005_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _006_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _007_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _008_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _009_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _010_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _011_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _012_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _013_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _014_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _015_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _016_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _017_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _018_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _019_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _020_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _021_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _022_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _023_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _024_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _025_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _026_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _027_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _028_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _029_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _030_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _031_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _032_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _033_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _034_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _035_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _036_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _037_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _038_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _039_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _040_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _041_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _042_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _043_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _044_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _045_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _046_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _047_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _048_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _049_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _050_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _051_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _052_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _053_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _054_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _055_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _056_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _057_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _058_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _059_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _060_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _061_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _062_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _063_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _064_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _065_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _066_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _067_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _068_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _069_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _070_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _071_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _072_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _073_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _074_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _075_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _076_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _077_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _078_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _079_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _080_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _081_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _082_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _083_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _084_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _085_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _086_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _087_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _088_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _089_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _090_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _091_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _092_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _093_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _094_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _095_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _096_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _097_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _098_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _099_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _100_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _101_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _102_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _103_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _104_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _105_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _106_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _107_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _108_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _109_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _110_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _111_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _112_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _113_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _114_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _115_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _116_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _117_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _118_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _119_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _120_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _121_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _122_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _123_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _124_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _125_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _126_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _127_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _128_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _129_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _130_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _131_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _132_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _133_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _134_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _135_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _136_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _137_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _138_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _139_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _140_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _141_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _142_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _143_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _144_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _145_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _146_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _147_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _148_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _149_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _150_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _151_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _152_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _153_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _154_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _155_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _156_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _157_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _158_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _159_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _160_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _161_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _162_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _163_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _164_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _165_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _166_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _167_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _168_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _169_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _170_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _171_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _172_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _173_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _174_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _175_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _176_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _177_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _178_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _179_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _180_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _181_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _182_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _183_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _184_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _185_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _186_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _187_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _188_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _189_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _190_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _191_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _192_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _193_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _194_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _195_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _196_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _197_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _198_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _199_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _200_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _201_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _202_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _203_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _204_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _205_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _206_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _207_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _208_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _209_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _210_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _211_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _212_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _213_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _214_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _215_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _216_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _217_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _218_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _219_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _220_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _221_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _222_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _223_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _224_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _225_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _226_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _227_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _228_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _229_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _230_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _231_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _232_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _233_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _234_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _235_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _236_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _237_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _238_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _239_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _240_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _241_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _242_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _243_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _244_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _245_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _246_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _247_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _248_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _249_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _250_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _251_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _252_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _253_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _254_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _255_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _256_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _257_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _258_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _259_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _260_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _261_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _262_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _263_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _264_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _265_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _266_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _267_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _268_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _269_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _270_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _271_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _272_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _273_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _274_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _275_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _276_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _277_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _278_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _279_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _280_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _281_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _282_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _283_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _284_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _285_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _286_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _287_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _288_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _289_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _290_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _291_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _292_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _293_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _294_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _295_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _296_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _297_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _298_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _299_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _300_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _301_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _302_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _303_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _304_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _305_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _306_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _307_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _308_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _309_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _310_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _311_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _312_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _313_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _314_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _315_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _316_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _317_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _318_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _319_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _320_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _321_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _322_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _323_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _324_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _325_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _326_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _327_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _328_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _329_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _330_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _331_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _332_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _333_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _334_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _335_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _336_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _337_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _338_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _339_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _340_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _341_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _342_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _343_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _344_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _345_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _346_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _347_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _348_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _349_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _350_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _351_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _352_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _353_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _354_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _355_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _356_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _357_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _358_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _359_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _360_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _361_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _362_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _363_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _364_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _365_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _366_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _367_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _368_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _369_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _370_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _371_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _372_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _373_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _374_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _375_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _376_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _377_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _378_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _379_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _380_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _381_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _382_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _383_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _384_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _385_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _386_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _387_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _388_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _389_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _390_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _391_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _392_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _393_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _394_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _395_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _396_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _397_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _398_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _399_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - _400_ DFF_X1 + PLACED ( 38218 123234 ) N ; +END COMPONENTS +PINS 3 ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + PLACED ( 254430 140 ) N ; + - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + PLACED ( 238750 140 ) N ; + - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + PLACED ( 234270 140 ) N ; +END PINS +NETS 3 ; + - io_1 ( PIN io_1 ) + USE SIGNAL ; + - io_2 ( PIN io_2 ) + USE SIGNAL ; + - io_3 ( PIN io_3 ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/mpl/test/io_constraints3.ok b/src/mpl/test/io_constraints3.ok new file mode 100644 index 00000000000..768c68b91c8 --- /dev/null +++ b/src/mpl/test/io_constraints3.ok @@ -0,0 +1,30 @@ +[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: ./testcases/macro_only.lef, created 9 library cells +[WARNING STA-1171] ./testcases/macro_only.lib line 32, default_max_transition is 0.0. +[WARNING ORD-2011] LEF master DFF_X1 has no liberty cell. +[INFO ODB-0128] Design: io_constraints1 +[INFO ODB-0252] Updated 3 pins. +[INFO ODB-0253] Updated 401 components. +Found 1 macro blocks. +Using 2 tracks default min distance between IO pins. +[INFO PPL-0001] Number of slots 966 +[INFO PPL-0002] Number of I/O 3 +[INFO PPL-0003] Number of I/O w/sink 0 +[INFO PPL-0004] Number of I/O w/o sink 3 +[INFO PPL-0012] I/O nets HPWL: 0.00 um. +Die Area: (0, 0) (150, 125), Floorplan Area: (0, 0) (149.91, 124.6) + Number of std cell instances: 400 + Area of std cell instances: 1808.79 + Number of macros: 1 + Area of macros: 10000.00 + Halo width: 4.00 + Halo height: 4.00 + Area of macros with halos: 11664.00 + Area of std cell instances + Area of macros: 11808.79 + Floorplan area: 18678.79 + Design Utilization: 0.63 + Floorplan Utilization: 0.21 + Manufacturing Grid: 10 + +[WARNING MPL-0014] No Liberty data found for std cells. Continuing without dataflow. +No differences found. diff --git a/src/mpl/test/io_constraints3.tcl b/src/mpl/test/io_constraints3.tcl new file mode 100644 index 00000000000..0dbbe45b267 --- /dev/null +++ b/src/mpl/test/io_constraints3.tcl @@ -0,0 +1,26 @@ +# Test if pin access blockages are generated correctly for a case +# with two blocked regions for pins. +source "helpers.tcl" + +# We're not interested in the connections, so don't include the lib. +read_lef "./Nangate45/Nangate45.lef" + +read_lef "./testcases/macro_only.lef" +read_liberty "./testcases/macro_only.lib" + +read_verilog "./testcases/io_constraints1.v" +link_design "io_constraints1" +read_def "./testcases/io_constraints1.def" -floorplan_initialize + +# Run random PPL to incorporate the -exclude constraints into ODB +place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 \ + -exclude right:40-125 \ + -exclude top:10-150 + +set_thread_count 0 +rtl_macro_placer -report_directory results/io_constraints3 -halo_width 4.0 + +set def_file [make_result_file io_constraints3.def] +write_def $def_file + +diff_files io_constraints3.defok $def_file \ No newline at end of file diff --git a/src/mpl/test/io_constraints4.defok b/src/mpl/test/io_constraints4.defok new file mode 100644 index 00000000000..124abf7b7b7 --- /dev/null +++ b/src/mpl/test/io_constraints4.defok @@ -0,0 +1,538 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN io_constraints1 ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 300000 250000 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; +COMPONENTS 401 ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8010 ) S ; + - _001_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _002_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _003_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _004_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _005_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _006_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _007_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _008_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _009_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _010_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _011_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _012_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _013_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _014_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _015_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _016_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _017_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _018_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _019_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _020_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _021_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _022_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _023_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _024_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _025_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _026_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _027_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _028_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _029_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _030_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _031_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _032_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _033_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _034_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _035_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _036_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _037_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _038_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _039_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _040_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _041_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _042_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _043_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _044_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _045_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _046_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _047_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _048_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _049_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _050_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _051_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _052_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _053_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _054_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _055_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _056_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _057_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _058_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _059_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _060_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _061_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _062_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _063_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _064_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _065_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _066_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _067_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _068_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _069_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _070_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _071_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _072_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _073_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _074_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _075_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _076_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _077_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _078_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _079_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _080_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _081_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _082_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _083_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _084_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _085_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _086_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _087_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _088_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _089_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _090_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _091_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _092_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _093_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _094_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _095_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _096_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _097_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _098_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _099_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _100_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _101_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _102_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _103_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _104_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _105_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _106_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _107_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _108_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _109_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _110_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _111_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _112_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _113_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _114_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _115_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _116_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _117_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _118_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _119_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _120_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _121_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _122_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _123_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _124_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _125_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _126_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _127_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _128_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _129_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _130_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _131_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _132_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _133_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _134_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _135_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _136_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _137_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _138_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _139_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _140_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _141_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _142_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _143_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _144_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _145_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _146_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _147_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _148_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _149_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _150_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _151_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _152_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _153_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _154_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _155_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _156_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _157_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _158_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _159_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _160_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _161_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _162_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _163_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _164_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _165_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _166_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _167_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _168_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _169_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _170_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _171_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _172_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _173_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _174_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _175_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _176_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _177_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _178_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _179_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _180_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _181_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _182_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _183_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _184_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _185_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _186_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _187_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _188_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _189_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _190_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _191_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _192_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _193_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _194_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _195_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _196_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _197_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _198_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _199_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _200_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _201_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _202_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _203_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _204_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _205_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _206_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _207_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _208_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _209_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _210_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _211_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _212_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _213_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _214_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _215_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _216_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _217_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _218_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _219_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _220_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _221_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _222_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _223_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _224_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _225_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _226_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _227_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _228_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _229_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _230_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _231_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _232_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _233_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _234_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _235_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _236_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _237_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _238_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _239_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _240_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _241_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _242_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _243_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _244_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _245_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _246_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _247_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _248_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _249_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _250_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _251_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _252_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _253_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _254_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _255_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _256_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _257_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _258_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _259_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _260_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _261_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _262_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _263_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _264_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _265_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _266_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _267_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _268_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _269_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _270_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _271_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _272_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _273_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _274_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _275_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _276_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _277_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _278_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _279_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _280_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _281_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _282_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _283_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _284_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _285_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _286_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _287_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _288_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _289_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _290_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _291_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _292_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _293_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _294_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _295_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _296_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _297_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _298_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _299_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _300_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _301_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _302_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _303_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _304_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _305_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _306_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _307_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _308_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _309_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _310_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _311_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _312_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _313_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _314_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _315_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _316_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _317_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _318_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _319_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _320_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _321_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _322_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _323_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _324_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _325_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _326_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _327_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _328_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _329_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _330_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _331_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _332_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _333_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _334_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _335_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _336_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _337_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _338_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _339_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _340_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _341_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _342_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _343_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _344_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _345_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _346_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _347_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _348_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _349_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _350_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _351_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _352_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _353_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _354_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _355_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _356_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _357_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _358_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _359_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _360_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _361_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _362_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _363_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _364_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _365_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _366_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _367_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _368_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _369_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _370_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _371_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _372_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _373_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _374_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _375_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _376_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _377_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _378_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _379_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _380_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _381_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _382_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _383_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _384_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _385_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _386_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _387_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _388_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _389_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _390_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _391_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _392_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _393_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _394_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _395_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _396_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _397_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _398_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _399_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _400_ DFF_X1 + PLACED ( 38680 123234 ) N ; +END COMPONENTS +PINS 3 ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 140 164780 ) N ; + - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 140 147980 ) N ; + - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 299860 178220 ) N ; +END PINS +NETS 3 ; + - io_1 ( PIN io_1 ) + USE SIGNAL ; + - io_2 ( PIN io_2 ) + USE SIGNAL ; + - io_3 ( PIN io_3 ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/mpl/test/io_constraints4.ok b/src/mpl/test/io_constraints4.ok new file mode 100644 index 00000000000..69a60b1bb05 --- /dev/null +++ b/src/mpl/test/io_constraints4.ok @@ -0,0 +1,32 @@ +[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: ./testcases/macro_only.lef, created 9 library cells +[WARNING STA-1171] ./testcases/macro_only.lib line 32, default_max_transition is 0.0. +[WARNING ORD-2011] LEF master DFF_X1 has no liberty cell. +[INFO ODB-0128] Design: io_constraints1 +[INFO ODB-0252] Updated 3 pins. +[INFO ODB-0253] Updated 401 components. +[INFO PPL-0048] Restrict pins [ io_1 io_2 ] to region 70.00u-90.00u at the LEFT edge. +[INFO PPL-0048] Restrict pins [ io_3 ] to region 70.00u-90.00u at the RIGHT edge. +Found 1 macro blocks. +Using 2 tracks default min distance between IO pins. +[INFO PPL-0001] Number of slots 966 +[INFO PPL-0002] Number of I/O 3 +[INFO PPL-0003] Number of I/O w/sink 0 +[INFO PPL-0004] Number of I/O w/o sink 3 +[INFO PPL-0012] I/O nets HPWL: 0.00 um. +Die Area: (0, 0) (150, 125), Floorplan Area: (0, 0) (149.91, 124.6) + Number of std cell instances: 400 + Area of std cell instances: 1808.79 + Number of macros: 1 + Area of macros: 10000.00 + Halo width: 4.00 + Halo height: 4.00 + Area of macros with halos: 11664.00 + Area of std cell instances + Area of macros: 11808.79 + Floorplan area: 18678.79 + Design Utilization: 0.63 + Floorplan Utilization: 0.21 + Manufacturing Grid: 10 + +[WARNING MPL-0014] No Liberty data found for std cells. Continuing without dataflow. +No differences found. diff --git a/src/mpl/test/io_constraints4.tcl b/src/mpl/test/io_constraints4.tcl new file mode 100644 index 00000000000..955b779b466 --- /dev/null +++ b/src/mpl/test/io_constraints4.tcl @@ -0,0 +1,28 @@ +# Test if pin access blockages are generated correctly for a case +# with pins with different constraint regions. One region has +# more pins and should have a larger blockage. +source "helpers.tcl" + +# We're not interested in the connections, so don't include the lib. +read_lef "./Nangate45/Nangate45.lef" + +read_lef "./testcases/macro_only.lef" +read_liberty "./testcases/macro_only.lib" + +read_verilog "./testcases/io_constraints1.v" +link_design "io_constraints1" +read_def "./testcases/io_constraints1.def" -floorplan_initialize + +set_io_pin_constraint -pin_names {io_1 io_2} -region left:70-90 +set_io_pin_constraint -pin_names {io_3} -region right:70-90 + +# Run random PPL to incorporate the constraints into ODB +place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 + +set_thread_count 0 +rtl_macro_placer -report_directory results/io_constraints4 -halo_width 4.0 + +set def_file [make_result_file io_constraints4.def] +write_def $def_file + +diff_files io_constraints4.defok $def_file \ No newline at end of file diff --git a/src/mpl/test/io_constraints5.defok b/src/mpl/test/io_constraints5.defok new file mode 100644 index 00000000000..e55414fd635 --- /dev/null +++ b/src/mpl/test/io_constraints5.defok @@ -0,0 +1,538 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN io_constraints1 ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 300000 250000 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; +COMPONENTS 401 ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8010 ) S ; + - _001_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _002_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _003_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _004_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _005_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _006_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _007_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _008_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _009_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _010_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _011_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _012_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _013_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _014_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _015_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _016_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _017_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _018_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _019_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _020_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _021_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _022_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _023_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _024_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _025_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _026_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _027_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _028_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _029_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _030_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _031_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _032_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _033_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _034_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _035_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _036_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _037_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _038_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _039_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _040_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _041_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _042_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _043_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _044_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _045_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _046_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _047_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _048_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _049_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _050_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _051_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _052_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _053_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _054_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _055_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _056_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _057_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _058_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _059_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _060_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _061_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _062_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _063_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _064_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _065_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _066_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _067_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _068_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _069_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _070_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _071_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _072_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _073_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _074_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _075_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _076_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _077_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _078_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _079_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _080_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _081_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _082_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _083_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _084_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _085_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _086_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _087_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _088_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _089_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _090_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _091_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _092_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _093_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _094_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _095_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _096_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _097_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _098_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _099_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _100_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _101_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _102_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _103_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _104_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _105_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _106_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _107_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _108_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _109_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _110_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _111_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _112_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _113_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _114_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _115_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _116_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _117_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _118_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _119_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _120_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _121_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _122_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _123_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _124_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _125_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _126_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _127_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _128_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _129_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _130_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _131_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _132_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _133_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _134_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _135_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _136_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _137_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _138_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _139_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _140_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _141_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _142_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _143_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _144_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _145_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _146_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _147_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _148_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _149_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _150_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _151_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _152_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _153_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _154_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _155_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _156_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _157_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _158_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _159_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _160_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _161_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _162_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _163_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _164_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _165_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _166_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _167_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _168_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _169_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _170_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _171_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _172_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _173_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _174_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _175_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _176_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _177_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _178_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _179_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _180_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _181_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _182_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _183_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _184_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _185_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _186_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _187_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _188_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _189_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _190_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _191_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _192_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _193_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _194_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _195_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _196_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _197_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _198_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _199_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _200_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _201_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _202_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _203_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _204_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _205_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _206_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _207_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _208_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _209_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _210_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _211_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _212_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _213_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _214_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _215_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _216_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _217_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _218_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _219_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _220_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _221_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _222_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _223_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _224_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _225_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _226_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _227_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _228_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _229_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _230_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _231_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _232_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _233_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _234_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _235_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _236_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _237_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _238_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _239_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _240_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _241_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _242_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _243_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _244_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _245_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _246_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _247_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _248_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _249_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _250_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _251_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _252_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _253_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _254_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _255_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _256_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _257_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _258_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _259_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _260_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _261_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _262_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _263_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _264_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _265_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _266_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _267_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _268_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _269_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _270_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _271_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _272_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _273_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _274_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _275_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _276_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _277_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _278_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _279_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _280_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _281_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _282_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _283_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _284_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _285_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _286_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _287_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _288_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _289_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _290_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _291_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _292_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _293_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _294_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _295_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _296_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _297_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _298_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _299_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _300_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _301_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _302_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _303_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _304_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _305_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _306_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _307_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _308_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _309_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _310_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _311_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _312_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _313_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _314_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _315_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _316_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _317_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _318_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _319_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _320_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _321_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _322_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _323_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _324_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _325_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _326_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _327_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _328_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _329_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _330_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _331_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _332_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _333_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _334_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _335_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _336_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _337_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _338_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _339_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _340_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _341_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _342_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _343_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _344_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _345_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _346_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _347_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _348_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _349_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _350_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _351_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _352_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _353_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _354_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _355_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _356_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _357_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _358_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _359_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _360_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _361_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _362_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _363_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _364_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _365_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _366_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _367_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _368_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _369_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _370_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _371_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _372_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _373_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _374_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _375_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _376_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _377_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _378_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _379_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _380_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _381_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _382_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _383_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _384_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _385_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _386_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _387_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _388_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _389_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _390_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _391_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _392_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _393_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _394_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _395_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _396_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _397_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _398_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _399_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _400_ DFF_X1 + PLACED ( 254680 123234 ) N ; +END COMPONENTS +PINS 3 ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 299860 154700 ) N ; + - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 299860 171500 ) N ; + - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 299860 96460 ) N ; +END PINS +NETS 3 ; + - io_1 ( PIN io_1 ) + USE SIGNAL ; + - io_2 ( PIN io_2 ) + USE SIGNAL ; + - io_3 ( PIN io_3 ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/mpl/test/io_constraints5.ok b/src/mpl/test/io_constraints5.ok new file mode 100644 index 00000000000..33d4213f7ce --- /dev/null +++ b/src/mpl/test/io_constraints5.ok @@ -0,0 +1,32 @@ +[INFO ODB-0227] LEF file: ./Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: ./testcases/macro_only.lef, created 9 library cells +[WARNING STA-1171] ./testcases/macro_only.lib line 32, default_max_transition is 0.0. +[WARNING ORD-2011] LEF master DFF_X1 has no liberty cell. +[INFO ODB-0128] Design: io_constraints1 +[INFO ODB-0252] Updated 3 pins. +[INFO ODB-0253] Updated 401 components. +[INFO PPL-0048] Restrict pins [ io_1 io_2 ] to region 70.00u-90.00u at the RIGHT edge. +[INFO PPL-0048] Restrict pins [ io_3 ] to region 10.00u-50.00u at the RIGHT edge. +Found 1 macro blocks. +Using 2 tracks default min distance between IO pins. +[INFO PPL-0001] Number of slots 966 +[INFO PPL-0002] Number of I/O 3 +[INFO PPL-0003] Number of I/O w/sink 0 +[INFO PPL-0004] Number of I/O w/o sink 3 +[INFO PPL-0012] I/O nets HPWL: 0.00 um. +Die Area: (0, 0) (150, 125), Floorplan Area: (0, 0) (149.91, 124.6) + Number of std cell instances: 400 + Area of std cell instances: 1808.79 + Number of macros: 1 + Area of macros: 10000.00 + Halo width: 4.00 + Halo height: 4.00 + Area of macros with halos: 11664.00 + Area of std cell instances + Area of macros: 11808.79 + Floorplan area: 18678.79 + Design Utilization: 0.63 + Floorplan Utilization: 0.21 + Manufacturing Grid: 10 + +[WARNING MPL-0014] No Liberty data found for std cells. Continuing without dataflow. +No differences found. diff --git a/src/mpl/test/io_constraints5.tcl b/src/mpl/test/io_constraints5.tcl new file mode 100644 index 00000000000..f18bdf2ebf2 --- /dev/null +++ b/src/mpl/test/io_constraints5.tcl @@ -0,0 +1,28 @@ +# Test if pin access blockages are generated correctly for a case +# with pins with different constraint regions. Both regions are +# in the same boundary, but have different densities. +source "helpers.tcl" + +# We're not interested in the connections, so don't include the lib. +read_lef "./Nangate45/Nangate45.lef" + +read_lef "./testcases/macro_only.lef" +read_liberty "./testcases/macro_only.lib" + +read_verilog "./testcases/io_constraints1.v" +link_design "io_constraints1" +read_def "./testcases/io_constraints1.def" -floorplan_initialize + +set_io_pin_constraint -pin_names {io_1 io_2} -region right:70-90 +set_io_pin_constraint -pin_names {io_3} -region right:10-50 + +# Run random PPL to incorporate the constraints into ODB +place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 + +set_thread_count 0 +rtl_macro_placer -report_directory results/io_constraints5 -halo_width 4.0 + +set def_file [make_result_file io_constraints5.def] +write_def $def_file + +diff_files io_constraints5.defok $def_file \ No newline at end of file From a102c48c676745263b5c52a7aec3449ade8930ab Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Thu, 6 Feb 2025 16:45:54 -0300 Subject: [PATCH 02/34] mpl: some refactoring, clean up and anotations for subsequent work Signed-off-by: Arthur Koucher --- src/mpl/src/clusterEngine.cpp | 7 ------- src/mpl/src/clusterEngine.h | 4 +--- src/mpl/src/hier_rtlmp.cpp | 39 ++++++++++++++++++++--------------- src/mpl/src/hier_rtlmp.h | 8 ++++--- 4 files changed, 28 insertions(+), 30 deletions(-) diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 81afeeaac0a..2e5e22fee84 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -67,9 +67,7 @@ void ClusteringEngine::run() mapIOPinsAndPads(); createDataFlow(); - createIOClusters(); - setBlockedRegionsForPins(); if (design_metrics_->getNumStdCell() == 0) { logger_->warn(MPL, 25, "Design has no standard cells!"); @@ -439,11 +437,6 @@ void ClusteringEngine::createIOCluster( tree_->root->addChild(std::move(cluster)); } -void ClusteringEngine::setBlockedRegionsForPins() -{ - tree_->blocked_regions_for_pins = block_->getBlockedRegionsForPins(); -} - void ClusteringEngine::mapIOPinsAndPads() { bool design_has_io_pads = false; diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 56634fb739b..96e32c89963 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -113,9 +113,8 @@ struct PhysicalHierarchy std::unique_ptr root; PhysicalHierarchyMaps maps; - std::vector blocked_regions_for_pins; std::set blocked_boundaries; // TODO: remove - std::set unblocked_boundaries; // For orientation improvement. + std::set unblocked_boundaries; // TODO: remove float halo_width{0.0f}; float halo_height{0.0f}; @@ -199,7 +198,6 @@ class ClusteringEngine const odb::Rect& bterm_constraint); void createIOPadClusters(); void createIOPadCluster(odb::dbInst* pad, odb::dbBTerm* bterm); - void setBlockedRegionsForPins(); void mapIOPinsAndPads(); void treatEachMacroAsSingleCluster(); void incorporateNewCluster(std::unique_ptr cluster, Cluster* parent); diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index fca800a7f46..867d9bf4460 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -891,6 +891,23 @@ void HierRTLMP::createPinAccessBlockages() } if (tree_->has_only_unconstrained_ios) { + const std::vector& blocked_regions_for_pins + = block_->getBlockedRegionsForPins(); + + if (blocked_regions_for_pins.empty()) { + // If there are no constraints at all, we give freedom to SA so it + // doesn't have to deal with pin access blockages in all boundaries. + // This will help SA not relying on extreme utilizations to + // converge for designs such as sky130hd/uW. + return; + } + + BoundaryToRegionsMap boundary_to_blocked_regions + = getBoundaryToBlockedRegionsMap(blocked_regions_for_pins); + + available_regions_for_pins_ + = computeAvailableRegions(boundary_to_blocked_regions); + createBlockagesForAvailableRegions(); } else { createBlockagesForConstraintRegions(); @@ -899,28 +916,15 @@ void HierRTLMP::createPinAccessBlockages() void HierRTLMP::createBlockagesForAvailableRegions() { - if (tree_->blocked_regions_for_pins.empty()) { - // If there are no constraints at all, give freedom to SA so it - // doesn't have to deal with pin access blockages in all boundaries. - // This will help SA not relying on extreme utilizations to - // converge for designs such as sky130hd/uW. - return; - } - - BoundaryToRegionsMap boundary_to_blocked_regions - = getBoundaryToBlockedRegionsMap(); - std::vector available_regions - = computeAvailableRegions(boundary_to_blocked_regions); - float io_span = 0.0f; - for (const odb::Rect& available_region : available_regions) { + for (const odb::Rect& available_region : available_regions_for_pins_) { const Rect region = dbuToMicrons(available_region); io_span += region.getPerimeter() / 2; } const float depth = computePinAccessBaseDepth(io_span); - for (const odb::Rect& available_region : available_regions) { + for (const odb::Rect& available_region : available_regions_for_pins_) { createPinAccessBlockage(dbuToMicrons(available_region), depth); } } @@ -960,7 +964,8 @@ void HierRTLMP::createBlockagesForConstraintRegions() } } -BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap() +BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap( + const std::vector& blocked_regions_for_pins) { BoundaryToRegionsMap boundary_to_blocked_regions; std::queue blocked_regions; @@ -970,7 +975,7 @@ BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap() boundary_to_blocked_regions[B] = blocked_regions; boundary_to_blocked_regions[T] = blocked_regions; - for (const odb::Rect& blocked_region : tree_->blocked_regions_for_pins) { + for (const odb::Rect& blocked_region : blocked_regions_for_pins) { Boundary boundary = getRegionBoundary(blocked_region); boundary_to_blocked_regions.at(boundary).push(blocked_region); diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index 1375e6415fe..c86bc128a34 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -182,7 +182,8 @@ class HierRTLMP std::vector getClustersOfUnplacedIOPins(); void createPinAccessBlockage(const Rect& micron_region, const float depth); float computePinAccessBaseDepth(const float io_span); - BoundaryToRegionsMap getBoundaryToBlockedRegionsMap(); + BoundaryToRegionsMap getBoundaryToBlockedRegionsMap( + const std::vector& blocked_regions_for_pins); std::vector computeAvailableRegions( BoundaryToRegionsMap& boundary_to_blocked_regions); void createBlockagesForAvailableRegions(); @@ -325,7 +326,8 @@ class HierRTLMP std::vector placement_blockages_; std::vector macro_blockages_; std::vector io_blockages_; - std::map boundary_to_io_blockage_; + std::vector available_regions_for_pins_; + std::map boundary_to_io_blockage_; // TODO: remove // Fast SA hyperparameter float init_prob_ = 0.9; @@ -387,7 +389,7 @@ class Pusher odb::dbBlock* block_; odb::Rect core_; - std::map boundary_to_io_blockage_; + std::map boundary_to_io_blockage_; // TODO: remove std::vector hard_macros_; }; From f8f5de59db728ac823fe581bd740cb4e2b46792c Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Thu, 27 Feb 2025 14:38:09 -0300 Subject: [PATCH 03/34] mpl: 1) Improve comments 2) Renaming 3) Update regression tests results for: a. Snapper truncated value fix b. New spdlog default float type report 4) Improve regression tests comment descriptions Signed-off-by: Arthur Koucher --- src/mpl/src/clusterEngine.cpp | 18 ++++++++++-------- src/mpl/src/clusterEngine.h | 7 ++++--- src/mpl/test/io_constraints3.ok | 2 +- src/mpl/test/io_constraints4.defok | 2 +- src/mpl/test/io_constraints4.ok | 2 +- src/mpl/test/io_constraints4.tcl | 5 +++-- src/mpl/test/io_constraints5.defok | 2 +- src/mpl/test/io_constraints5.ok | 2 +- src/mpl/test/io_constraints5.tcl | 2 +- 9 files changed, 23 insertions(+), 19 deletions(-) diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 2e5e22fee84..757eaedd23c 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -361,11 +361,11 @@ void ClusteringEngine::setBaseThresholds() // 1. A Group of Unplaced Pins; // 2. An IO Pad. // -// For the former, we group IO pins that are constrainted to the same region; -// the shape of the cluster is the shape of the constraint region. -// If a pin has no constraints, we consider it constrained to all edges of -// the die area - for this case, the shape of the IO cluster is the shape of -// the die area. +// For 1: +// We group IO pins that are constrained to the same region - the cluster's +// shape is the constraint region. If a pin has no constraints, we consider +// it constrained to all edges of the die area - for this case, the cluster's +// shape is the die area. void ClusteringEngine::createIOClusters() { if (!tree_->maps.pad_to_bterm.empty()) { @@ -386,9 +386,11 @@ void ClusteringEngine::createIOClusters() auto bterm_constraint = bterm->getConstraintRegion(); if (bterm_constraint) { design_has_only_unconstrained_ios = false; - createIOCluster(cluster_and_region_list, bterm, bterm_constraint.value()); + createClusterOfUnplacedIOs( + cluster_and_region_list, bterm, bterm_constraint.value()); } else { - createIOCluster(cluster_and_region_list, bterm, block_->getDieArea()); + createClusterOfUnplacedIOs( + cluster_and_region_list, bterm, block_->getDieArea()); } } @@ -398,7 +400,7 @@ void ClusteringEngine::createIOClusters() } // Isso pode ter um nome melhor -void ClusteringEngine::createIOCluster( +void ClusteringEngine::createClusterOfUnplacedIOs( std::vector& cluster_and_region_list, odb::dbBTerm* bterm, const odb::Rect& bterm_constraint) diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 96e32c89963..e183e3040d9 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -193,9 +193,10 @@ class ClusteringEngine void createRoot(); void setBaseThresholds(); void createIOClusters(); - void createIOCluster(std::vector& cluster_and_region_list, - odb::dbBTerm* bterm, - const odb::Rect& bterm_constraint); + void createClusterOfUnplacedIOs( + std::vector& cluster_and_region_list, + odb::dbBTerm* bterm, + const odb::Rect& bterm_constraint); void createIOPadClusters(); void createIOPadCluster(odb::dbInst* pad, odb::dbBTerm* bterm); void mapIOPinsAndPads(); diff --git a/src/mpl/test/io_constraints3.ok b/src/mpl/test/io_constraints3.ok index 768c68b91c8..103ea9491ac 100644 --- a/src/mpl/test/io_constraints3.ok +++ b/src/mpl/test/io_constraints3.ok @@ -12,7 +12,7 @@ Using 2 tracks default min distance between IO pins. [INFO PPL-0003] Number of I/O w/sink 0 [INFO PPL-0004] Number of I/O w/o sink 3 [INFO PPL-0012] I/O nets HPWL: 0.00 um. -Die Area: (0, 0) (150, 125), Floorplan Area: (0, 0) (149.91, 124.6) +Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) Number of std cell instances: 400 Area of std cell instances: 1808.79 Number of macros: 1 diff --git a/src/mpl/test/io_constraints4.defok b/src/mpl/test/io_constraints4.defok index 124abf7b7b7..d4d22e5510b 100644 --- a/src/mpl/test/io_constraints4.defok +++ b/src/mpl/test/io_constraints4.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8010 ) S ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8290 ) S ; - _001_ DFF_X1 + PLACED ( 38680 123234 ) N ; - _002_ DFF_X1 + PLACED ( 38680 123234 ) N ; - _003_ DFF_X1 + PLACED ( 38680 123234 ) N ; diff --git a/src/mpl/test/io_constraints4.ok b/src/mpl/test/io_constraints4.ok index 69a60b1bb05..69e2549b96d 100644 --- a/src/mpl/test/io_constraints4.ok +++ b/src/mpl/test/io_constraints4.ok @@ -14,7 +14,7 @@ Using 2 tracks default min distance between IO pins. [INFO PPL-0003] Number of I/O w/sink 0 [INFO PPL-0004] Number of I/O w/o sink 3 [INFO PPL-0012] I/O nets HPWL: 0.00 um. -Die Area: (0, 0) (150, 125), Floorplan Area: (0, 0) (149.91, 124.6) +Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) Number of std cell instances: 400 Area of std cell instances: 1808.79 Number of macros: 1 diff --git a/src/mpl/test/io_constraints4.tcl b/src/mpl/test/io_constraints4.tcl index 955b779b466..37a6ce29cfe 100644 --- a/src/mpl/test/io_constraints4.tcl +++ b/src/mpl/test/io_constraints4.tcl @@ -1,6 +1,7 @@ # Test if pin access blockages are generated correctly for a case -# with pins with different constraint regions. One region has -# more pins and should have a larger blockage. +# with pins with different constraint regions. The region on the left +# edge has more pins and should have a larger blockage. The macro should, +# then, be placed closer to the right edge. source "helpers.tcl" # We're not interested in the connections, so don't include the lib. diff --git a/src/mpl/test/io_constraints5.defok b/src/mpl/test/io_constraints5.defok index e55414fd635..0cc9325891e 100644 --- a/src/mpl/test/io_constraints5.defok +++ b/src/mpl/test/io_constraints5.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8010 ) S ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8290 ) S ; - _001_ DFF_X1 + PLACED ( 254680 123234 ) N ; - _002_ DFF_X1 + PLACED ( 254680 123234 ) N ; - _003_ DFF_X1 + PLACED ( 254680 123234 ) N ; diff --git a/src/mpl/test/io_constraints5.ok b/src/mpl/test/io_constraints5.ok index 33d4213f7ce..97af0d303a5 100644 --- a/src/mpl/test/io_constraints5.ok +++ b/src/mpl/test/io_constraints5.ok @@ -14,7 +14,7 @@ Using 2 tracks default min distance between IO pins. [INFO PPL-0003] Number of I/O w/sink 0 [INFO PPL-0004] Number of I/O w/o sink 3 [INFO PPL-0012] I/O nets HPWL: 0.00 um. -Die Area: (0, 0) (150, 125), Floorplan Area: (0, 0) (149.91, 124.6) +Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) Number of std cell instances: 400 Area of std cell instances: 1808.79 Number of macros: 1 diff --git a/src/mpl/test/io_constraints5.tcl b/src/mpl/test/io_constraints5.tcl index f18bdf2ebf2..94328e9b194 100644 --- a/src/mpl/test/io_constraints5.tcl +++ b/src/mpl/test/io_constraints5.tcl @@ -1,6 +1,6 @@ # Test if pin access blockages are generated correctly for a case # with pins with different constraint regions. Both regions are -# in the same boundary, but have different densities. +# in the same boundary, but have different IO density. source "helpers.tcl" # We're not interested in the connections, so don't include the lib. From f157c03250af3fab4051627faa290527feddd049 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 28 Feb 2025 14:55:39 -0300 Subject: [PATCH 04/34] mpl: uncomment code Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.cpp | 96 +++++++++++++------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 21c41b5d49c..9e4de3a2f4c 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -328,54 +328,54 @@ void SimulatedAnnealingCore::addBoundaryDistToWirelength( const T& io, const float net_weight) { - // Cluster* io_cluster = io.getCluster(); - // const Rect die = io_cluster->getBBox(); - // const float die_hpwl = die.getWidth() + die.getHeight(); - - // if (isOutsideTheOutline(macro)) { - // wirelength_ += net_weight * die_hpwl; - // return; - // } - - // const float x1 = macro.getPinX(); - // const float y1 = macro.getPinY(); - - // Boundary constraint_boundary = io_cluster->getConstraintBoundary(); - - // if (constraint_boundary == NONE) { - // float dist_to_left = die_hpwl; - // if (!left_is_blocked_) { - // dist_to_left = std::abs(x1 - die.xMin()); - // } - - // float dist_to_right = die_hpwl; - // if (!right_is_blocked_) { - // dist_to_right = std::abs(x1 - die.xMax()); - // } - - // float dist_to_bottom = die_hpwl; - // if (!bottom_is_blocked_) { - // dist_to_right = std::abs(y1 - die.yMin()); - // } - - // float dist_to_top = die_hpwl; - // if (!top_is_blocked_) { - // dist_to_top = std::abs(y1 - die.yMax()); - // } - - // wirelength_ - // += net_weight - // * std::min( - // {dist_to_left, dist_to_right, dist_to_bottom, dist_to_top}); - // } else if (constraint_boundary == Boundary::L - // || constraint_boundary == Boundary::R) { - // const float x2 = io.getPinX(); - // wirelength_ += net_weight * std::abs(x2 - x1); - // } else if (constraint_boundary == Boundary::T - // || constraint_boundary == Boundary::B) { - // const float y2 = io.getPinY(); - // wirelength_ += net_weight * std::abs(y2 - y1); - // } + Cluster* io_cluster = io.getCluster(); + const Rect die = io_cluster->getBBox(); + const float die_hpwl = die.getWidth() + die.getHeight(); + + if (isOutsideTheOutline(macro)) { + wirelength_ += net_weight * die_hpwl; + return; + } + + const float x1 = macro.getPinX(); + const float y1 = macro.getPinY(); + + Boundary constraint_boundary = io_cluster->getConstraintBoundary(); + + if (constraint_boundary == NONE) { + float dist_to_left = die_hpwl; + if (!left_is_blocked_) { + dist_to_left = std::abs(x1 - die.xMin()); + } + + float dist_to_right = die_hpwl; + if (!right_is_blocked_) { + dist_to_right = std::abs(x1 - die.xMax()); + } + + float dist_to_bottom = die_hpwl; + if (!bottom_is_blocked_) { + dist_to_right = std::abs(y1 - die.yMin()); + } + + float dist_to_top = die_hpwl; + if (!top_is_blocked_) { + dist_to_top = std::abs(y1 - die.yMax()); + } + + wirelength_ + += net_weight + * std::min( + {dist_to_left, dist_to_right, dist_to_bottom, dist_to_top}); + } else if (constraint_boundary == Boundary::L + || constraint_boundary == Boundary::R) { + const float x2 = io.getPinX(); + wirelength_ += net_weight * std::abs(x2 - x1); + } else if (constraint_boundary == Boundary::T + || constraint_boundary == Boundary::B) { + const float y2 = io.getPinY(); + wirelength_ += net_weight * std::abs(y2 - y1); + } } // We consider the macro outside the outline based on the location of From a4f6ea93592b195a24e72ac6ad4b2d1ab3cb1e6c Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 28 Feb 2025 12:11:39 -0300 Subject: [PATCH 05/34] mpl: fix limit/max cost for dist to boundary WL computation Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.cpp | 24 +++++++++++++++--------- src/mpl/src/SimulatedAnnealingCore.h | 8 ++++---- src/mpl/src/clusterEngine.cpp | 14 ++++++++++++++ src/mpl/src/clusterEngine.h | 2 ++ 4 files changed, 35 insertions(+), 13 deletions(-) diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 9e4de3a2f4c..e38da9f7068 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -86,6 +86,7 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, macros_ = macros; setBlockedBoundariesForIOs(); + die_hpwl_ = tree->die_area.getPerimeter() / 2; } template @@ -328,12 +329,8 @@ void SimulatedAnnealingCore::addBoundaryDistToWirelength( const T& io, const float net_weight) { - Cluster* io_cluster = io.getCluster(); - const Rect die = io_cluster->getBBox(); - const float die_hpwl = die.getWidth() + die.getHeight(); - if (isOutsideTheOutline(macro)) { - wirelength_ += net_weight * die_hpwl; + wirelength_ += net_weight * die_hpwl_; return; } @@ -343,22 +340,31 @@ void SimulatedAnnealingCore::addBoundaryDistToWirelength( Boundary constraint_boundary = io_cluster->getConstraintBoundary(); if (constraint_boundary == NONE) { - float dist_to_left = die_hpwl; + // We need to use the bbox of the SoftMacro and NOT the Cluster to + // get shape of the cluster of unconstrained IOs - which has the + // shape of the die but it's offset based on the current outline. + // Reminder: + // - The SoftMacro bbox is the bbox w.r.t to the current outline. + // - The Cluster bbox is the bbox w.r.t. to the origin of the actual + // die area. + const Rect& offset_die = io.getBBox(); + + float dist_to_left = die_hpwl_; if (!left_is_blocked_) { dist_to_left = std::abs(x1 - die.xMin()); } - float dist_to_right = die_hpwl; + float dist_to_right = die_hpwl_; if (!right_is_blocked_) { dist_to_right = std::abs(x1 - die.xMax()); } - float dist_to_bottom = die_hpwl; + float dist_to_bottom = die_hpwl_; if (!bottom_is_blocked_) { dist_to_right = std::abs(y1 - die.yMin()); } - float dist_to_top = die_hpwl; + float dist_to_top = die_hpwl_; if (!top_is_blocked_) { dist_to_top = std::abs(y1 - die.yMax()); } diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 71af90f3f5c..c488b0c0a2e 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -162,12 +162,12 @@ class SimulatedAnnealingCore void reportLocations() const; void report(const PenaltyData& penalty) const; - ///////////////////////////////////////////// - // private member variables - ///////////////////////////////////////////// - // boundary constraints Rect outline_; + // The max cost for distance to boundary wirelength computation + // when one of the SoftMacros is a cluster of unplaced IO pins. + float die_hpwl_; + // Boundaries blocked for IO pins std::set blocked_boundaries_; diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 757eaedd23c..9b1d94d0ae9 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -113,6 +113,7 @@ void ClusteringEngine::init() return; } + setDieArea(); setFloorplanShape(); searchForFixedInstsInsideFloorplanShape(); @@ -132,6 +133,19 @@ void ClusteringEngine::init() reportDesignData(); } +// Note: The die area's dimensions will be used inside +// SA Core when computing the wirelength in a situation in which +// the target cluster is a cluster of unplaced IOs. +void ClusteringEngine::setDieArea() +{ + const odb::Rect& die = block_->getDieArea(); + + tree_->die_area = Rect(block_->dbuToMicrons(die.xMin()), + block_->dbuToMicrons(die.yMin()), + block_->dbuToMicrons(die.xMax()), + block_->dbuToMicrons(die.yMax())); +} + float ClusteringEngine::computeMacroWithHaloArea( const std::vector& unfixed_macros) { diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index e183e3040d9..e89fa8ef57c 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -121,6 +121,7 @@ struct PhysicalHierarchy float macro_with_halo_area{0.0f}; Rect global_fence; Rect floorplan_shape; + Rect die_area; bool has_io_clusters{true}; bool has_only_unconstrained_ios{false}; @@ -185,6 +186,7 @@ class ClusteringEngine void init(); Metrics* computeModuleMetrics(odb::dbModule* module); std::vector getUnfixedMacros(); + void setDieArea(); void setFloorplanShape(); void searchForFixedInstsInsideFloorplanShape(); float computeMacroWithHaloArea( From 3c4fefce4495831b5717276a89e2b868ff4460be Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Tue, 4 Mar 2025 14:44:17 -0300 Subject: [PATCH 06/34] mpl: 1. Change WL computation mechanism for IO clusters: a. Clusters of unplaced IOs are treated as usual fixed terminals b. Clusters of unconstrained IOs have WL computed based on the distance to the center of the closest available region for pins. 2. Adapt graphics to the previous item; 3. Collateral changes: a. Add API to Soft/Hard macros to allow check for unconstrained IOs cluster; b. Create function to compute distance between << micron points >> Signed-off-by: Arthur Koucher --- src/mpl/src/MplObserver.h | 8 + src/mpl/src/SimulatedAnnealingCore.cpp | 90 +--- src/mpl/src/SimulatedAnnealingCore.h | 19 +- src/mpl/src/clusterEngine.h | 10 +- src/mpl/src/graphics.cpp | 209 ++------ src/mpl/src/graphics.h | 18 +- src/mpl/src/hier_rtlmp.cpp | 23 +- src/mpl/src/hier_rtlmp.h | 5 +- src/mpl/src/object.cpp | 18 + src/mpl/src/object.h | 4 +- src/mpl/src/util.h | 9 + src/mpl/test/CMakeLists.txt | 2 + src/mpl/test/io_constraints6.defok | 538 +++++++++++++++++++++ src/mpl/test/io_constraints6.ok | 28 ++ src/mpl/test/io_constraints6.tcl | 23 + src/mpl/test/io_constraints7.defok | 538 +++++++++++++++++++++ src/mpl/test/io_constraints7.ok | 30 ++ src/mpl/test/io_constraints7.tcl | 33 ++ src/mpl/test/testcases/io_constraints6.def | 531 ++++++++++++++++++++ 19 files changed, 1876 insertions(+), 260 deletions(-) create mode 100644 src/mpl/test/io_constraints6.defok create mode 100644 src/mpl/test/io_constraints6.ok create mode 100644 src/mpl/test/io_constraints6.tcl create mode 100644 src/mpl/test/io_constraints7.defok create mode 100644 src/mpl/test/io_constraints7.ok create mode 100644 src/mpl/test/io_constraints7.tcl create mode 100644 src/mpl/test/testcases/io_constraints6.def diff --git a/src/mpl/src/MplObserver.h b/src/mpl/src/MplObserver.h index ca8dc21ff34..5850b1e9e67 100644 --- a/src/mpl/src/MplObserver.h +++ b/src/mpl/src/MplObserver.h @@ -85,6 +85,14 @@ class MplObserver virtual void setOutline(const odb::Rect& outline) {} virtual void setGuides(const std::map& guides) {} virtual void setFences(const std::map& fences) {} + virtual void setBlockedRegionsForPins( + const std::vector& blocked_regions_for_pins) + { + } + virtual void setAvailableRegionsForPins( + const std::vector& available_regions_for_pins) + { + } virtual void setAreaPenalty(const PenaltyData& penalty) {} virtual void setBoundaryPenalty(const PenaltyData& penalty) {} diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index e38da9f7068..22f791b7271 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -33,6 +33,7 @@ #include "SimulatedAnnealingCore.h" +#include #include #include #include @@ -62,7 +63,6 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, MplObserver* graphics, utl::Logger* logger) : outline_(outline), - blocked_boundaries_(tree->blocked_boundaries), graphics_(graphics) { core_weights_ = weights; @@ -85,27 +85,19 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, logger_ = logger; macros_ = macros; - setBlockedBoundariesForIOs(); die_hpwl_ = tree->die_area.getPerimeter() / 2; + setAvailableRegionForPins(tree->available_regions_for_pins); } template -void SimulatedAnnealingCore::setBlockedBoundariesForIOs() +void SimulatedAnnealingCore::setAvailableRegionForPins( + const std::vector& regions) { - if (blocked_boundaries_.find(Boundary::L) != blocked_boundaries_.end()) { - left_is_blocked_ = true; - } - - if (blocked_boundaries_.find(Boundary::R) != blocked_boundaries_.end()) { - right_is_blocked_ = true; - } - - if (blocked_boundaries_.find(Boundary::B) != blocked_boundaries_.end()) { - bottom_is_blocked_ = true; - } - - if (blocked_boundaries_.find(Boundary::T) != blocked_boundaries_.end()) { - top_is_blocked_ = true; + for (const Rect& region : regions) { + Rect offset_region = region; + offset_region.moveHor(-outline_.xMin()); + offset_region.moveVer(-outline_.yMin()); + available_regions_for_pins_.push_back(offset_region); } } @@ -299,8 +291,8 @@ void SimulatedAnnealingCore::calWirelength() T& source = macros_[net.terminals.first]; T& target = macros_[net.terminals.second]; - if (target.isClusterOfUnplacedIOPins()) { - addBoundaryDistToWirelength(source, target, net.weight); + if (target.isClusterOfUnconstrainedIOPins()) { + addClosestAvailableRegionDistToWL(source, target, net.weight); continue; } @@ -324,7 +316,7 @@ void SimulatedAnnealingCore::calWirelength() } template -void SimulatedAnnealingCore::addBoundaryDistToWirelength( +void SimulatedAnnealingCore::addClosestAvailableRegionDistToWL( const T& macro, const T& io, const float net_weight) @@ -334,54 +326,22 @@ void SimulatedAnnealingCore::addBoundaryDistToWirelength( return; } - const float x1 = macro.getPinX(); - const float y1 = macro.getPinY(); - - Boundary constraint_boundary = io_cluster->getConstraintBoundary(); - - if (constraint_boundary == NONE) { - // We need to use the bbox of the SoftMacro and NOT the Cluster to - // get shape of the cluster of unconstrained IOs - which has the - // shape of the die but it's offset based on the current outline. - // Reminder: - // - The SoftMacro bbox is the bbox w.r.t to the current outline. - // - The Cluster bbox is the bbox w.r.t. to the origin of the actual - // die area. - const Rect& offset_die = io.getBBox(); - - float dist_to_left = die_hpwl_; - if (!left_is_blocked_) { - dist_to_left = std::abs(x1 - die.xMin()); - } - - float dist_to_right = die_hpwl_; - if (!right_is_blocked_) { - dist_to_right = std::abs(x1 - die.xMax()); - } - - float dist_to_bottom = die_hpwl_; - if (!bottom_is_blocked_) { - dist_to_right = std::abs(y1 - die.yMin()); - } + if (available_regions_for_pins_.empty()) { + logger_->critical( + utl::MPL, 47, "The unconstrained pins have no available region!"); + } - float dist_to_top = die_hpwl_; - if (!top_is_blocked_) { - dist_to_top = std::abs(y1 - die.yMax()); + float dist_to_closest_available_region = std::numeric_limits::max(); + for (const Rect& region : available_regions_for_pins_) { + const float dist_to_available_region + = computeDistance(/* from */ {macro.getPinX(), macro.getPinY()}, + /* to */ {region.getX(), region.getY()}); + if (dist_to_available_region < dist_to_closest_available_region) { + dist_to_closest_available_region = dist_to_available_region; } - - wirelength_ - += net_weight - * std::min( - {dist_to_left, dist_to_right, dist_to_bottom, dist_to_top}); - } else if (constraint_boundary == Boundary::L - || constraint_boundary == Boundary::R) { - const float x2 = io.getPinX(); - wirelength_ += net_weight * std::abs(x2 - x1); - } else if (constraint_boundary == Boundary::T - || constraint_boundary == Boundary::B) { - const float y2 = io.getPinY(); - wirelength_ += net_weight * std::abs(y2 - y1); } + + wirelength_ += net_weight * dist_to_closest_available_region; } // We consider the macro outside the outline based on the location of diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index c488b0c0a2e..430217c5152 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -125,8 +125,8 @@ class SimulatedAnnealingCore void fastSA(); + void setAvailableRegionForPins(const std::vector& regions); void initSequencePair(); - void setBlockedBoundariesForIOs(); void updateBestValidResult(); void useBestValidResult(); @@ -134,9 +134,9 @@ class SimulatedAnnealingCore virtual void calPenalty() = 0; void calOutlinePenalty(); void calWirelength(); - void addBoundaryDistToWirelength(const T& macro, - const T& io, - float net_weight); + void addClosestAvailableRegionDistToWL(const T& macro, + const T& io, + float net_weight); bool isOutsideTheOutline(const T& macro) const; void calGuidancePenalty(); void calFencePenalty(); @@ -167,9 +167,7 @@ class SimulatedAnnealingCore // The max cost for distance to boundary wirelength computation // when one of the SoftMacros is a cluster of unplaced IO pins. float die_hpwl_; - - // Boundaries blocked for IO pins - std::set blocked_boundaries_; + std::vector available_regions_for_pins_; // Number of macros that will actually be part of the sequence pair int macros_to_place_ = 0; @@ -249,13 +247,6 @@ class SimulatedAnnealingCore static constexpr float acc_tolerance_ = 0.001; bool has_initial_sequence_pair_ = false; - - // Blocked boundaries data is kept in bools to avoid overhead - // during SA steps. - bool left_is_blocked_ = false; - bool right_is_blocked_ = false; - bool bottom_is_blocked_ = false; - bool top_is_blocked_ = false; }; // SACore wrapper function diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index e89fa8ef57c..65e80723595 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -113,15 +113,21 @@ struct PhysicalHierarchy std::unique_ptr root; PhysicalHierarchyMaps maps; - std::set blocked_boundaries; // TODO: remove + std::vector available_regions_for_pins; std::set unblocked_boundaries; // TODO: remove float halo_width{0.0f}; float halo_height{0.0f}; float macro_with_halo_area{0.0f}; + + Rect die_area; + + // The constraint set by the user. Rect global_fence; + + // The actual area used by MPL - computed using the dimensions + // of the core versus the global fence set by the user. Rect floorplan_shape; - Rect die_area; bool has_io_clusters{true}; bool has_only_unconstrained_ios{false}; diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp index 3ab5b6e1545..d6c482ad87d 100644 --- a/src/mpl/src/graphics.cpp +++ b/src/mpl/src/graphics.cpp @@ -310,43 +310,16 @@ void Graphics::setMaxLevel(const int max_level) void Graphics::finishedClustering(PhysicalHierarchy* tree) { root_ = tree->root.get(); - setXMarksSizeAndPosition(tree->blocked_boundaries); + setXMarksSize(); } -void Graphics::setXMarksSizeAndPosition( - const std::set& blocked_boundaries) +// Mark to indicate blocked regions for pins. +void Graphics::setXMarksSize() { - const odb::Rect die = block_->getDieArea(); + const odb::Rect& die = block_->getDieArea(); // Not too big/small - x_mark_size_ = (die.dx() + die.dy()) * 0.03; - - for (Boundary boundary : blocked_boundaries) { - odb::Point x_mark_point; - - switch (boundary) { - case L: { - x_mark_point = odb::Point(die.xMin(), die.yCenter()); - break; - } - case R: { - x_mark_point = odb::Point(die.xMax(), die.yCenter()); - break; - } - case B: { - x_mark_point = odb::Point(die.xCenter(), die.yMin()); - break; - } - case T: { - x_mark_point = odb::Point(die.xCenter(), die.yMax()); - break; - } - case NONE: - break; - } - - blocked_boundary_to_mark_[boundary] = x_mark_point; - } + x_mark_size_ = (die.dx() + die.dy()) * 0.02; } void Graphics::drawCluster(Cluster* cluster, gui::Painter& painter) @@ -597,8 +570,8 @@ void Graphics::drawBlockedBoundariesIndication(gui::Painter& painter) painter.setPen(gui::Painter::red, true); painter.setBrush(gui::Painter::transparent); - for (const auto [boundary, x_mark_point] : blocked_boundary_to_mark_) { - painter.drawX(x_mark_point.getX(), x_mark_point.getY(), x_mark_size_); + for (const odb::Rect& region : blocked_regions_for_pins_) { + painter.drawX(region.xCenter(), region.yCenter(), x_mark_size_); } } @@ -610,7 +583,7 @@ void Graphics::drawBundledNets(gui::Painter& painter, const T& source = macros[bundled_net.terminals.first]; const T& target = macros[bundled_net.terminals.second]; - if (target.isClusterOfUnplacedIOPins()) { + if (target.isClusterOfUnconstrainedIOPins()) { drawDistToIoConstraintBoundary(painter, source, target); continue; } @@ -633,47 +606,38 @@ void Graphics::drawDistToIoConstraintBoundary(gui::Painter& painter, const T& macro, const T& io) { - // if (isOutsideTheOutline(macro)) { - // return; - // } - - // Cluster* io_cluster = io.getCluster(); - - // const int x1 = block_->micronsToDbu(macro.getPinX()); - // const int y1 = block_->micronsToDbu(macro.getPinY()); - // odb::Point from(x1, y1); - - // odb::Point to; - // Boundary constraint_boundary = io_cluster->getConstraintBoundary(); - - // if (constraint_boundary == Boundary::L - // || constraint_boundary == Boundary::R) { - // const int x2 = block_->micronsToDbu(io.getPinX()); - // const int y2 = block_->micronsToDbu(macro.getPinY()); - // to.setX(x2); - // to.setY(y2); - // } else if (constraint_boundary == Boundary::B - // || constraint_boundary == Boundary::T) { - // const int x2 = block_->micronsToDbu(macro.getPinX()); - // const int y2 = block_->micronsToDbu(io.getPinY()); - // to.setX(x2); - // to.setY(y2); - // } else { - // // For NONE, the shape of the io cluster is the die area. - // const Rect die = io_cluster->getBBox(); - // Boundary closest_unblocked_boundary - // = getClosestUnblockedBoundary(macro, die); - - // to = getClosestBoundaryPoint(macro, die, closest_unblocked_boundary); - // } - - // addOutlineOffsetToLine(from, to); - - // painter.drawLine(from, to); - // painter.drawString(to.getX(), - // to.getY(), - // gui::Painter::CENTER, - // toString(constraint_boundary)); + if (isOutsideTheOutline(macro)) { + return; + } + + const float x1 = macro.getPinX(); + const float y1 = macro.getPinY(); + + odb::Point from(block_->micronsToDbu(x1), block_->micronsToDbu(y1)); + from.addX(outline_.xMin()); + from.addY(outline_.yMin()); + + odb::Point to; + float dist_to_closest_available_region = std::numeric_limits::max(); + for (const odb::Rect& dbu_region : available_regions_for_pins_) { + const Rect micron_region(block_->dbuToMicrons(dbu_region.xMin()), + block_->dbuToMicrons(dbu_region.yMin()), + block_->dbuToMicrons(dbu_region.xMax()), + block_->dbuToMicrons(dbu_region.yMax())); + + const float dist_to_available_region = computeDistance( + /* from */ {x1, y1}, + /* to */ {micron_region.getX(), micron_region.getY()}); + if (dist_to_available_region < dist_to_closest_available_region) { + dist_to_closest_available_region = dist_to_available_region; + to = {block_->micronsToDbu(micron_region.getX()), + block_->micronsToDbu(micron_region.getY())}; + } + } + + painter.drawLine(from, to); + painter.drawString( + to.getX(), to.getY(), gui::Painter::CENTER, "Unconstrained IOs"); } template @@ -683,36 +647,6 @@ bool Graphics::isOutsideTheOutline(const T& macro) const || block_->micronsToDbu(macro.getPinY()) > outline_.dy(); } -// Here, we have to manually decompensate the offset of the -// coordinates that come from the cluster. -template -odb::Point Graphics::getClosestBoundaryPoint(const T& macro, - const Rect& die, - Boundary closest_boundary) -{ - odb::Point to; - - if (closest_boundary == Boundary::L) { - to.setX(block_->micronsToDbu(die.xMin())); - to.setY(block_->micronsToDbu(macro.getPinY())); - to.addX(-outline_.xMin()); - } else if (closest_boundary == Boundary::R) { - to.setX(block_->micronsToDbu(die.xMax())); - to.setY(block_->micronsToDbu(macro.getPinY())); - to.addX(-outline_.xMin()); - } else if (closest_boundary == Boundary::B) { - to.setX(block_->micronsToDbu(macro.getPinX())); - to.setY(block_->micronsToDbu(die.yMin())); - to.addY(-outline_.yMin()); - } else { // Top - to.setX(block_->micronsToDbu(macro.getPinX())); - to.setY(block_->micronsToDbu(die.yMax())); - to.addY(-outline_.yMin()); - } - - return to; -} - void Graphics::addOutlineOffsetToLine(odb::Point& from, odb::Point& to) { from.addX(outline_.xMin()); @@ -721,55 +655,6 @@ void Graphics::addOutlineOffsetToLine(odb::Point& from, odb::Point& to) to.addY(outline_.yMin()); } -template -Boundary Graphics::getClosestUnblockedBoundary(const T& macro, const Rect& die) -{ - const float macro_x = macro.getPinX(); - const float macro_y = macro.getPinY(); - - float shortest_distance = std::numeric_limits::max(); - Boundary closest_boundary = Boundary::NONE; - - if (!isBlockedBoundary(Boundary::L)) { - const float dist_to_left = std::abs(macro_x - die.xMin()); - if (dist_to_left < shortest_distance) { - shortest_distance = dist_to_left; - closest_boundary = Boundary::L; - } - } - - if (!isBlockedBoundary(Boundary::R)) { - const float dist_to_right = std::abs(macro_x - die.xMax()); - if (dist_to_right < shortest_distance) { - shortest_distance = dist_to_right; - closest_boundary = Boundary::R; - } - } - - if (!isBlockedBoundary(Boundary::B)) { - const float dist_to_bottom = std::abs(macro_y - die.yMin()); - if (dist_to_bottom < shortest_distance) { - shortest_distance = dist_to_bottom; - closest_boundary = Boundary::B; - } - } - - if (!isBlockedBoundary(Boundary::T)) { - const float dist_to_top = std::abs(macro_y - die.yMax()); - if (dist_to_top < shortest_distance) { - closest_boundary = Boundary::T; - } - } - - return closest_boundary; -} - -bool Graphics::isBlockedBoundary(Boundary boundary) -{ - return blocked_boundary_to_mark_.find(boundary) - != blocked_boundary_to_mark_.end(); -} - // Give some transparency to mixed and hard so we can see overlap with // macro blockages. void Graphics::setSoftMacroBrush(gui::Painter& painter, @@ -858,6 +743,18 @@ void Graphics::setFences(const std::map& fences) fences_ = fences; } +void Graphics::setBlockedRegionsForPins( + const std::vector& blocked_regions_for_pins) +{ + blocked_regions_for_pins_ = blocked_regions_for_pins; +} + +void Graphics::setAvailableRegionsForPins( + const std::vector& available_regions_for_pins) +{ + available_regions_for_pins_ = available_regions_for_pins; +} + void Graphics::eraseDrawing() { // Ensure we don't try to access the clusters after they were deleted @@ -870,7 +767,7 @@ void Graphics::eraseDrawing() bundled_nets_.clear(); outline_.reset(0, 0, 0, 0); outlines_.clear(); - blocked_boundary_to_mark_.clear(); + blocked_regions_for_pins_.clear(); guides_.clear(); } diff --git a/src/mpl/src/graphics.h b/src/mpl/src/graphics.h index 23ae6485f98..1c0300163fd 100644 --- a/src/mpl/src/graphics.h +++ b/src/mpl/src/graphics.h @@ -90,11 +90,15 @@ class Graphics : public gui::Renderer, public MplObserver void setCurrentCluster(Cluster* current_cluster) override; void setGuides(const std::map& guides) override; void setFences(const std::map& fences) override; + void setBlockedRegionsForPins( + const std::vector& blocked_regions_for_pins) override; + void setAvailableRegionsForPins( + const std::vector& available_regions_for_pins) override; void eraseDrawing() override; private: - void setXMarksSizeAndPosition(const std::set& blocked_boundaries); + void setXMarksSize(); void resetPenalties(); void drawCluster(Cluster* cluster, gui::Painter& painter); void drawBlockedBoundariesIndication(gui::Painter& painter); @@ -112,13 +116,6 @@ class Graphics : public gui::Renderer, public MplObserver const T& io); template bool isOutsideTheOutline(const T& macro) const; - template - odb::Point getClosestBoundaryPoint(const T& macro, - const Rect& die, - Boundary closest_boundary); - template - Boundary getClosestUnblockedBoundary(const T& macro, const Rect& die); - bool isBlockedBoundary(Boundary boundary); void addOutlineOffsetToLine(odb::Point& from, odb::Point& to); void setSoftMacroBrush(gui::Painter& painter, const SoftMacro& soft_macro); void fetchSoftAndHard(Cluster* parent, @@ -140,7 +137,8 @@ class Graphics : public gui::Renderer, public MplObserver odb::Rect outline_; int target_cluster_id_{-1}; std::vector> outlines_; - std::map blocked_boundary_to_mark_; + std::vector blocked_regions_for_pins_; + std::vector available_regions_for_pins_; // In Soft SA, we're shaping/placing the children of a certain parent, // so for this case, the current cluster is actually the current parent. @@ -148,7 +146,7 @@ class Graphics : public gui::Renderer, public MplObserver std::map guides_; // Id -> Guidance Region std::map fences_; // Id -> Fence - int x_mark_size_{0}; // For blocked boundaries. + int x_mark_size_{0}; // For blocked regions. bool active_ = true; bool coarse_; diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 867d9bf4460..07c6acbd701 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -904,10 +904,19 @@ void HierRTLMP::createPinAccessBlockages() BoundaryToRegionsMap boundary_to_blocked_regions = getBoundaryToBlockedRegionsMap(blocked_regions_for_pins); - - available_regions_for_pins_ + std::vector dbu_available_regions = computeAvailableRegions(boundary_to_blocked_regions); + if (graphics_) { + graphics_->setBlockedRegionsForPins(blocked_regions_for_pins); + graphics_->setAvailableRegionsForPins(dbu_available_regions); + } + + for (const odb::Rect& dbu_available_region : dbu_available_regions) { + tree_->available_regions_for_pins.push_back( + dbuToMicrons(dbu_available_region)); + } + createBlockagesForAvailableRegions(); } else { createBlockagesForConstraintRegions(); @@ -917,15 +926,14 @@ void HierRTLMP::createPinAccessBlockages() void HierRTLMP::createBlockagesForAvailableRegions() { float io_span = 0.0f; - for (const odb::Rect& available_region : available_regions_for_pins_) { - const Rect region = dbuToMicrons(available_region); - io_span += region.getPerimeter() / 2; + for (const Rect& available_region : tree_->available_regions_for_pins) { + io_span += available_region.getPerimeter() / 2; } const float depth = computePinAccessBaseDepth(io_span); - for (const odb::Rect& available_region : available_regions_for_pins_) { - createPinAccessBlockage(dbuToMicrons(available_region), depth); + for (const Rect& available_region : tree_->available_regions_for_pins) { + createPinAccessBlockage(available_region, depth); } } @@ -3258,7 +3266,6 @@ odb::Rect HierRTLMP::getRect(Boundary boundary) return boundary_rect; } - template void HierRTLMP::printPlacementResult(Cluster* parent, const Rect& outline, diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index c86bc128a34..9e9adfc3d7a 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -326,8 +326,7 @@ class HierRTLMP std::vector placement_blockages_; std::vector macro_blockages_; std::vector io_blockages_; - std::vector available_regions_for_pins_; - std::map boundary_to_io_blockage_; // TODO: remove + std::map boundary_to_io_blockage_; // TODO: remove // Fast SA hyperparameter float init_prob_ = 0.9; @@ -389,7 +388,7 @@ class Pusher odb::dbBlock* block_; odb::Rect core_; - std::map boundary_to_io_blockage_; // TODO: remove + std::map boundary_to_io_blockage_; // TODO: remove std::vector hard_macros_; }; diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp index 6e0fbaf950f..449aa3f082e 100644 --- a/src/mpl/src/object.cpp +++ b/src/mpl/src/object.cpp @@ -851,6 +851,15 @@ bool HardMacro::isClusterOfUnplacedIOPins() const return cluster_->isClusterOfUnplacedIOPins(); } +bool HardMacro::isClusterOfUnconstrainedIOPins() const +{ + if (!cluster_) { + return false; + } + + return cluster_->isClusterOfUnconstrainedIOPins(); +} + // Get Physical Information // Note that the default X and Y include halo_width void HardMacro::setLocation(const std::pair& location) @@ -1343,6 +1352,15 @@ bool SoftMacro::isClusterOfUnplacedIOPins() const return cluster_->isClusterOfUnplacedIOPins(); } +bool SoftMacro::isClusterOfUnconstrainedIOPins() const +{ + if (!cluster_) { + return false; + } + + return cluster_->isClusterOfUnconstrainedIOPins(); +} + void SoftMacro::setLocationF(float x, float y) { x_ = x; diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index 78ec5fa024b..8c138f9bbf2 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -48,7 +48,6 @@ namespace odb { class Rect; -class Point; class dbInst; class dbModule; class dbDatabase; @@ -69,7 +68,6 @@ class SoftMacro; class Cluster; using UniqueClusterVector = std::vector>; -using Point = std::pair; // **************************************************************************** // This file includes the basic functions and basic classes for the HierRTLMP @@ -363,6 +361,7 @@ class HardMacro void setCluster(Cluster* cluster) { cluster_ = cluster; } Cluster* getCluster() const { return cluster_; } bool isClusterOfUnplacedIOPins() const; + bool isClusterOfUnconstrainedIOPins() const; // Get Physical Information // Note that the default X and Y include halo_width @@ -537,6 +536,7 @@ class SoftMacro bool isStdCellCluster() const; bool isMixedCluster() const; bool isClusterOfUnplacedIOPins() const; + bool isClusterOfUnconstrainedIOPins() const; void setLocationF(float x, float y); void setShapeF(float width, float height); int getNumMacro() const; diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index e400c5b39c0..e7a8a581746 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -37,6 +37,8 @@ namespace mpl { +using Point = std::pair; + struct SACoreWeights { float area{0.0f}; @@ -62,4 +64,11 @@ struct PenaltyData float normalization_factor{0.0f}; }; +inline float computeDistance(const Point& a, const Point& b) +{ + const float dx = std::abs(a.first - b.first); + const float dy = std::abs(a.second - b.second); + return std::sqrt(std::pow(dx, 2) + std::pow(dy, 2)); +} + } // namespace mpl \ No newline at end of file diff --git a/src/mpl/test/CMakeLists.txt b/src/mpl/test/CMakeLists.txt index 0a97aa50ed1..37101a99185 100644 --- a/src/mpl/test/CMakeLists.txt +++ b/src/mpl/test/CMakeLists.txt @@ -10,6 +10,8 @@ or_integration_tests( io_constraints3 io_constraints4 io_constraints5 + io_constraints6 + io_constraints7 io_pads1 orientation_improve1 orientation_improve2 diff --git a/src/mpl/test/io_constraints6.defok b/src/mpl/test/io_constraints6.defok new file mode 100644 index 00000000000..8bd1649b1e2 --- /dev/null +++ b/src/mpl/test/io_constraints6.defok @@ -0,0 +1,538 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN io_constraints1 ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 300000 250000 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; +COMPONENTS 401 ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8290 ) S ; + - _001_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _002_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _003_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _004_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _005_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _006_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _007_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _008_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _009_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _010_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _011_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _012_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _013_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _014_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _015_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _016_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _017_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _018_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _019_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _020_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _021_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _022_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _023_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _024_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _025_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _026_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _027_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _028_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _029_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _030_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _031_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _032_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _033_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _034_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _035_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _036_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _037_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _038_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _039_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _040_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _041_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _042_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _043_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _044_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _045_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _046_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _047_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _048_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _049_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _050_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _051_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _052_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _053_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _054_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _055_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _056_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _057_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _058_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _059_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _060_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _061_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _062_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _063_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _064_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _065_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _066_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _067_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _068_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _069_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _070_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _071_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _072_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _073_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _074_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _075_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _076_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _077_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _078_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _079_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _080_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _081_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _082_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _083_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _084_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _085_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _086_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _087_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _088_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _089_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _090_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _091_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _092_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _093_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _094_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _095_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _096_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _097_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _098_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _099_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _100_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _101_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _102_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _103_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _104_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _105_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _106_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _107_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _108_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _109_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _110_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _111_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _112_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _113_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _114_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _115_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _116_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _117_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _118_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _119_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _120_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _121_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _122_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _123_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _124_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _125_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _126_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _127_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _128_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _129_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _130_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _131_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _132_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _133_ DFF_X1 + PLACED ( 38680 123234 ) N ; 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+ - _156_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _157_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _158_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _159_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _160_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _161_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _162_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _163_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _164_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _165_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _166_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _167_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _168_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _169_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _170_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _171_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _172_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _173_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _174_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _175_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _176_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _177_ DFF_X1 + PLACED ( 38680 123234 ) N ; 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+ - _200_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _201_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _202_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _203_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _204_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _205_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _206_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _207_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _208_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _209_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _210_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _211_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _212_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _213_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _214_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _215_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _216_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _217_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _218_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _219_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _220_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _221_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _222_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _223_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _224_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _225_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _226_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _227_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _228_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _229_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _230_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _231_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _232_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _233_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _234_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _235_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _236_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _237_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _238_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _239_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _240_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _241_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _242_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _243_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _244_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _245_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _246_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _247_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _248_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _249_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _250_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _251_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _252_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _253_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _254_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _255_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _256_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _257_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _258_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _259_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _260_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _261_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _262_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _263_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _264_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _265_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _266_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _267_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _268_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _269_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _270_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _271_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _272_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _273_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _274_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _275_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _276_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _277_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _278_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _279_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _280_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _281_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _282_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _283_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _284_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _285_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _286_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _287_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _288_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _289_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _290_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _291_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _292_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _293_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _294_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _295_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _296_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _297_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _298_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _299_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _300_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _301_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _302_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _303_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _304_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _305_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _306_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _307_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _308_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _309_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _310_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _311_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _312_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _313_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _314_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _315_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _316_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _317_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _318_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _319_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _320_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _321_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _322_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _323_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _324_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _325_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _326_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _327_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _328_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _329_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _330_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _331_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _332_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _333_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _334_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _335_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _336_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _337_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _338_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _339_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _340_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _341_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _342_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _343_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _344_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _345_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _346_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _347_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _348_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _349_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _350_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _351_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _352_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _353_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _354_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _355_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _356_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _357_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _358_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _359_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _360_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _361_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _362_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _363_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _364_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _365_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _366_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _367_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _368_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _369_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _370_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _371_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _372_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _373_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _374_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _375_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _376_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _377_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _378_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _379_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _380_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _381_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _382_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _383_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _384_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _385_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _386_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _387_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _388_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _389_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _390_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _391_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _392_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _393_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _394_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _395_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _396_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _397_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _398_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _399_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - _400_ DFF_X1 + PLACED ( 38680 123234 ) N ; +END COMPONENTS +PINS 3 ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + PLACED ( 254430 140 ) N ; + - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + PLACED ( 238750 140 ) N ; + - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + PLACED ( 234270 140 ) N ; +END PINS +NETS 3 ; + - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ; + - io_2 ( PIN io_2 ) ( MACRO_1 O1 ) + USE SIGNAL ; + - io_3 ( PIN io_3 ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/mpl/test/io_constraints6.ok b/src/mpl/test/io_constraints6.ok new file mode 100644 index 00000000000..b53c580708f --- /dev/null +++ b/src/mpl/test/io_constraints6.ok @@ -0,0 +1,28 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: testcases/macro_only.lef, created 9 library cells +[INFO ODB-0128] Design: io_constraints1 +[INFO ODB-0130] Created 3 pins. +[INFO ODB-0131] Created 401 components and 2402 component-terminals. +[INFO ODB-0133] Created 2 nets and 2 connections. +Found 1 macro blocks. +Using 2 tracks default min distance between IO pins. +[INFO PPL-0001] Number of slots 966 +[INFO PPL-0002] Number of I/O 3 +[INFO PPL-0003] Number of I/O w/sink 2 +[INFO PPL-0004] Number of I/O w/o sink 1 +[INFO PPL-0012] I/O nets HPWL: 221.59 um. +Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) + Number of std cell instances: 400 + Area of std cell instances: 1808.79 + Number of macros: 1 + Area of macros: 10000.00 + Halo width: 4.00 + Halo height: 4.00 + Area of macros with halos: 11664.00 + Area of std cell instances + Area of macros: 11808.79 + Floorplan area: 18678.79 + Design Utilization: 0.63 + Floorplan Utilization: 0.21 + Manufacturing Grid: 10 + +No differences found. diff --git a/src/mpl/test/io_constraints6.tcl b/src/mpl/test/io_constraints6.tcl new file mode 100644 index 00000000000..8b521996673 --- /dev/null +++ b/src/mpl/test/io_constraints6.tcl @@ -0,0 +1,23 @@ +# Test if the bundled nets inside annealing are correct for a block with +# two blocked regions for pins and Macro -> IO connections. +source "helpers.tcl" + +read_lef Nangate45/Nangate45.lef +read_lef testcases/macro_only.lef + +read_liberty Nangate45/Nangate45_fast.lib + +read_def testcases/io_constraints6.def + +# Run random PPL to incorporate the -exclude constraints into ODB +place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 \ + -exclude right:40-125 \ + -exclude top:10-150 + +set_thread_count 0 +rtl_macro_placer -report_directory results/io_constraints6 -halo_width 4.0 + +set def_file [make_result_file "io_constraints6.def"] +write_def $def_file +diff_files $def_file "io_constraints6.defok" + diff --git a/src/mpl/test/io_constraints7.defok b/src/mpl/test/io_constraints7.defok new file mode 100644 index 00000000000..19447be3129 --- /dev/null +++ b/src/mpl/test/io_constraints7.defok @@ -0,0 +1,538 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN io_constraints1 ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 300000 250000 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; +COMPONENTS 401 ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8150 ) N ; + - _001_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _002_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _003_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _004_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _005_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _006_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _007_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _008_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _009_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _010_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _011_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _012_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _013_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _014_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _015_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _016_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _017_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _018_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _019_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _020_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _021_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _022_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _023_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _024_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _025_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _026_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _027_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _028_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _029_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _030_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _031_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _032_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _033_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _034_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _035_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _036_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _037_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _038_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _039_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _040_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _041_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _042_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _043_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _044_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _045_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _046_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _047_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _048_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _049_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _050_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _051_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _052_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _053_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _054_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _055_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _056_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _057_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _058_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _059_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _060_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _061_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _062_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _063_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _064_ DFF_X1 + PLACED ( 254680 123234 ) N ; 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+ - _317_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _318_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _319_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _320_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _321_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _322_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _323_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _324_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _325_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _326_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _327_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _328_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _329_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _330_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _331_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _332_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _333_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _334_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _335_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _336_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _337_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _338_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _339_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _340_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _341_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _342_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _343_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _344_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _345_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _346_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _347_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _348_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _349_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _350_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _351_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _352_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _353_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _354_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _355_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _356_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _357_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _358_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _359_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _360_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _361_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _362_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _363_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _364_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _365_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _366_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _367_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _368_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _369_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _370_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _371_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _372_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _373_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _374_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _375_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _376_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _377_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _378_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _379_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _380_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _381_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _382_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _383_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _384_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _385_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _386_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _387_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _388_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _389_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _390_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _391_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _392_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _393_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _394_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _395_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _396_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _397_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _398_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _399_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - _400_ DFF_X1 + PLACED ( 254680 123234 ) N ; +END COMPONENTS +PINS 3 ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 140 164780 ) N ; + - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 140 147980 ) N ; + - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + PLACED ( 299860 178220 ) N ; +END PINS +NETS 3 ; + - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ; + - io_2 ( PIN io_2 ) ( MACRO_1 O1 ) + USE SIGNAL ; + - io_3 ( PIN io_3 ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/mpl/test/io_constraints7.ok b/src/mpl/test/io_constraints7.ok new file mode 100644 index 00000000000..c713c242c43 --- /dev/null +++ b/src/mpl/test/io_constraints7.ok @@ -0,0 +1,30 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: testcases/macro_only.lef, created 9 library cells +[INFO ODB-0128] Design: io_constraints1 +[INFO ODB-0130] Created 3 pins. +[INFO ODB-0131] Created 401 components and 2402 component-terminals. +[INFO ODB-0133] Created 2 nets and 2 connections. +[INFO PPL-0048] Restrict pins [ io_1 io_2 ] to region 70.00u-90.00u at the LEFT edge. +[INFO PPL-0048] Restrict pins [ io_3 ] to region 70.00u-90.00u at the RIGHT edge. +Found 1 macro blocks. +Using 2 tracks default min distance between IO pins. +[INFO PPL-0001] Number of slots 966 +[INFO PPL-0002] Number of I/O 3 +[INFO PPL-0003] Number of I/O w/sink 2 +[INFO PPL-0004] Number of I/O w/o sink 1 +[INFO PPL-0012] I/O nets HPWL: 181.38 um. +Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) + Number of std cell instances: 400 + Area of std cell instances: 1808.79 + Number of macros: 1 + Area of macros: 10000.00 + Halo width: 4.00 + Halo height: 4.00 + Area of macros with halos: 11664.00 + Area of std cell instances + Area of macros: 11808.79 + Floorplan area: 18678.79 + Design Utilization: 0.63 + Floorplan Utilization: 0.21 + Manufacturing Grid: 10 + +No differences found. diff --git a/src/mpl/test/io_constraints7.tcl b/src/mpl/test/io_constraints7.tcl new file mode 100644 index 00000000000..b2bf780783c --- /dev/null +++ b/src/mpl/test/io_constraints7.tcl @@ -0,0 +1,33 @@ +# Test if the bundled nets inside annealing are correct for a block with +# pins with different constraint regions and Macro -> IO connections. + +# +# +# +# TO DO: This test requires the fix terminal bug fix in order to work! +# +# +# + +source "helpers.tcl" + +read_lef Nangate45/Nangate45.lef +read_lef testcases/macro_only.lef + +read_liberty Nangate45/Nangate45_fast.lib + +read_def testcases/io_constraints6.def + +set_io_pin_constraint -pin_names {io_1 io_2} -region left:70-90 +set_io_pin_constraint -pin_names {io_3} -region right:70-90 + +# Run random PPL to incorporate the constraints into ODB +place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 + +set_thread_count 0 +rtl_macro_placer -report_directory results/io_constraints6 -halo_width 4.0 + +set def_file [make_result_file "io_constraints7.def"] +write_def $def_file +diff_files $def_file "io_constraints7.defok" + diff --git a/src/mpl/test/testcases/io_constraints6.def b/src/mpl/test/testcases/io_constraints6.def new file mode 100644 index 00000000000..e33e9f05980 --- /dev/null +++ b/src/mpl/test/testcases/io_constraints6.def @@ -0,0 +1,531 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN io_constraints1 ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 300000 250000 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; +COMPONENTS 401 ; + - MACRO_1 HM_100x100_1x1 ; + - _001_ DFF_X1 ; + - _002_ DFF_X1 ; + - _003_ DFF_X1 ; + - _004_ DFF_X1 ; + - _005_ DFF_X1 ; + - _006_ DFF_X1 ; + - _007_ DFF_X1 ; + - _008_ DFF_X1 ; + - _009_ DFF_X1 ; + - _010_ DFF_X1 ; + - _011_ DFF_X1 ; + - _012_ DFF_X1 ; + - _013_ DFF_X1 ; + - _014_ DFF_X1 ; + - _015_ DFF_X1 ; + - _016_ DFF_X1 ; + - _017_ DFF_X1 ; + - _018_ DFF_X1 ; + - _019_ DFF_X1 ; + - _020_ DFF_X1 ; + - _021_ DFF_X1 ; + - _022_ DFF_X1 ; + - _023_ DFF_X1 ; + - _024_ DFF_X1 ; + - _025_ DFF_X1 ; + - _026_ DFF_X1 ; + - _027_ DFF_X1 ; + - _028_ DFF_X1 ; + - _029_ DFF_X1 ; + - _030_ DFF_X1 ; + - _031_ DFF_X1 ; + - _032_ DFF_X1 ; + - _033_ DFF_X1 ; + - _034_ DFF_X1 ; + - _035_ DFF_X1 ; + - _036_ DFF_X1 ; + - _037_ DFF_X1 ; + - _038_ DFF_X1 ; + - _039_ DFF_X1 ; + - _040_ DFF_X1 ; + - _041_ DFF_X1 ; + - _042_ DFF_X1 ; + - _043_ DFF_X1 ; + - _044_ DFF_X1 ; + - _045_ DFF_X1 ; + - _046_ DFF_X1 ; + - _047_ DFF_X1 ; + - _048_ DFF_X1 ; + - _049_ DFF_X1 ; + - _050_ DFF_X1 ; + - _051_ DFF_X1 ; + - _052_ DFF_X1 ; + - _053_ DFF_X1 ; + - _054_ DFF_X1 ; + - _055_ DFF_X1 ; + - _056_ DFF_X1 ; + - _057_ DFF_X1 ; + - _058_ DFF_X1 ; + - _059_ DFF_X1 ; + - _060_ DFF_X1 ; + - _061_ DFF_X1 ; + - _062_ DFF_X1 ; + - _063_ DFF_X1 ; + - _064_ DFF_X1 ; + - _065_ DFF_X1 ; + - _066_ DFF_X1 ; + - _067_ DFF_X1 ; + - _068_ DFF_X1 ; + - _069_ DFF_X1 ; + - _070_ DFF_X1 ; + - _071_ DFF_X1 ; + - _072_ DFF_X1 ; + - _073_ DFF_X1 ; + - _074_ DFF_X1 ; + - _075_ DFF_X1 ; + - _076_ DFF_X1 ; + - _077_ DFF_X1 ; + - _078_ DFF_X1 ; + - _079_ DFF_X1 ; + - _080_ DFF_X1 ; + - _081_ DFF_X1 ; + - _082_ DFF_X1 ; + - _083_ DFF_X1 ; + - _084_ DFF_X1 ; + - _085_ DFF_X1 ; + - _086_ DFF_X1 ; + - _087_ DFF_X1 ; + - _088_ DFF_X1 ; + - _089_ DFF_X1 ; + - _090_ DFF_X1 ; + - _091_ DFF_X1 ; + - _092_ DFF_X1 ; + - _093_ DFF_X1 ; + - _094_ DFF_X1 ; + - _095_ DFF_X1 ; + - _096_ DFF_X1 ; + - _097_ DFF_X1 ; + - _098_ DFF_X1 ; + - _099_ DFF_X1 ; + - _100_ DFF_X1 ; + - _101_ DFF_X1 ; + - _102_ DFF_X1 ; + - _103_ DFF_X1 ; + - _104_ DFF_X1 ; + - _105_ DFF_X1 ; + - _106_ DFF_X1 ; + - _107_ DFF_X1 ; + - _108_ DFF_X1 ; + - _109_ DFF_X1 ; + - _110_ DFF_X1 ; + - _111_ DFF_X1 ; + - _112_ DFF_X1 ; + - _113_ DFF_X1 ; + - _114_ DFF_X1 ; + - _115_ DFF_X1 ; + - _116_ DFF_X1 ; + - _117_ DFF_X1 ; + - _118_ DFF_X1 ; + - _119_ DFF_X1 ; + - _120_ DFF_X1 ; + - _121_ DFF_X1 ; + - _122_ DFF_X1 ; + - _123_ DFF_X1 ; + - _124_ DFF_X1 ; + - _125_ DFF_X1 ; + - _126_ DFF_X1 ; + - _127_ DFF_X1 ; + - _128_ DFF_X1 ; + - _129_ DFF_X1 ; + - _130_ DFF_X1 ; + - _131_ DFF_X1 ; + - _132_ DFF_X1 ; + - _133_ DFF_X1 ; + - _134_ DFF_X1 ; + - _135_ DFF_X1 ; + - _136_ DFF_X1 ; + - _137_ DFF_X1 ; + - _138_ DFF_X1 ; + - _139_ DFF_X1 ; + - _140_ DFF_X1 ; + - _141_ DFF_X1 ; + - _142_ DFF_X1 ; + - _143_ DFF_X1 ; + - _144_ DFF_X1 ; + - _145_ DFF_X1 ; + - _146_ DFF_X1 ; + - _147_ DFF_X1 ; + - _148_ DFF_X1 ; + - _149_ DFF_X1 ; + - _150_ DFF_X1 ; + - _151_ DFF_X1 ; + - _152_ DFF_X1 ; + - _153_ DFF_X1 ; + - _154_ DFF_X1 ; + - _155_ DFF_X1 ; + - _156_ DFF_X1 ; + - _157_ DFF_X1 ; + - _158_ DFF_X1 ; + - _159_ DFF_X1 ; + - _160_ DFF_X1 ; + - _161_ DFF_X1 ; + - _162_ DFF_X1 ; + - _163_ DFF_X1 ; + - _164_ DFF_X1 ; + - _165_ DFF_X1 ; + - _166_ DFF_X1 ; + - _167_ DFF_X1 ; + - _168_ DFF_X1 ; + - _169_ DFF_X1 ; + - _170_ DFF_X1 ; + - _171_ DFF_X1 ; + - _172_ DFF_X1 ; + - _173_ DFF_X1 ; + - _174_ DFF_X1 ; + - _175_ DFF_X1 ; + - _176_ DFF_X1 ; + - _177_ DFF_X1 ; + - _178_ DFF_X1 ; + - _179_ DFF_X1 ; + - _180_ DFF_X1 ; + - _181_ DFF_X1 ; + - _182_ DFF_X1 ; + - _183_ DFF_X1 ; + - _184_ DFF_X1 ; + - _185_ DFF_X1 ; + - _186_ DFF_X1 ; + - _187_ DFF_X1 ; + - _188_ DFF_X1 ; + - _189_ DFF_X1 ; + - _190_ DFF_X1 ; + - _191_ DFF_X1 ; + - _192_ DFF_X1 ; + - _193_ DFF_X1 ; + - _194_ DFF_X1 ; + - _195_ DFF_X1 ; + - _196_ DFF_X1 ; + - _197_ DFF_X1 ; + - _198_ DFF_X1 ; + - _199_ DFF_X1 ; + - _200_ DFF_X1 ; + - _201_ DFF_X1 ; + - _202_ DFF_X1 ; + - _203_ DFF_X1 ; + - _204_ DFF_X1 ; + - _205_ DFF_X1 ; + - _206_ DFF_X1 ; + - _207_ DFF_X1 ; + - _208_ DFF_X1 ; + - _209_ DFF_X1 ; + - _210_ DFF_X1 ; + - _211_ DFF_X1 ; + - _212_ DFF_X1 ; + - _213_ DFF_X1 ; + - _214_ DFF_X1 ; + - _215_ DFF_X1 ; + - _216_ DFF_X1 ; + - _217_ DFF_X1 ; + - _218_ DFF_X1 ; + - _219_ DFF_X1 ; + - _220_ DFF_X1 ; + - _221_ DFF_X1 ; + - _222_ DFF_X1 ; + - _223_ DFF_X1 ; + - _224_ DFF_X1 ; + - _225_ DFF_X1 ; + - _226_ DFF_X1 ; + - _227_ DFF_X1 ; + - _228_ DFF_X1 ; + - _229_ DFF_X1 ; + - _230_ DFF_X1 ; + - _231_ DFF_X1 ; + - _232_ DFF_X1 ; + - _233_ DFF_X1 ; + - _234_ DFF_X1 ; + - _235_ DFF_X1 ; + - _236_ DFF_X1 ; + - _237_ DFF_X1 ; + - _238_ DFF_X1 ; + - _239_ DFF_X1 ; + - _240_ DFF_X1 ; + - _241_ DFF_X1 ; + - _242_ DFF_X1 ; + - _243_ DFF_X1 ; + - _244_ DFF_X1 ; + - _245_ DFF_X1 ; + - _246_ DFF_X1 ; + - _247_ DFF_X1 ; + - _248_ DFF_X1 ; + - _249_ DFF_X1 ; + - _250_ DFF_X1 ; + - _251_ DFF_X1 ; + - _252_ DFF_X1 ; + - _253_ DFF_X1 ; + - _254_ DFF_X1 ; + - _255_ DFF_X1 ; + - _256_ DFF_X1 ; + - _257_ DFF_X1 ; + - _258_ DFF_X1 ; + - _259_ DFF_X1 ; + - _260_ DFF_X1 ; + - _261_ DFF_X1 ; + - _262_ DFF_X1 ; + - _263_ DFF_X1 ; + - _264_ DFF_X1 ; + - _265_ DFF_X1 ; + - _266_ DFF_X1 ; + - _267_ DFF_X1 ; + - _268_ DFF_X1 ; + - _269_ DFF_X1 ; + - _270_ DFF_X1 ; + - _271_ DFF_X1 ; + - _272_ DFF_X1 ; + - _273_ DFF_X1 ; + - _274_ DFF_X1 ; + - _275_ DFF_X1 ; + - _276_ DFF_X1 ; + - _277_ DFF_X1 ; + - _278_ DFF_X1 ; + - _279_ DFF_X1 ; + - _280_ DFF_X1 ; + - _281_ DFF_X1 ; + - _282_ DFF_X1 ; + - _283_ DFF_X1 ; + - _284_ DFF_X1 ; + - _285_ DFF_X1 ; + - _286_ DFF_X1 ; + - _287_ DFF_X1 ; + - _288_ DFF_X1 ; + - _289_ DFF_X1 ; + - _290_ DFF_X1 ; + - _291_ DFF_X1 ; + - _292_ DFF_X1 ; + - _293_ DFF_X1 ; + - _294_ DFF_X1 ; + - _295_ DFF_X1 ; + - _296_ DFF_X1 ; + - _297_ DFF_X1 ; + - _298_ DFF_X1 ; + - _299_ DFF_X1 ; + - _300_ DFF_X1 ; + - _301_ DFF_X1 ; + - _302_ DFF_X1 ; + - _303_ DFF_X1 ; + - _304_ DFF_X1 ; + - _305_ DFF_X1 ; + - _306_ DFF_X1 ; + - _307_ DFF_X1 ; + - _308_ DFF_X1 ; + - _309_ DFF_X1 ; + - _310_ DFF_X1 ; + - _311_ DFF_X1 ; + - _312_ DFF_X1 ; + - _313_ DFF_X1 ; + - _314_ DFF_X1 ; + - _315_ DFF_X1 ; + - _316_ DFF_X1 ; + - _317_ DFF_X1 ; + - _318_ DFF_X1 ; + - _319_ DFF_X1 ; + - _320_ DFF_X1 ; + - _321_ DFF_X1 ; + - _322_ DFF_X1 ; + - _323_ DFF_X1 ; + - _324_ DFF_X1 ; + - _325_ DFF_X1 ; + - _326_ DFF_X1 ; + - _327_ DFF_X1 ; + - _328_ DFF_X1 ; + - _329_ DFF_X1 ; + - _330_ DFF_X1 ; + - _331_ DFF_X1 ; + - _332_ DFF_X1 ; + - _333_ DFF_X1 ; + - _334_ DFF_X1 ; + - _335_ DFF_X1 ; + - _336_ DFF_X1 ; + - _337_ DFF_X1 ; + - _338_ DFF_X1 ; + - _339_ DFF_X1 ; + - _340_ DFF_X1 ; + - _341_ DFF_X1 ; + - _342_ DFF_X1 ; + - _343_ DFF_X1 ; + - _344_ DFF_X1 ; + - _345_ DFF_X1 ; + - _346_ DFF_X1 ; + - _347_ DFF_X1 ; + - _348_ DFF_X1 ; + - _349_ DFF_X1 ; + - _350_ DFF_X1 ; + - _351_ DFF_X1 ; + - _352_ DFF_X1 ; + - _353_ DFF_X1 ; + - _354_ DFF_X1 ; + - _355_ DFF_X1 ; + - _356_ DFF_X1 ; + - _357_ DFF_X1 ; + - _358_ DFF_X1 ; + - _359_ DFF_X1 ; + - _360_ DFF_X1 ; + - _361_ DFF_X1 ; + - _362_ DFF_X1 ; + - _363_ DFF_X1 ; + - _364_ DFF_X1 ; + - _365_ DFF_X1 ; + - _366_ DFF_X1 ; + - _367_ DFF_X1 ; + - _368_ DFF_X1 ; + - _369_ DFF_X1 ; + - _370_ DFF_X1 ; + - _371_ DFF_X1 ; + - _372_ DFF_X1 ; + - _373_ DFF_X1 ; + - _374_ DFF_X1 ; + - _375_ DFF_X1 ; + - _376_ DFF_X1 ; + - _377_ DFF_X1 ; + - _378_ DFF_X1 ; + - _379_ DFF_X1 ; + - _380_ DFF_X1 ; + - _381_ DFF_X1 ; + - _382_ DFF_X1 ; + - _383_ DFF_X1 ; + - _384_ DFF_X1 ; + - _385_ DFF_X1 ; + - _386_ DFF_X1 ; + - _387_ DFF_X1 ; + - _388_ DFF_X1 ; + - _389_ DFF_X1 ; + - _390_ DFF_X1 ; + - _391_ DFF_X1 ; + - _392_ DFF_X1 ; + - _393_ DFF_X1 ; + - _394_ DFF_X1 ; + - _395_ DFF_X1 ; + - _396_ DFF_X1 ; + - _397_ DFF_X1 ; + - _398_ DFF_X1 ; + - _399_ DFF_X1 ; + - _400_ DFF_X1 ; +END COMPONENTS + +PINS 2 ; + - io_1 + NET io_1 ; + - io_2 + NET io_2 ; + - io_3 + NET io_3 ; +END PINS + +NETS 2 ; + - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ; + - io_2 ( MACRO_1 O1 ) ( PIN io_2 ) + USE SIGNAL ; +END NETS + +END DESIGN \ No newline at end of file From 98dc6a6cfb9f57ad48181115ac9be25c4e60ebb2 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Wed, 5 Mar 2025 11:31:35 -0300 Subject: [PATCH 07/34] mpl: adapt orientation improvement to work with regions Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.cpp | 12 +++- src/mpl/src/SimulatedAnnealingCore.h | 1 + src/mpl/src/graphics.cpp | 37 ++++------- src/mpl/src/graphics.h | 6 +- src/mpl/src/hier_rtlmp.cpp | 90 +++----------------------- src/mpl/src/hier_rtlmp.h | 5 +- src/mpl/src/util.h | 26 ++++++-- 7 files changed, 59 insertions(+), 118 deletions(-) diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 22f791b7271..ee895948c59 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -62,8 +62,7 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, unsigned seed, MplObserver* graphics, utl::Logger* logger) - : outline_(outline), - graphics_(graphics) + : outline_(outline), graphics_(graphics) { core_weights_ = weights; @@ -353,6 +352,15 @@ bool SimulatedAnnealingCore::isOutsideTheOutline(const T& macro) const || macro.getPinY() > outline_.getHeight(); } +template +float SimulatedAnnealingCore::computeDistance(const Point& a, + const Point& b) const +{ + const float dx = std::abs(a.first - b.first); + const float dy = std::abs(a.second - b.second); + return std::sqrt(std::pow(dx, 2) + std::pow(dy, 2)); +} + template void SimulatedAnnealingCore::calFencePenalty() { diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 430217c5152..6d7018a6c10 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -138,6 +138,7 @@ class SimulatedAnnealingCore const T& io, float net_weight); bool isOutsideTheOutline(const T& macro) const; + float computeDistance(const Point& a, const Point& b) const; void calGuidancePenalty(); void calFencePenalty(); diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp index d6c482ad87d..1bf4e91906e 100644 --- a/src/mpl/src/graphics.cpp +++ b/src/mpl/src/graphics.cpp @@ -584,7 +584,7 @@ void Graphics::drawBundledNets(gui::Painter& painter, const T& target = macros[bundled_net.terminals.second]; if (target.isClusterOfUnconstrainedIOPins()) { - drawDistToIoConstraintBoundary(painter, source, target); + drawDistToClosestAvailableRegion(painter, source, target); continue; } @@ -602,38 +602,25 @@ void Graphics::drawBundledNets(gui::Painter& painter, } template -void Graphics::drawDistToIoConstraintBoundary(gui::Painter& painter, - const T& macro, - const T& io) +void Graphics::drawDistToClosestAvailableRegion(gui::Painter& painter, + const T& macro, + const T& io) { if (isOutsideTheOutline(macro)) { return; } - const float x1 = macro.getPinX(); - const float y1 = macro.getPinY(); - - odb::Point from(block_->micronsToDbu(x1), block_->micronsToDbu(y1)); + odb::Point from(block_->micronsToDbu(macro.getPinX()), + block_->micronsToDbu(macro.getPinY())); from.addX(outline_.xMin()); from.addY(outline_.yMin()); - odb::Point to; - float dist_to_closest_available_region = std::numeric_limits::max(); - for (const odb::Rect& dbu_region : available_regions_for_pins_) { - const Rect micron_region(block_->dbuToMicrons(dbu_region.xMin()), - block_->dbuToMicrons(dbu_region.yMin()), - block_->dbuToMicrons(dbu_region.xMax()), - block_->dbuToMicrons(dbu_region.yMax())); - - const float dist_to_available_region = computeDistance( - /* from */ {x1, y1}, - /* to */ {micron_region.getX(), micron_region.getY()}); - if (dist_to_available_region < dist_to_closest_available_region) { - dist_to_closest_available_region = dist_to_available_region; - to = {block_->micronsToDbu(micron_region.getX()), - block_->micronsToDbu(micron_region.getY())}; - } - } + // Differently from what happens inside the SA core - where all + // computations are made using the origin of the current outline as + // reference - here we search for the center of the closest region + // using the die area origin as reference. I.e., we offset the macro + // location instead of offsetting the regions as we do inside SA. + odb::Point to = findCenterOfClosestRegion(from, available_regions_for_pins_); painter.drawLine(from, to); painter.drawString( diff --git a/src/mpl/src/graphics.h b/src/mpl/src/graphics.h index 1c0300163fd..43ae6090cdb 100644 --- a/src/mpl/src/graphics.h +++ b/src/mpl/src/graphics.h @@ -111,9 +111,9 @@ class Graphics : public gui::Renderer, public MplObserver template void drawBundledNets(gui::Painter& painter, const std::vector& macros); template - void drawDistToIoConstraintBoundary(gui::Painter& painter, - const T& macro, - const T& io); + void drawDistToClosestAvailableRegion(gui::Painter& painter, + const T& macro, + const T& io); template bool isOutsideTheOutline(const T& macro) const; void addOutlineOffsetToLine(odb::Point& from, odb::Point& to); diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 07c6acbd701..e4a99ee5df5 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -904,15 +904,16 @@ void HierRTLMP::createPinAccessBlockages() BoundaryToRegionsMap boundary_to_blocked_regions = getBoundaryToBlockedRegionsMap(blocked_regions_for_pins); - std::vector dbu_available_regions + available_regions_for_pins_ = computeAvailableRegions(boundary_to_blocked_regions); if (graphics_) { graphics_->setBlockedRegionsForPins(blocked_regions_for_pins); - graphics_->setAvailableRegionsForPins(dbu_available_regions); + graphics_->setAvailableRegionsForPins(available_regions_for_pins_); } - for (const odb::Rect& dbu_available_region : dbu_available_regions) { + for (const odb::Rect& dbu_available_region : available_regions_for_pins_) { + // Store regions in micron inside the tree to be used inside SA. tree_->available_regions_for_pins.push_back( dbuToMicrons(dbu_available_region)); } @@ -2930,24 +2931,12 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro) odb::Rect region_rect(x, y, x, y); net_box.merge(region_rect); } else { - odb::Point macro_pin_location(macro_pin->getBBox().xCenter(), - macro_pin->getBBox().yCenter()); - Boundary closest_boundary = getClosestBoundary( - macro_pin_location, tree_->unblocked_boundaries); - - // As we classify the blocked/unblocked state of the boundary based on - // the extension of the -exclude constraint, it's possible to have - // all boundaries blocked for IOs even though there are small - // unblocked spaces in those boundaries. For this situation, we just - // skip IOs without constraint regions. - if (closest_boundary == NONE) { - continue; - } - - odb::Point closest_point - = getClosestBoundaryPoint(macro_pin_location, closest_boundary); - odb::Rect closest_point_rect(closest_point, closest_point); - net_box.merge(closest_point_rect); + odb::Point closest_available_region_center + = findCenterOfClosestRegion(macro_pin->getBBox().center(), + available_regions_for_pins_); + odb::Rect center_rect(closest_available_region_center, + closest_available_region_center); + net_box.merge(center_rect); } } @@ -2958,65 +2947,6 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro) return wirelength; } -// Search the given boundaries list for the closest boundary to the point. -Boundary HierRTLMP::getClosestBoundary(const odb::Point& from, - const std::set& boundaries) -{ - Boundary closest_boundary = NONE; - int shortest_distance = std::numeric_limits::max(); - - for (const Boundary boundary : boundaries) { - const int dist_to_boundary = getDistanceToBoundary(from, boundary); - if (dist_to_boundary < shortest_distance) { - shortest_distance = dist_to_boundary; - closest_boundary = boundary; - } - } - - return closest_boundary; -} - -int HierRTLMP::getDistanceToBoundary(const odb::Point& from, - const Boundary boundary) -{ - int distance = 0; - - if (boundary == L) { - distance = from.x() - block_->getDieArea().xMin(); - } else if (boundary == R) { - distance = from.x() - block_->getDieArea().xMax(); - } else if (boundary == B) { - distance = from.y() - block_->getDieArea().yMin(); - } else if (boundary == T) { - distance = from.y() - block_->getDieArea().yMax(); - } - - return std::abs(distance); -} - -odb::Point HierRTLMP::getClosestBoundaryPoint(const odb::Point& from, - const Boundary boundary) -{ - odb::Point closest_boundary_point; - const odb::Rect& die = block_->getDieArea(); - - if (boundary == L) { - closest_boundary_point.setX(die.xMin()); - closest_boundary_point.setY(from.y()); - } else if (boundary == R) { - closest_boundary_point.setX(die.xMax()); - closest_boundary_point.setY(from.y()); - } else if (boundary == B) { - closest_boundary_point.setX(from.x()); - closest_boundary_point.setY(die.yMin()); - } else { // Top - closest_boundary_point.setX(from.x()); - closest_boundary_point.setY(die.yMax()); - } - - return closest_boundary_point; -} - void HierRTLMP::flipRealMacro(odb::dbInst* macro, const bool& is_vertical_flip) { if (is_vertical_flip) { diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index 9e9adfc3d7a..452420b827c 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -245,10 +245,6 @@ class HierRTLMP void correctAllMacrosOrientation(); float calculateRealMacroWirelength(odb::dbInst* macro); - Boundary getClosestBoundary(const odb::Point& from, - const std::set& boundaries); - int getDistanceToBoundary(const odb::Point& from, Boundary boundary); - odb::Point getClosestBoundaryPoint(const odb::Point& from, Boundary boundary); void adjustRealMacroOrientation(const bool& is_vertical_flip); void flipRealMacro(odb::dbInst* macro, const bool& is_vertical_flip); @@ -327,6 +323,7 @@ class HierRTLMP std::vector macro_blockages_; std::vector io_blockages_; std::map boundary_to_io_blockage_; // TODO: remove + RegionsList available_regions_for_pins_; // For orientation improvement. // Fast SA hyperparameter float init_prob_ = 0.9; diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index e7a8a581746..7640eb85ded 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -35,9 +35,12 @@ #include +#include "odb/geom.h" + namespace mpl { using Point = std::pair; +using RegionsList = std::vector; struct SACoreWeights { @@ -64,11 +67,26 @@ struct PenaltyData float normalization_factor{0.0f}; }; -inline float computeDistance(const Point& a, const Point& b) +inline int computeDistance(const odb::Point& from, const odb::Point& to) +{ + const int dx = std::abs(from.getX() - to.getX()); + const int dy = std::abs(from.getY() - to.getY()); + return static_cast(std::sqrt(std::pow(dx, 2) + std::pow(dy, 2))); +} + +inline odb::Point findCenterOfClosestRegion(const odb::Point& from, + const RegionsList& regions) { - const float dx = std::abs(a.first - b.first); - const float dy = std::abs(a.second - b.second); - return std::sqrt(std::pow(dx, 2) + std::pow(dy, 2)); + odb::Point to; + int dist_to_closest_region = std::numeric_limits::max(); + for (const odb::Rect& region : regions) { + const int dist_to_region = computeDistance(from, region.center()); + if (dist_to_region < dist_to_closest_region) { + dist_to_closest_region = dist_to_region; + to = region.center(); + } + } + return to; } } // namespace mpl \ No newline at end of file From 3ba36bb301d3b2daa2d4f7be8f8da8b28f2b1d44 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Wed, 5 Mar 2025 11:34:39 -0300 Subject: [PATCH 08/34] mpl: remove odd comment Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 6d7018a6c10..18bb3cf4943 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -164,11 +164,8 @@ class SimulatedAnnealingCore void report(const PenaltyData& penalty) const; Rect outline_; - - // The max cost for distance to boundary wirelength computation - // when one of the SoftMacros is a cluster of unplaced IO pins. - float die_hpwl_; std::vector available_regions_for_pins_; + float die_hpwl_; // Number of macros that will actually be part of the sequence pair int macros_to_place_ = 0; From db20afb9825606c1c53e37fd9357b45cfe67d8f3 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Wed, 5 Mar 2025 11:40:27 -0300 Subject: [PATCH 09/34] mpl: remove comment Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index e4a99ee5df5..ae6d61c0bae 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -1085,7 +1085,6 @@ void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, io_blockages_.push_back(blockage); } -// Isso aqui é melhor ser uma API do Cluster pq vai ser util no SA Boundary HierRTLMP::getRegionBoundary(const odb::Rect& constraint_region) { const odb::Rect& die = block_->getDieArea(); From 0ec8347ebf568223f323530d37f6be2e42fb8f16 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Wed, 5 Mar 2025 12:17:31 -0300 Subject: [PATCH 10/34] mpl: adapt pusher to new io blockages based on regions and update test to correct overlap computation Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 39 ++++++++++++------------------ src/mpl/src/hier_rtlmp.h | 13 +++++----- src/mpl/src/util.h | 6 ++--- src/mpl/test/io_constraints3.defok | 2 +- 4 files changed, 26 insertions(+), 34 deletions(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index ae6d61c0bae..8922dc06e97 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -255,7 +255,7 @@ void HierRTLMP::run() graphics_->drawResult(); } - Pusher pusher(logger_, tree_->root.get(), block_, boundary_to_io_blockage_); + Pusher pusher(logger_, tree_->root.get(), block_, io_blockages_); pusher.pushMacrosToCoreBoundaries(); updateMacrosOnDb(); @@ -3214,22 +3214,20 @@ void HierRTLMP::printPlacementResult(Cluster* parent, Pusher::Pusher(utl::Logger* logger, Cluster* root, odb::dbBlock* block, - const std::map& boundary_to_io_blockage) + const std::vector& io_blockages) : logger_(logger), root_(root), block_(block) { core_ = block_->getCoreArea(); - setIOBlockages(boundary_to_io_blockage); + setIOBlockages(io_blockages); } -void Pusher::setIOBlockages( - const std::map& boundary_to_io_blockage) +void Pusher::setIOBlockages(const std::vector& io_blockages) { - for (const auto& [boundary, box] : boundary_to_io_blockage) { - boundary_to_io_blockage_[boundary] - = odb::Rect(block_->micronsToDbu(box.getX()), - block_->micronsToDbu(box.getY()), - block_->micronsToDbu(box.getX() + box.getWidth()), - block_->micronsToDbu(box.getY() + box.getHeight())); + for (const Rect& blockage : io_blockages) { + io_blockages_.push_back(odb::Rect(block_->micronsToDbu(blockage.xMin()), + block_->micronsToDbu(blockage.yMin()), + block_->micronsToDbu(blockage.xMax()), + block_->micronsToDbu(blockage.yMax()))); } } @@ -3403,7 +3401,7 @@ void Pusher::pushMacroClusterToCoreBoundaries( // Check based on the shape of the macro cluster to avoid iterating each // of its HardMacros. if (overlapsWithHardMacro(cluster_box, hard_macros) - || overlapsWithIOBlockage(cluster_box, boundary)) { + || overlapsWithIOBlockage(cluster_box)) { debugPrint(logger_, MPL, "boundary_push", @@ -3501,19 +3499,12 @@ bool Pusher::overlapsWithHardMacro( return false; } -bool Pusher::overlapsWithIOBlockage(const odb::Rect& cluster_box, - const Boundary boundary) +bool Pusher::overlapsWithIOBlockage(const odb::Rect& cluster_box) { - if (boundary_to_io_blockage_.find(boundary) - == boundary_to_io_blockage_.end()) { - return false; - } - - const odb::Rect box = boundary_to_io_blockage_.at(boundary); - - if (cluster_box.xMin() < box.xMax() && cluster_box.yMin() < box.yMax() - && cluster_box.xMax() > box.xMin() && cluster_box.yMax() > box.yMin()) { - return true; + for (const odb::Rect& io_blockage : io_blockages_) { + if (cluster_box.overlaps(io_blockage)) { + return true; + } } return false; diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index 452420b827c..d85e6732c9e 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -322,8 +322,9 @@ class HierRTLMP std::vector placement_blockages_; std::vector macro_blockages_; std::vector io_blockages_; - std::map boundary_to_io_blockage_; // TODO: remove - RegionsList available_regions_for_pins_; // For orientation improvement. + + // For orientation improvement. + std::vector available_regions_for_pins_; // Fast SA hyperparameter float init_prob_ = 0.9; @@ -357,12 +358,12 @@ class Pusher Pusher(utl::Logger* logger, Cluster* root, odb::dbBlock* block, - const std::map& boundary_to_io_blockage); + const std::vector& io_blockages); void pushMacrosToCoreBoundaries(); private: - void setIOBlockages(const std::map& boundary_to_io_blockage); + void setIOBlockages(const std::vector& io_blockages); bool designHasSingleCentralizedMacroArray(); void pushMacroClusterToCoreBoundaries( Cluster* macro_cluster, @@ -377,7 +378,7 @@ class Pusher bool overlapsWithHardMacro( const odb::Rect& cluster_box, const std::vector& cluster_hard_macros); - bool overlapsWithIOBlockage(const odb::Rect& cluster_box, Boundary boundary); + bool overlapsWithIOBlockage(const odb::Rect& cluster_box); utl::Logger* logger_; @@ -385,7 +386,7 @@ class Pusher odb::dbBlock* block_; odb::Rect core_; - std::map boundary_to_io_blockage_; // TODO: remove + std::vector io_blockages_; std::vector hard_macros_; }; diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index 7640eb85ded..da912b0580b 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -40,7 +40,6 @@ namespace mpl { using Point = std::pair; -using RegionsList = std::vector; struct SACoreWeights { @@ -74,8 +73,9 @@ inline int computeDistance(const odb::Point& from, const odb::Point& to) return static_cast(std::sqrt(std::pow(dx, 2) + std::pow(dy, 2))); } -inline odb::Point findCenterOfClosestRegion(const odb::Point& from, - const RegionsList& regions) +inline odb::Point findCenterOfClosestRegion( + const odb::Point& from, + const std::vector& regions) { odb::Point to; int dist_to_closest_region = std::numeric_limits::max(); diff --git a/src/mpl/test/io_constraints3.defok b/src/mpl/test/io_constraints3.defok index aeac6e85033..8f39bab6c64 100644 --- a/src/mpl/test/io_constraints3.defok +++ b/src/mpl/test/io_constraints3.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 41330 ) FS ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 90900 24810 ) FS ; - _001_ DFF_X1 + PLACED ( 38218 123234 ) N ; - _002_ DFF_X1 + PLACED ( 38218 123234 ) N ; - _003_ DFF_X1 + PLACED ( 38218 123234 ) N ; From 3a90f134d7082d3355eed54a3c11ca55060e9bbd Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Wed, 5 Mar 2025 14:17:57 -0300 Subject: [PATCH 11/34] mpl: adjust regression tests' results to orientation improve bug fix from master Signed-off-by: Arthur Koucher --- src/mpl/test/io_constraints4.defok | 2 +- src/mpl/test/io_constraints5.defok | 2 +- src/mpl/test/io_constraints6.defok | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mpl/test/io_constraints4.defok b/src/mpl/test/io_constraints4.defok index d4d22e5510b..b49e8312d10 100644 --- a/src/mpl/test/io_constraints4.defok +++ b/src/mpl/test/io_constraints4.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8290 ) S ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8290 ) FS ; - _001_ DFF_X1 + PLACED ( 38680 123234 ) N ; - _002_ DFF_X1 + PLACED ( 38680 123234 ) N ; - _003_ DFF_X1 + PLACED ( 38680 123234 ) N ; diff --git a/src/mpl/test/io_constraints5.defok b/src/mpl/test/io_constraints5.defok index 0cc9325891e..6eaf1c8411a 100644 --- a/src/mpl/test/io_constraints5.defok +++ b/src/mpl/test/io_constraints5.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8290 ) S ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8290 ) FS ; - _001_ DFF_X1 + PLACED ( 254680 123234 ) N ; - _002_ DFF_X1 + PLACED ( 254680 123234 ) N ; - _003_ DFF_X1 + PLACED ( 254680 123234 ) N ; diff --git a/src/mpl/test/io_constraints6.defok b/src/mpl/test/io_constraints6.defok index 8bd1649b1e2..6ae081c0d80 100644 --- a/src/mpl/test/io_constraints6.defok +++ b/src/mpl/test/io_constraints6.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8290 ) S ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8290 ) FS ; - _001_ DFF_X1 + PLACED ( 38680 123234 ) N ; - _002_ DFF_X1 + PLACED ( 38680 123234 ) N ; - _003_ DFF_X1 + PLACED ( 38680 123234 ) N ; From 7ee63d0563083c970c83e5c06004b7f7fec7a9d1 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Thu, 6 Mar 2025 11:45:37 -0300 Subject: [PATCH 12/34] mpl: 1. Simplify creation of clusters of unplaced IOs 2. [Fix] Set root as parent clusters of unplaced IOs 3. Some comment and critical message improvements Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.cpp | 4 +- src/mpl/src/clusterEngine.cpp | 64 +++++++++++--------------- src/mpl/src/clusterEngine.h | 10 ++-- src/mpl/src/hier_rtlmp.cpp | 13 +++++- src/mpl/src/hier_rtlmp.h | 3 +- 5 files changed, 50 insertions(+), 44 deletions(-) diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index ee895948c59..6115f29c870 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -327,7 +327,9 @@ void SimulatedAnnealingCore::addClosestAvailableRegionDistToWL( if (available_regions_for_pins_.empty()) { logger_->critical( - utl::MPL, 47, "The unconstrained pins have no available region!"); + utl::MPL, + 47, + "There's no available region for the unconstrained pins!"); } float dist_to_closest_available_region = std::numeric_limits::max(); diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 9b1d94d0ae9..afea5b17af3 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -393,60 +393,52 @@ void ClusteringEngine::createIOClusters() tree_->has_io_clusters = false; } - bool design_has_only_unconstrained_ios = true; - std::vector cluster_and_region_list; - for (odb::dbBTerm* bterm : block_->getBTerms()) { - auto bterm_constraint = bterm->getConstraintRegion(); - if (bterm_constraint) { - design_has_only_unconstrained_ios = false; - createClusterOfUnplacedIOs( - cluster_and_region_list, bterm, bterm_constraint.value()); + Cluster* same_constraint_cluster = findIOClusterWithSameConstraint(bterm); + if (same_constraint_cluster) { + tree_->maps.bterm_to_cluster_id[bterm] = same_constraint_cluster->getId(); } else { - createClusterOfUnplacedIOs( - cluster_and_region_list, bterm, block_->getDieArea()); + createClusterOfUnplacedIOs(bterm); } } - - if (design_has_only_unconstrained_ios) { - tree_->has_only_unconstrained_ios = true; - } } -// Isso pode ter um nome melhor -void ClusteringEngine::createClusterOfUnplacedIOs( - std::vector& cluster_and_region_list, - odb::dbBTerm* bterm, - const odb::Rect& bterm_constraint) +Cluster* ClusteringEngine::findIOClusterWithSameConstraint(odb::dbBTerm* bterm) { - bool found_cluster_with_same_constraint = false; - for (const auto& [cluster, cluster_constraint] : cluster_and_region_list) { - if (bterm_constraint == cluster_constraint) { - tree_->maps.bterm_to_cluster_id[bterm] = cluster->getId(); - found_cluster_with_same_constraint = true; - break; + for (const auto& [cluster, cluster_constraint] : + io_cluster_and_region_list_) { + if (bterm->getConstraintRegion() == cluster_constraint) { + return cluster; } } - if (found_cluster_with_same_constraint) { - return; - } + return nullptr; +} +void ClusteringEngine::createClusterOfUnplacedIOs(odb::dbBTerm* bterm) +{ auto cluster = std::make_unique(id_, "", logger_); - if (bterm_constraint == block_->getDieArea()) { + cluster->setParent(tree_->root.get()); + + odb::Rect constraint_shape; + const std::optional& bterm_constraint + = bterm->getConstraintRegion(); + if (bterm_constraint) { + constraint_shape = *bterm_constraint; + cluster->setName("ios_" + std::to_string(id_)); + } else { + constraint_shape = block_->getDieArea(); cluster->setName("unconstrained_ios"); cluster->setAsClusterOfUnconstrainedIOPins(); - } else { - cluster->setName("ios_" + std::to_string(id_)); } cluster->setAsClusterOfUnplacedIOPins( - {block_->dbuToMicrons(bterm_constraint.xMin()), - block_->dbuToMicrons(bterm_constraint.yMin())}, - block_->dbuToMicrons(bterm_constraint.dx()), - block_->dbuToMicrons(bterm_constraint.dy())); + {block_->dbuToMicrons(constraint_shape.xMin()), + block_->dbuToMicrons(constraint_shape.yMin())}, + block_->dbuToMicrons(constraint_shape.dx()), + block_->dbuToMicrons(constraint_shape.dy())); - cluster_and_region_list.push_back({cluster.get(), bterm_constraint}); + io_cluster_and_region_list_.push_back({cluster.get(), constraint_shape}); tree_->maps.bterm_to_cluster_id[bterm] = id_; tree_->maps.id_to_cluster[id_++] = cluster.get(); diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 65e80723595..93eb191f28c 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -130,7 +130,6 @@ struct PhysicalHierarchy Rect floorplan_shape; bool has_io_clusters{true}; - bool has_only_unconstrained_ios{false}; bool has_only_macros{false}; bool has_std_cells{true}; bool has_unfixed_macros{true}; @@ -201,10 +200,8 @@ class ClusteringEngine void createRoot(); void setBaseThresholds(); void createIOClusters(); - void createClusterOfUnplacedIOs( - std::vector& cluster_and_region_list, - odb::dbBTerm* bterm, - const odb::Rect& bterm_constraint); + Cluster* findIOClusterWithSameConstraint(odb::dbBTerm* bterm); + void createClusterOfUnplacedIOs(odb::dbBTerm* bterm); void createIOPadClusters(); void createIOPadCluster(odb::dbInst* pad, odb::dbBTerm* bterm); void mapIOPinsAndPads(); @@ -291,6 +288,9 @@ class ClusteringEngine Metrics* design_metrics_{nullptr}; PhysicalHierarchy* tree_{nullptr}; + // Only for clusters of unplaced IOs. + std::vector io_cluster_and_region_list_; + int level_{0}; // Current level int id_{0}; // Current "highest" id diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 8922dc06e97..f219247c476 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -890,7 +890,7 @@ void HierRTLMP::createPinAccessBlockages() return; } - if (tree_->has_only_unconstrained_ios) { + if (treeHasOnlyUnconstrainedIOs()) { const std::vector& blocked_regions_for_pins = block_->getBlockedRegionsForPins(); @@ -924,6 +924,17 @@ void HierRTLMP::createPinAccessBlockages() } } +bool HierRTLMP::treeHasOnlyUnconstrainedIOs() +{ + std::vector io_clusters = getClustersOfUnplacedIOPins(); + for (Cluster* io_cluster : io_clusters) { + if (!io_cluster->isClusterOfUnconstrainedIOPins()) { + return false; + } + } + return true; +} + void HierRTLMP::createBlockagesForAvailableRegions() { float io_span = 0.0f; diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index d85e6732c9e..86995baf6c1 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -179,6 +179,7 @@ class HierRTLMP void calculateMacroTilings(Cluster* cluster); void setTightPackingTilings(Cluster* macro_array); void createPinAccessBlockages(); + bool treeHasOnlyUnconstrainedIOs(); std::vector getClustersOfUnplacedIOPins(); void createPinAccessBlockage(const Rect& micron_region, const float depth); float computePinAccessBaseDepth(const float io_span); @@ -323,7 +324,7 @@ class HierRTLMP std::vector macro_blockages_; std::vector io_blockages_; - // For orientation improvement. + // Cache needed for orientation improvement. std::vector available_regions_for_pins_; // Fast SA hyperparameter From 701ca9e1398c76f2265171bff0680161767e6fb3 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Thu, 6 Mar 2025 15:01:39 -0300 Subject: [PATCH 13/34] mpl: 1. Remove unused argument 2. Improve comments 3. Adpt function name 4. TO DOs clean up Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.cpp | 3 +-- src/mpl/src/SimulatedAnnealingCore.h | 1 - src/mpl/src/clusterEngine.h | 1 - src/mpl/src/graphics.cpp | 4 ++-- src/mpl/src/graphics.h | 2 +- src/mpl/src/hier_rtlmp.cpp | 7 ++++--- 6 files changed, 8 insertions(+), 10 deletions(-) diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 6115f29c870..467bfce83e1 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -291,7 +291,7 @@ void SimulatedAnnealingCore::calWirelength() T& target = macros_[net.terminals.second]; if (target.isClusterOfUnconstrainedIOPins()) { - addClosestAvailableRegionDistToWL(source, target, net.weight); + addClosestAvailableRegionDistToWL(source, net.weight); continue; } @@ -317,7 +317,6 @@ void SimulatedAnnealingCore::calWirelength() template void SimulatedAnnealingCore::addClosestAvailableRegionDistToWL( const T& macro, - const T& io, const float net_weight) { if (isOutsideTheOutline(macro)) { diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 18bb3cf4943..a25bd47d88d 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -135,7 +135,6 @@ class SimulatedAnnealingCore void calOutlinePenalty(); void calWirelength(); void addClosestAvailableRegionDistToWL(const T& macro, - const T& io, float net_weight); bool isOutsideTheOutline(const T& macro) const; float computeDistance(const Point& a, const Point& b) const; diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 93eb191f28c..53d781a756d 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -114,7 +114,6 @@ struct PhysicalHierarchy PhysicalHierarchyMaps maps; std::vector available_regions_for_pins; - std::set unblocked_boundaries; // TODO: remove float halo_width{0.0f}; float halo_height{0.0f}; diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp index 1bf4e91906e..55bee99f889 100644 --- a/src/mpl/src/graphics.cpp +++ b/src/mpl/src/graphics.cpp @@ -519,7 +519,7 @@ void Graphics::drawObjects(gui::Painter& painter) } } - drawBlockedBoundariesIndication(painter); + drawBlockedRegionsIndication(painter); painter.setBrush(gui::Painter::transparent); if (only_final_result_) { @@ -565,7 +565,7 @@ void Graphics::drawGuides(gui::Painter& painter) } } -void Graphics::drawBlockedBoundariesIndication(gui::Painter& painter) +void Graphics::drawBlockedRegionsIndication(gui::Painter& painter) { painter.setPen(gui::Painter::red, true); painter.setBrush(gui::Painter::transparent); diff --git a/src/mpl/src/graphics.h b/src/mpl/src/graphics.h index 43ae6090cdb..bd748e0c564 100644 --- a/src/mpl/src/graphics.h +++ b/src/mpl/src/graphics.h @@ -101,7 +101,7 @@ class Graphics : public gui::Renderer, public MplObserver void setXMarksSize(); void resetPenalties(); void drawCluster(Cluster* cluster, gui::Painter& painter); - void drawBlockedBoundariesIndication(gui::Painter& painter); + void drawBlockedRegionsIndication(gui::Painter& painter); void drawAllBlockages(gui::Painter& painter); void drawOffsetRect(const Rect& rect, const std::string& center_text, diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index f219247c476..d8fb1033ce4 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -896,9 +896,10 @@ void HierRTLMP::createPinAccessBlockages() if (blocked_regions_for_pins.empty()) { // If there are no constraints at all, we give freedom to SA so it - // doesn't have to deal with pin access blockages in all boundaries. - // This will help SA not relying on extreme utilizations to - // converge for designs such as sky130hd/uW. + // doesn't have to deal with pin access blockages across the entire + // extension of all edges of the die area. This should help SA not + // relying on extreme utilizations to converge for designs such as + // sky130hd/uW. return; } From f734be799f62cb9247fc55a163d0ac0bb7e22ae3 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Thu, 6 Mar 2025 17:55:58 -0300 Subject: [PATCH 14/34] mpl: 1. Cache actual offset die area instead of just the half perimeter and use the cached die to compute the max dist for max cost. 2. Some renaming. Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.cpp | 15 +++++++++++++-- src/mpl/src/SimulatedAnnealingCore.h | 4 +++- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 467bfce83e1..e80a2906fcc 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -84,10 +84,18 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, logger_ = logger; macros_ = macros; - die_hpwl_ = tree->die_area.getPerimeter() / 2; + setDieArea(tree->die_area); setAvailableRegionForPins(tree->available_regions_for_pins); } +template +void SimulatedAnnealingCore::setDieArea(const Rect& die_area) +{ + die_area_ = die_area; + die_area_.moveHor(-outline_.xMin()); + die_area_.moveVer(-outline_.yMin()); +} + template void SimulatedAnnealingCore::setAvailableRegionForPins( const std::vector& regions) @@ -319,8 +327,11 @@ void SimulatedAnnealingCore::addClosestAvailableRegionDistToWL( const T& macro, const float net_weight) { + // To generate maximum cost. + const float max_dist = die_area_.getPerimeter() / 2; + if (isOutsideTheOutline(macro)) { - wirelength_ += net_weight * die_hpwl_; + wirelength_ += net_weight * max_dist; return; } diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index a25bd47d88d..ff683c44fea 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -127,6 +127,7 @@ class SimulatedAnnealingCore void setAvailableRegionForPins(const std::vector& regions); void initSequencePair(); + void setDieArea(const Rect& die_area); void updateBestValidResult(); void useBestValidResult(); @@ -163,8 +164,9 @@ class SimulatedAnnealingCore void report(const PenaltyData& penalty) const; Rect outline_; + Rect die_area_; // Offset to the current outline. + std::vector available_regions_for_pins_; - float die_hpwl_; // Number of macros that will actually be part of the sequence pair int macros_to_place_ = 0; From 9d95cd3ecb97001f7c6adbe946e75f4df0a86e68 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 7 Mar 2025 11:48:56 -0300 Subject: [PATCH 15/34] mpl: clang-tidy and format Signed-off-by: Arthur Koucher --- src/mpl/src/SimulatedAnnealingCore.h | 3 +-- src/mpl/src/clusterEngine.cpp | 5 ++--- src/mpl/src/clusterEngine.h | 3 +-- src/mpl/src/hier_rtlmp.cpp | 9 +++++---- src/mpl/src/hier_rtlmp.h | 4 ++-- 5 files changed, 11 insertions(+), 13 deletions(-) diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index ff683c44fea..2e90408f329 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -135,8 +135,7 @@ class SimulatedAnnealingCore virtual void calPenalty() = 0; void calOutlinePenalty(); void calWirelength(); - void addClosestAvailableRegionDistToWL(const T& macro, - float net_weight); + void addClosestAvailableRegionDistToWL(const T& macro, float net_weight); bool isOutsideTheOutline(const T& macro) const; float computeDistance(const Point& a, const Point& b) const; void calGuidancePenalty(); diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index afea5b17af3..0d2d08a432f 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -405,8 +405,7 @@ void ClusteringEngine::createIOClusters() Cluster* ClusteringEngine::findIOClusterWithSameConstraint(odb::dbBTerm* bterm) { - for (const auto& [cluster, cluster_constraint] : - io_cluster_and_region_list_) { + for (const auto& [cluster, cluster_constraint] : unplaced_ios_to_region_) { if (bterm->getConstraintRegion() == cluster_constraint) { return cluster; } @@ -438,7 +437,7 @@ void ClusteringEngine::createClusterOfUnplacedIOs(odb::dbBTerm* bterm) block_->dbuToMicrons(constraint_shape.dx()), block_->dbuToMicrons(constraint_shape.dy())); - io_cluster_and_region_list_.push_back({cluster.get(), constraint_shape}); + unplaced_ios_to_region_[cluster.get()] = constraint_shape; tree_->maps.bterm_to_cluster_id[bterm] = id_; tree_->maps.id_to_cluster[id_++] = cluster.get(); diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 53d781a756d..7ad72d7694f 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -185,7 +185,6 @@ class ClusteringEngine private: using UniqueClusterQueue = std::queue>; - using IOClusterAndRegion = std::pair; void init(); Metrics* computeModuleMetrics(odb::dbModule* module); @@ -288,7 +287,7 @@ class ClusteringEngine PhysicalHierarchy* tree_{nullptr}; // Only for clusters of unplaced IOs. - std::vector io_cluster_and_region_list_; + std::map unplaced_ios_to_region_; int level_{0}; // Current level int id_{0}; // Current "highest" id diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index d8fb1033ce4..8f9d99abbb5 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -3236,10 +3236,11 @@ Pusher::Pusher(utl::Logger* logger, void Pusher::setIOBlockages(const std::vector& io_blockages) { for (const Rect& blockage : io_blockages) { - io_blockages_.push_back(odb::Rect(block_->micronsToDbu(blockage.xMin()), - block_->micronsToDbu(blockage.yMin()), - block_->micronsToDbu(blockage.xMax()), - block_->micronsToDbu(blockage.yMax()))); + io_blockages_.emplace_back( + odb::Rect(block_->micronsToDbu(blockage.xMin()), + block_->micronsToDbu(blockage.yMin()), + block_->micronsToDbu(blockage.xMax()), + block_->micronsToDbu(blockage.yMax()))); } } diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index 86995baf6c1..539d4dc356e 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -181,8 +181,8 @@ class HierRTLMP void createPinAccessBlockages(); bool treeHasOnlyUnconstrainedIOs(); std::vector getClustersOfUnplacedIOPins(); - void createPinAccessBlockage(const Rect& micron_region, const float depth); - float computePinAccessBaseDepth(const float io_span); + void createPinAccessBlockage(const Rect& micron_region, float depth); + float computePinAccessBaseDepth(float io_span); BoundaryToRegionsMap getBoundaryToBlockedRegionsMap( const std::vector& blocked_regions_for_pins); std::vector computeAvailableRegions( From 845d02ab3008ee9982707ba46108bb0e2bef35fa Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 7 Mar 2025 12:00:38 -0300 Subject: [PATCH 16/34] mpl: remove unneeded function and alias from util.h Signed-off-by: Arthur Koucher --- src/mpl/src/object.h | 1 + src/mpl/src/util.h | 14 +++----------- 2 files changed, 4 insertions(+), 11 deletions(-) diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index 8c138f9bbf2..2251fc3205a 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -68,6 +68,7 @@ class SoftMacro; class Cluster; using UniqueClusterVector = std::vector>; +using Point = std::pair; // **************************************************************************** // This file includes the basic functions and basic classes for the HierRTLMP diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index da912b0580b..1e7b399d8b1 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -39,8 +39,6 @@ namespace mpl { -using Point = std::pair; - struct SACoreWeights { float area{0.0f}; @@ -66,21 +64,15 @@ struct PenaltyData float normalization_factor{0.0f}; }; -inline int computeDistance(const odb::Point& from, const odb::Point& to) -{ - const int dx = std::abs(from.getX() - to.getX()); - const int dy = std::abs(from.getY() - to.getY()); - return static_cast(std::sqrt(std::pow(dx, 2) + std::pow(dy, 2))); -} - inline odb::Point findCenterOfClosestRegion( const odb::Point& from, const std::vector& regions) { odb::Point to; - int dist_to_closest_region = std::numeric_limits::max(); + double dist_to_closest_region = std::numeric_limits::max(); for (const odb::Rect& region : regions) { - const int dist_to_region = computeDistance(from, region.center()); + const double dist_to_region + = std::sqrt(odb::Point::squaredDistance(from, region.center())); if (dist_to_region < dist_to_closest_region) { dist_to_closest_region = dist_to_region; to = region.center(); From b33f9def3ad8843306f647435de67900574e8007 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 7 Mar 2025 12:05:37 -0300 Subject: [PATCH 17/34] mpl: remove unused APIs to avoid confusion Signed-off-by: Arthur Koucher --- src/mpl/src/object.cpp | 22 +++------------------- src/mpl/src/object.h | 3 --- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp index 449aa3f082e..b1511b07e46 100644 --- a/src/mpl/src/object.cpp +++ b/src/mpl/src/object.cpp @@ -841,16 +841,7 @@ bool HardMacro::operator==(const HardMacro& macro) const } // Cluster support to identify if a fixed terminal correponds -// to a cluster of unplaced IO pins when running HardMacro SA. -bool HardMacro::isClusterOfUnplacedIOPins() const -{ - if (!cluster_) { - return false; - } - - return cluster_->isClusterOfUnplacedIOPins(); -} - +// to the cluster of unconstrained IO pins when running HardMacro SA. bool HardMacro::isClusterOfUnconstrainedIOPins() const { if (!cluster_) { @@ -1343,15 +1334,8 @@ bool SoftMacro::isMixedCluster() const return (cluster_->getClusterType() == MixedCluster); } -bool SoftMacro::isClusterOfUnplacedIOPins() const -{ - if (!cluster_) { - return false; - } - - return cluster_->isClusterOfUnplacedIOPins(); -} - +// Used to identify if a fixed terminal correponds to the cluster of +// unconstrained IO pins when running SoftMacro SA. bool SoftMacro::isClusterOfUnconstrainedIOPins() const { if (!cluster_) { diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index 2251fc3205a..8884c78dbc4 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -360,8 +360,6 @@ class HardMacro bool operator==(const HardMacro& macro) const; void setCluster(Cluster* cluster) { cluster_ = cluster; } - Cluster* getCluster() const { return cluster_; } - bool isClusterOfUnplacedIOPins() const; bool isClusterOfUnconstrainedIOPins() const; // Get Physical Information @@ -536,7 +534,6 @@ class SoftMacro bool isMacroCluster() const; bool isStdCellCluster() const; bool isMixedCluster() const; - bool isClusterOfUnplacedIOPins() const; bool isClusterOfUnconstrainedIOPins() const; void setLocationF(float x, float y); void setShapeF(float width, float height); From dd6f6843c09b642258e9cb8aa15a054a22c13614 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Mon, 28 Apr 2025 11:22:53 -0300 Subject: [PATCH 18/34] mpl: 1) Make fixed terminals points again as the new approach doesn't require that anymore when computing distance to region in WL computation. 2) Format. Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 23 ++++++++--------------- src/mpl/src/util.h | 3 +-- 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index ed5d42e48fb..5b62d134a43 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -2100,20 +2100,14 @@ void HierRTLMP::createFixedTerminal(Cluster* cluster, const Rect& outline, std::vector& macros) { - // A conventional fixed terminal is just a point without - // the cluster data. Point location = cluster->getCenter(); float width = 0.0f; float height = 0.0f; Cluster* terminal_cluster = nullptr; - if (cluster->isClusterOfUnplacedIOPins()) { - // Clusters of unplaced IOs are not treated as conventional - // fixed terminals. As they correspond to regions, we need - // both their actual shape and their cluster data inside SA. - location = {cluster->getX(), cluster->getY()}; - width = cluster->getWidth(); - height = cluster->getHeight(); + if (cluster->isClusterOfUnconstrainedIOPins()) { + // The cluster data is needed so that the annealer + // can identify the cluster of unconstrained IOs. terminal_cluster = cluster; } @@ -3320,14 +3314,13 @@ bool Pusher::overlapsWithIOBlockage(const odb::Rect& cluster_box) for (const odb::Rect& io_blockage : io_blockages_) { if (cluster_box.overlaps(io_blockage)) { debugPrint(logger_, - MPL, - "boundary_push", - 1, - "\tFound overlap with IO blockage {}. Push will be reverted.", - io_blockage); + MPL, + "boundary_push", + 1, + "\tFound overlap with IO blockage {}. Push will be reverted.", + io_blockage); return true; } - } return false; diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index e918901f9d8..8e1ff7438de 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -6,9 +6,8 @@ #include #include -#include "shapes.h" - #include "odb/geom.h" +#include "shapes.h" namespace mpl { From 67d1cf44f7ae10f32d1fa19646921565949e0425 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Mon, 28 Apr 2025 14:57:04 -0300 Subject: [PATCH 19/34] mpl: 1) Remove PPL calls from new tests. 2) Adapt tests to be more concise. Signed-off-by: Arthur Koucher --- src/mpl/test/boundary_push2.defok | 6 +- src/mpl/test/boundary_push3.defok | 4 +- src/mpl/test/io_constraints3.defok | 817 ++++++++++---------- src/mpl/test/io_constraints3.ok | 7 - src/mpl/test/io_constraints3.tcl | 5 +- src/mpl/test/io_constraints4.defok | 817 ++++++++++---------- src/mpl/test/io_constraints4.ok | 9 - src/mpl/test/io_constraints4.tcl | 7 +- src/mpl/test/io_constraints5.defok | 817 ++++++++++---------- src/mpl/test/io_constraints5.ok | 9 - src/mpl/test/io_constraints5.tcl | 3 - src/mpl/test/io_constraints6.defok | 821 ++++++++++----------- src/mpl/test/io_constraints6.ok | 11 +- src/mpl/test/io_constraints6.tcl | 6 +- src/mpl/test/io_constraints7.defok | 821 ++++++++++----------- src/mpl/test/io_constraints7.ok | 13 +- src/mpl/test/io_constraints7.tcl | 15 +- src/mpl/test/testcases/io_constraints6.def | 7 +- 18 files changed, 2037 insertions(+), 2158 deletions(-) diff --git a/src/mpl/test/boundary_push2.defok b/src/mpl/test/boundary_push2.defok index 1ebf92c2099..4974b643a37 100644 --- a/src/mpl/test/boundary_push2.defok +++ b/src/mpl/test/boundary_push2.defok @@ -183,9 +183,9 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 54 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 600 20770 ) S ; - - MACRO_2 HM_100x100_1x1 + FIXED ( 239440 221810 ) FS ; - - MACRO_3 HM_100x100_1x1 + FIXED ( 600 221810 ) FS ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 600 221810 ) S ; + - MACRO_2 HM_100x100_1x1 + FIXED ( 600 20770 ) FS ; + - MACRO_3 HM_100x100_1x1 + FIXED ( 239440 221810 ) FS ; - MACRO_4 HM_100x100_1x1 + FIXED ( 239440 20770 ) FS ; - _001_ DFF_X1 + PLACED ( 15591 18600 ) N ; - _002_ DFF_X1 + PLACED ( 15591 18600 ) N ; diff --git a/src/mpl/test/boundary_push3.defok b/src/mpl/test/boundary_push3.defok index b8b404ab058..1b279a1ab94 100644 --- a/src/mpl/test/boundary_push3.defok +++ b/src/mpl/test/boundary_push3.defok @@ -183,9 +183,9 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 54 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 19420 610 ) S ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 220620 610 ) S ; - MACRO_2 HM_100x100_1x1 + FIXED ( 19420 241970 ) FS ; - - MACRO_3 HM_100x100_1x1 + FIXED ( 220620 610 ) FS ; + - MACRO_3 HM_100x100_1x1 + FIXED ( 19420 610 ) FS ; - MACRO_4 HM_100x100_1x1 + FIXED ( 220620 241970 ) FS ; - _001_ DFF_X1 + PLACED ( 15590 18601 ) N ; - _002_ DFF_X1 + PLACED ( 15590 18601 ) N ; diff --git a/src/mpl/test/io_constraints3.defok b/src/mpl/test/io_constraints3.defok index 8f39bab6c64..49acd7a712a 100644 --- a/src/mpl/test/io_constraints3.defok +++ b/src/mpl/test/io_constraints3.defok @@ -114,421 +114,412 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 90900 24810 ) FS ; - - _001_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _002_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _003_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _004_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _005_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _006_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _007_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _008_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _009_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _010_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _011_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _012_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _013_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _014_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _015_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _016_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _017_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _018_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _019_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _020_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _021_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _022_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _023_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _024_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _025_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _026_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _027_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _028_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _029_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _030_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _031_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _032_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _033_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _034_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _035_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _036_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _037_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _038_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _039_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _040_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _041_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _042_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _043_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _044_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _045_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _046_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _047_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _048_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _049_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _050_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _051_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _052_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _053_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _054_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _055_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _056_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _057_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _058_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _059_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _060_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _061_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _062_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _063_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _064_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _065_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _066_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _067_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _068_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _069_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _070_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _071_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _072_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _073_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _074_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _075_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _076_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _077_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _078_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _079_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _080_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _081_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _082_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _083_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _084_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _085_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _086_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _087_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _088_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _089_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _090_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _091_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _092_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _093_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _094_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _095_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _096_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _097_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _098_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _099_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _100_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _101_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _102_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _103_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _104_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _105_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _106_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _107_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _108_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _109_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _110_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _111_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _112_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _113_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _114_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _115_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _116_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _117_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _118_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _119_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _120_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _121_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _122_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _123_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _124_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _125_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _126_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _127_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _128_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _129_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _130_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _131_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _132_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _133_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _134_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _135_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _136_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _137_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _138_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _139_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _140_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _141_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _142_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _143_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _144_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _145_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _146_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _147_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _148_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _149_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _150_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _151_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _152_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _153_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _154_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _155_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _156_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _157_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _158_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _159_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _160_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _161_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _162_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _163_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _164_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _165_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _166_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _167_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _168_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _169_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _170_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _171_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _172_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _173_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _174_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _175_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _176_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _177_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _178_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _179_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _180_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _181_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _182_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _183_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _184_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _185_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _186_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _187_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _188_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _189_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _190_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _191_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _192_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _193_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _194_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _195_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _196_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _197_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _198_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _199_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _200_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _201_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _202_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _203_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _204_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _205_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _206_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _207_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _208_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _209_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _210_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _211_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _212_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _213_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _214_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _215_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _216_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _217_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _218_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _219_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _220_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _221_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _222_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _223_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _224_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _225_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _226_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _227_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _228_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _229_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _230_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _231_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _232_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _233_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _234_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _235_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _236_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _237_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _238_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _239_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _240_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _241_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _242_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _243_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _244_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _245_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _246_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _247_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _248_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _249_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _250_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _251_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _252_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _253_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _254_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _255_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _256_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _257_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _258_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _259_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _260_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _261_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _262_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _263_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _264_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _265_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _266_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _267_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _268_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _269_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _270_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _271_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _272_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _273_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _274_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _275_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _276_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _277_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _278_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _279_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _280_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _281_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _282_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _283_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _284_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _285_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _286_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _287_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _288_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _289_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _290_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _291_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _292_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _293_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _294_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _295_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _296_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _297_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _298_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _299_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _300_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _301_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _302_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _303_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _304_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _305_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _306_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _307_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _308_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _309_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _310_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _311_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _312_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _313_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _314_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _315_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _316_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _317_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _318_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _319_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _320_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _321_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _322_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _323_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _324_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _325_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _326_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _327_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _328_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _329_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _330_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _331_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _332_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _333_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _334_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _335_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _336_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _337_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _338_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _339_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _340_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _341_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _342_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _343_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _344_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _345_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _346_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _347_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _348_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _349_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _350_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _351_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _352_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _353_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _354_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _355_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _356_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _357_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _358_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _359_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _360_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _361_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _362_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _363_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _364_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _365_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _366_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _367_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _368_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _369_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _370_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _371_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _372_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _373_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _374_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _375_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _376_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _377_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _378_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _379_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _380_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _381_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _382_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _383_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _384_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _385_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _386_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _387_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _388_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _389_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _390_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _391_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _392_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _393_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _394_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _395_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _396_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _397_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _398_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _399_ DFF_X1 + PLACED ( 38218 123234 ) N ; - - _400_ DFF_X1 + PLACED ( 38218 123234 ) N ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 41330 ) FS ; + - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _004_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _005_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _006_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _007_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _008_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _009_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _010_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _011_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _012_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _013_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _014_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _015_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _016_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _017_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _018_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _019_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _020_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _021_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _022_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _023_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _024_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _025_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _026_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _027_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _028_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _029_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _030_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _031_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _032_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _033_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _034_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _035_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _036_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _037_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _038_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _039_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _040_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _041_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _042_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _043_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _044_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _045_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _046_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _047_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _048_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _049_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _050_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _051_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _052_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _053_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _054_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _055_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _056_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _057_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _058_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _059_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _060_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _061_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _062_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _063_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _064_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _065_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _066_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _067_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _068_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _069_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _070_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _071_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _072_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _073_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _074_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _075_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _076_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _077_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _078_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _079_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _080_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _081_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _082_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _083_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _084_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _085_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _086_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _087_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _088_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _089_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _090_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _091_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _092_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _093_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _094_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _095_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _096_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _097_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _098_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _099_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _100_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _101_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _102_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _103_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _104_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _105_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _106_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _107_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _108_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _109_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _110_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _111_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _112_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _113_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _114_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _115_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _116_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _117_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _118_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _119_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _120_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _121_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _122_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _123_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _124_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _125_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _126_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _127_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _128_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _129_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _130_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _131_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _132_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _133_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _134_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _135_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _136_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _137_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _138_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _139_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _140_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _141_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _142_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _143_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _144_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _145_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _146_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _147_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _148_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _149_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _150_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _151_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _152_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _153_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _154_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _155_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _156_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _157_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _158_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _159_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _160_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _161_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _162_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _163_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _164_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _165_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _166_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _167_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _168_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _169_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _170_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _171_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _172_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _173_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _174_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _175_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _176_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _177_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _178_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _179_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _180_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _181_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _182_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _183_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _184_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _185_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _186_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _187_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _188_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _189_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _190_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _191_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _192_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _193_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _194_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _195_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _196_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _197_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _198_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _199_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _200_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _201_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _202_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _203_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _204_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _205_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _206_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _207_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _208_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _209_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _210_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _211_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _212_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _213_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _214_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _215_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _216_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _217_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _218_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _219_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _220_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _221_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _222_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _223_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _224_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _225_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _226_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _227_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _228_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _229_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _230_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _231_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _232_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _233_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _234_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _235_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _236_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _237_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _238_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _239_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _240_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _241_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _242_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _243_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _244_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _245_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _246_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _247_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _248_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _249_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _250_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _251_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _252_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _253_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _254_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _255_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _256_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _257_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _258_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _259_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _260_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _261_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _262_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _263_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _264_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _265_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _266_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _267_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _268_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _269_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _270_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _271_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _272_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _273_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _274_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _275_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _276_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _277_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _278_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _279_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _280_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _281_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _282_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _283_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _284_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _285_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _286_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _287_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _288_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _289_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _290_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _291_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _292_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _293_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _294_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _295_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _296_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _297_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _298_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _299_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _300_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _301_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _302_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _303_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _304_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _305_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _306_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _307_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _308_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _309_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _310_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _311_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _312_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _313_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _314_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _315_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _316_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _317_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _318_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _319_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _320_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _321_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _322_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _323_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _324_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _325_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _326_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _327_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _328_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _329_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _330_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _331_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _332_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _333_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _334_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _335_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _336_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _337_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _338_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _339_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _340_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _341_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _342_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _343_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _344_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _345_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _346_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _347_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _348_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _349_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _350_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _351_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _352_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _353_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _354_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _355_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _356_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _357_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _358_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _359_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _360_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _361_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _362_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _363_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _364_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _365_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _366_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _367_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _368_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _369_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _370_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _371_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _372_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _373_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _374_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _375_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _376_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _377_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _378_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _379_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _380_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _381_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _382_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _383_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _384_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _385_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _386_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _387_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _388_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _389_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _390_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _391_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _392_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _393_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _394_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _395_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _396_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _397_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _398_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _399_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _400_ DFF_X1 + PLACED ( 38680 123252 ) N ; END COMPONENTS PINS 3 ; - - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal6 ( -140 -140 ) ( 140 140 ) - + PLACED ( 254430 140 ) N ; - - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal6 ( -140 -140 ) ( 140 140 ) - + PLACED ( 238750 140 ) N ; - - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal6 ( -140 -140 ) ( 140 140 ) - + PLACED ( 234270 140 ) N ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ; + - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL ; + - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL ; END PINS NETS 3 ; - io_1 ( PIN io_1 ) + USE SIGNAL ; diff --git a/src/mpl/test/io_constraints3.ok b/src/mpl/test/io_constraints3.ok index 6ce849d4603..07a50199eed 100644 --- a/src/mpl/test/io_constraints3.ok +++ b/src/mpl/test/io_constraints3.ok @@ -5,13 +5,6 @@ [INFO ODB-0128] Design: io_constraints1 [INFO ODB-0252] Updated 3 pins. [INFO ODB-0253] Updated 401 components. -Found 1 macro blocks. -Using 2 tracks default min distance between IO pins. -[INFO PPL-0001] Number of available slots 569 -[INFO PPL-0002] Number of I/O 3 -[INFO PPL-0003] Number of I/O w/sink 0 -[INFO PPL-0004] Number of I/O w/o sink 3 -[INFO PPL-0012] I/O nets HPWL: 0.00 um. Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) Number of std cell instances: 400 Area of std cell instances: 1808.79 diff --git a/src/mpl/test/io_constraints3.tcl b/src/mpl/test/io_constraints3.tcl index 0dbbe45b267..94cd6b9bc64 100644 --- a/src/mpl/test/io_constraints3.tcl +++ b/src/mpl/test/io_constraints3.tcl @@ -12,10 +12,7 @@ read_verilog "./testcases/io_constraints1.v" link_design "io_constraints1" read_def "./testcases/io_constraints1.def" -floorplan_initialize -# Run random PPL to incorporate the -exclude constraints into ODB -place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 \ - -exclude right:40-125 \ - -exclude top:10-150 +exclude_io_pin_region -region right:10-125 -region top:10-150 set_thread_count 0 rtl_macro_placer -report_directory results/io_constraints3 -halo_width 4.0 diff --git a/src/mpl/test/io_constraints4.defok b/src/mpl/test/io_constraints4.defok index b49e8312d10..75142f8a994 100644 --- a/src/mpl/test/io_constraints4.defok +++ b/src/mpl/test/io_constraints4.defok @@ -114,421 +114,412 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8290 ) FS ; - - _001_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _002_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _003_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _004_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _005_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _006_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _007_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _008_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _009_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _010_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _011_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _012_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _013_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _014_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _015_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _016_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _017_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _018_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _019_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _020_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _021_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _022_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _023_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _024_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _025_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _026_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _027_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _028_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _029_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _030_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _031_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _032_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _033_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _034_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _035_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _036_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _037_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _038_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _039_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _040_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _041_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _042_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _043_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _044_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _045_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _046_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _047_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _048_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _049_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _050_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _051_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _052_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _053_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _054_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _055_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _056_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _057_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _058_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _059_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _060_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _061_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _062_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _063_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _064_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _065_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _066_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _067_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _068_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _069_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _070_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _071_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _072_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _073_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _074_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _075_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _076_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _077_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _078_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _079_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _080_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _081_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _082_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _083_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _084_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _085_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _086_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _087_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _088_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _089_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _090_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _091_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _092_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _093_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _094_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _095_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _096_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _097_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _098_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _099_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _100_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _101_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _102_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _103_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _104_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _105_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _106_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _107_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _108_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _109_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _110_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _111_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _112_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _113_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _114_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _115_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _116_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _117_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _118_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _119_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _120_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _121_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _122_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _123_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _124_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _125_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _126_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _127_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _128_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _129_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _130_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _131_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _132_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _133_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _134_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _135_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _136_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _137_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _138_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _139_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _140_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _141_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _142_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _143_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _144_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _145_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _146_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _147_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _148_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _149_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _150_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _151_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _152_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _153_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _154_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _155_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _156_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _157_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _158_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _159_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _160_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _161_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _162_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _163_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _164_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _165_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _166_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _167_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _168_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _169_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _170_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _171_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _172_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _173_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _174_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _175_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _176_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _177_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _178_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _179_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _180_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _181_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _182_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _183_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _184_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _185_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _186_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _187_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _188_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _189_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _190_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _191_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _192_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _193_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _194_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _195_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _196_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _197_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _198_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _199_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _200_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _201_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _202_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _203_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _204_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _205_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _206_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _207_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _208_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _209_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _210_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _211_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _212_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _213_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _214_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _215_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _216_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _217_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _218_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _219_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _220_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _221_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _222_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _223_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _224_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _225_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _226_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _227_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _228_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _229_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _230_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _231_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _232_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _233_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _234_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _235_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _236_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _237_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _238_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _239_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _240_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _241_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _242_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _243_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _244_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _245_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _246_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _247_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _248_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _249_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _250_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _251_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _252_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _253_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _254_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _255_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _256_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _257_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _258_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _259_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _260_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _261_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _262_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _263_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _264_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _265_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _266_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _267_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _268_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _269_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _270_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _271_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _272_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _273_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _274_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _275_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _276_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _277_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _278_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _279_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _280_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _281_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _282_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _283_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _284_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _285_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _286_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _287_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _288_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _289_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _290_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _291_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _292_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _293_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _294_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _295_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _296_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _297_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _298_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _299_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _300_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _301_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _302_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _303_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _304_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _305_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _306_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _307_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _308_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _309_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _310_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _311_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _312_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _313_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _314_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _315_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _316_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _317_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _318_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _319_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _320_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _321_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _322_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _323_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _324_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _325_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _326_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _327_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _328_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _329_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _330_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _331_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _332_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _333_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _334_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _335_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _336_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _337_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _338_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _339_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _340_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _341_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _342_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _343_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _344_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _345_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _346_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _347_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _348_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _349_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _350_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _351_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _352_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _353_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _354_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _355_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _356_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _357_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _358_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _359_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _360_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _361_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _362_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _363_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _364_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _365_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _366_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _367_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _368_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _369_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _370_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _371_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _372_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _373_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _374_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _375_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _376_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _377_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _378_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _379_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _380_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _381_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _382_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _383_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _384_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _385_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _386_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _387_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _388_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _389_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _390_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _391_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _392_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _393_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _394_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _395_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _396_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _397_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _398_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _399_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _400_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8010 ) FS ; + - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _004_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _005_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _006_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _007_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _008_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _009_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _010_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _011_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _012_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _013_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _014_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _015_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _016_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _017_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _018_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _019_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _020_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _021_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _022_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _023_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _024_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _025_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _026_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _027_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _028_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _029_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _030_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _031_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _032_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _033_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _034_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _035_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _036_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _037_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _038_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _039_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _040_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _041_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _042_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _043_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _044_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _045_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _046_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _047_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _048_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _049_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _050_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _051_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _052_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _053_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _054_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _055_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _056_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _057_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _058_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _059_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _060_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _061_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _062_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _063_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _064_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _065_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _066_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _067_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _068_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _069_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _070_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _071_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _072_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _073_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _074_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _075_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _076_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _077_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _078_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _079_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _080_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _081_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _082_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _083_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _084_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _085_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _086_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _087_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _088_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _089_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _090_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _091_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _092_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _093_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _094_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _095_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _096_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _097_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _098_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _099_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _100_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _101_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _102_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _103_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _104_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _105_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _106_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _107_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _108_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _109_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _110_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _111_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _112_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _113_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _114_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _115_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _116_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _117_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _118_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _119_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _120_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _121_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _122_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _123_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _124_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _125_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _126_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _127_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _128_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _129_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _130_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _131_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _132_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _133_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _134_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _135_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _136_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _137_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _138_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _139_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _140_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _141_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _142_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _143_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _144_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _145_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _146_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _147_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _148_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _149_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _150_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _151_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _152_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _153_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _154_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _155_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _156_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _157_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _158_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _159_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _160_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _161_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _162_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _163_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _164_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _165_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _166_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _167_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _168_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _169_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _170_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _171_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _172_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _173_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _174_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _175_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _176_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _177_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _178_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _179_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _180_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _181_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _182_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _183_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _184_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _185_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _186_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _187_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _188_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _189_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _190_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _191_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _192_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _193_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _194_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _195_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _196_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _197_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _198_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _199_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _200_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _201_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _202_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _203_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _204_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _205_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _206_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _207_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _208_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _209_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _210_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _211_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _212_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _213_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _214_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _215_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _216_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _217_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _218_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _219_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _220_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _221_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _222_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _223_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _224_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _225_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _226_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _227_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _228_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _229_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _230_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _231_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _232_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _233_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _234_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _235_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _236_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _237_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _238_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _239_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _240_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _241_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _242_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _243_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _244_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _245_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _246_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _247_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _248_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _249_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _250_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _251_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _252_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _253_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _254_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _255_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _256_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _257_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _258_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _259_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _260_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _261_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _262_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _263_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _264_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _265_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _266_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _267_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _268_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _269_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _270_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _271_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _272_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _273_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _274_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _275_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _276_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _277_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _278_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _279_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _280_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _281_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _282_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _283_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _284_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _285_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _286_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _287_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _288_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _289_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _290_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _291_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _292_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _293_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _294_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _295_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _296_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _297_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _298_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _299_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _300_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _301_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _302_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _303_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _304_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _305_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _306_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _307_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _308_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _309_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _310_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _311_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _312_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _313_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _314_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _315_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _316_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _317_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _318_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _319_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _320_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _321_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _322_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _323_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _324_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _325_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _326_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _327_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _328_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _329_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _330_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _331_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _332_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _333_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _334_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _335_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _336_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _337_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _338_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _339_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _340_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _341_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _342_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _343_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _344_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _345_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _346_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _347_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _348_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _349_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _350_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _351_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _352_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _353_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _354_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _355_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _356_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _357_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _358_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _359_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _360_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _361_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _362_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _363_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _364_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _365_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _366_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _367_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _368_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _369_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _370_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _371_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _372_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _373_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _374_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _375_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _376_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _377_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _378_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _379_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _380_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _381_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _382_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _383_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _384_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _385_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _386_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _387_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _388_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _389_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _390_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _391_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _392_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _393_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _394_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _395_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _396_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _397_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _398_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _399_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _400_ DFF_X1 + PLACED ( 38680 123252 ) N ; END COMPONENTS PINS 3 ; - - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 140 164780 ) N ; - - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 140 147980 ) N ; - - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 299860 178220 ) N ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ; + - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL ; + - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL ; END PINS NETS 3 ; - io_1 ( PIN io_1 ) + USE SIGNAL ; diff --git a/src/mpl/test/io_constraints4.ok b/src/mpl/test/io_constraints4.ok index ebed155024d..07a50199eed 100644 --- a/src/mpl/test/io_constraints4.ok +++ b/src/mpl/test/io_constraints4.ok @@ -5,15 +5,6 @@ [INFO ODB-0128] Design: io_constraints1 [INFO ODB-0252] Updated 3 pins. [INFO ODB-0253] Updated 401 components. -[INFO PPL-0048] Restrict pins [ io_1 io_2 ] to region 70.00u-90.00u at the LEFT edge. -[INFO PPL-0048] Restrict pins [ io_3 ] to region 70.00u-90.00u at the RIGHT edge. -Found 1 macro blocks. -Using 2 tracks default min distance between IO pins. -[INFO PPL-0001] Number of available slots 966 -[INFO PPL-0002] Number of I/O 3 -[INFO PPL-0003] Number of I/O w/sink 0 -[INFO PPL-0004] Number of I/O w/o sink 3 -[INFO PPL-0012] I/O nets HPWL: 0.00 um. Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) Number of std cell instances: 400 Area of std cell instances: 1808.79 diff --git a/src/mpl/test/io_constraints4.tcl b/src/mpl/test/io_constraints4.tcl index 37a6ce29cfe..f9c10156d84 100644 --- a/src/mpl/test/io_constraints4.tcl +++ b/src/mpl/test/io_constraints4.tcl @@ -1,7 +1,7 @@ # Test if pin access blockages are generated correctly for a case # with pins with different constraint regions. The region on the left -# edge has more pins and should have a larger blockage. The macro should, -# then, be placed closer to the right edge. +# edge has more pins and should have a larger blockage. +# The macro should be placed closer to the right edge. source "helpers.tcl" # We're not interested in the connections, so don't include the lib. @@ -17,9 +17,6 @@ read_def "./testcases/io_constraints1.def" -floorplan_initialize set_io_pin_constraint -pin_names {io_1 io_2} -region left:70-90 set_io_pin_constraint -pin_names {io_3} -region right:70-90 -# Run random PPL to incorporate the constraints into ODB -place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 - set_thread_count 0 rtl_macro_placer -report_directory results/io_constraints4 -halo_width 4.0 diff --git a/src/mpl/test/io_constraints5.defok b/src/mpl/test/io_constraints5.defok index 6eaf1c8411a..d0c4895431b 100644 --- a/src/mpl/test/io_constraints5.defok +++ b/src/mpl/test/io_constraints5.defok @@ -114,421 +114,412 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8290 ) FS ; - - _001_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _002_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _003_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _004_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _005_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _006_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _007_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _008_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _009_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _010_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _011_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _012_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _013_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _014_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _015_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _016_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _017_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _018_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _019_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _020_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _021_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _022_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _023_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _024_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _025_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _026_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _027_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _028_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _029_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _030_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _031_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _032_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _033_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _034_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _035_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _036_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _037_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _038_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _039_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _040_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _041_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _042_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _043_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _044_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _045_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _046_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _047_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _048_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _049_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _050_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _051_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _052_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _053_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _054_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _055_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _056_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _057_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _058_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _059_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _060_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _061_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _062_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _063_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _064_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _065_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _066_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _067_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _068_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _069_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _070_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _071_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _072_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _073_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _074_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _075_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _076_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _077_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _078_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _079_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _080_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _081_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _082_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _083_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _084_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _085_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _086_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _087_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _088_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _089_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _090_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _091_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _092_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _093_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _094_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _095_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _096_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _097_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _098_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _099_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _100_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _101_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _102_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _103_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _104_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _105_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _106_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _107_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _108_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _109_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _110_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _111_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _112_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _113_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _114_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _115_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _116_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _117_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _118_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _119_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _120_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _121_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _122_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _123_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _124_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _125_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _126_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _127_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _128_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _129_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _130_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _131_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _132_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _133_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _134_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _135_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _136_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _137_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _138_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _139_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _140_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _141_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _142_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _143_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _144_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _145_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _146_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _147_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _148_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _149_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _150_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _151_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _152_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _153_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _154_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _155_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _156_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _157_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _158_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _159_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _160_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _161_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _162_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _163_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _164_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _165_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _166_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _167_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _168_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _169_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _170_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _171_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _172_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _173_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _174_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _175_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _176_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _177_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _178_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _179_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _180_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _181_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _182_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _183_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _184_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _185_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _186_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _187_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _188_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _189_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _190_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _191_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _192_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _193_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _194_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _195_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _196_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _197_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _198_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _199_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _200_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _201_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _202_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _203_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _204_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _205_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _206_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _207_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _208_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _209_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _210_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _211_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _212_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _213_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _214_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _215_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _216_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _217_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _218_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _219_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _220_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _221_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _222_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _223_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _224_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _225_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _226_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _227_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _228_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _229_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _230_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _231_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _232_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _233_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _234_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _235_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _236_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _237_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _238_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _239_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _240_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _241_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _242_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _243_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _244_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _245_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _246_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _247_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _248_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _249_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _250_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _251_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _252_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _253_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _254_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _255_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _256_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _257_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _258_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _259_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _260_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _261_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _262_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _263_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _264_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _265_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _266_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _267_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _268_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _269_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _270_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _271_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _272_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _273_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _274_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _275_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _276_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _277_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _278_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _279_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _280_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _281_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _282_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _283_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _284_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _285_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _286_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _287_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _288_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _289_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _290_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _291_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _292_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _293_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _294_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _295_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _296_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _297_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _298_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _299_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _300_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _301_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _302_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _303_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _304_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _305_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _306_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _307_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _308_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _309_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _310_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _311_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _312_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _313_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _314_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _315_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _316_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _317_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _318_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _319_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _320_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _321_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _322_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _323_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _324_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _325_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _326_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _327_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _328_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _329_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _330_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _331_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _332_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _333_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _334_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _335_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _336_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _337_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _338_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _339_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _340_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _341_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _342_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _343_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _344_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _345_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _346_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _347_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _348_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _349_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _350_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _351_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _352_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _353_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _354_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _355_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _356_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _357_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _358_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _359_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _360_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _361_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _362_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _363_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _364_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _365_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _366_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _367_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _368_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _369_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _370_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _371_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _372_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _373_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _374_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _375_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _376_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _377_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _378_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _379_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _380_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _381_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _382_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _383_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _384_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _385_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _386_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _387_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _388_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _389_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _390_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _391_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _392_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _393_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _394_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _395_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _396_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _397_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _398_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _399_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _400_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8010 ) FS ; + - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _004_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _005_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _006_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _007_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _008_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _009_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _010_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _011_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _012_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _013_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _014_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _015_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _016_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _017_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _018_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _019_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _020_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _021_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _022_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _023_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _024_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _025_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _026_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _027_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _028_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _029_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _030_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _031_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _032_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _033_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _034_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _035_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _036_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _037_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _038_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _039_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _040_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _041_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _042_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _043_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _044_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _045_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _046_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _047_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _048_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _049_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _050_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _051_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _052_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _053_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _054_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _055_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _056_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _057_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _058_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _059_ DFF_X1 + PLACED ( 254680 123252 ) N ; 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+ - _312_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _313_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _314_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _315_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _316_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _317_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _318_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _319_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _320_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _321_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _322_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _323_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _324_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _325_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _326_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _327_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _328_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _329_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _330_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _331_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _332_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _333_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _334_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _335_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _336_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _337_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _338_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _339_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _340_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _341_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _342_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _343_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _344_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _345_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _346_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _347_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _348_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _349_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _350_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _351_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _352_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _353_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _354_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _355_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _356_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _357_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _358_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _359_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _360_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _361_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _362_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _363_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _364_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _365_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _366_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _367_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _368_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _369_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _370_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _371_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _372_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _373_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _374_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _375_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _376_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _377_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _378_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _379_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _380_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _381_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _382_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _383_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _384_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _385_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _386_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _387_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _388_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _389_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _390_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _391_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _392_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _393_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _394_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _395_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _396_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _397_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _398_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _399_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _400_ DFF_X1 + PLACED ( 254680 123252 ) N ; END COMPONENTS PINS 3 ; - - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 299860 154700 ) N ; - - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 299860 171500 ) N ; - - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 299860 96460 ) N ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ; + - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL ; + - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL ; END PINS NETS 3 ; - io_1 ( PIN io_1 ) + USE SIGNAL ; diff --git a/src/mpl/test/io_constraints5.ok b/src/mpl/test/io_constraints5.ok index c4547a869b3..07a50199eed 100644 --- a/src/mpl/test/io_constraints5.ok +++ b/src/mpl/test/io_constraints5.ok @@ -5,15 +5,6 @@ [INFO ODB-0128] Design: io_constraints1 [INFO ODB-0252] Updated 3 pins. [INFO ODB-0253] Updated 401 components. -[INFO PPL-0048] Restrict pins [ io_1 io_2 ] to region 70.00u-90.00u at the RIGHT edge. -[INFO PPL-0048] Restrict pins [ io_3 ] to region 10.00u-50.00u at the RIGHT edge. -Found 1 macro blocks. -Using 2 tracks default min distance between IO pins. -[INFO PPL-0001] Number of available slots 966 -[INFO PPL-0002] Number of I/O 3 -[INFO PPL-0003] Number of I/O w/sink 0 -[INFO PPL-0004] Number of I/O w/o sink 3 -[INFO PPL-0012] I/O nets HPWL: 0.00 um. Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) Number of std cell instances: 400 Area of std cell instances: 1808.79 diff --git a/src/mpl/test/io_constraints5.tcl b/src/mpl/test/io_constraints5.tcl index 94328e9b194..babed5b84fb 100644 --- a/src/mpl/test/io_constraints5.tcl +++ b/src/mpl/test/io_constraints5.tcl @@ -16,9 +16,6 @@ read_def "./testcases/io_constraints1.def" -floorplan_initialize set_io_pin_constraint -pin_names {io_1 io_2} -region right:70-90 set_io_pin_constraint -pin_names {io_3} -region right:10-50 -# Run random PPL to incorporate the constraints into ODB -place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 - set_thread_count 0 rtl_macro_placer -report_directory results/io_constraints5 -halo_width 4.0 diff --git a/src/mpl/test/io_constraints6.defok b/src/mpl/test/io_constraints6.defok index 6ae081c0d80..8652f21d6b8 100644 --- a/src/mpl/test/io_constraints6.defok +++ b/src/mpl/test/io_constraints6.defok @@ -114,425 +114,412 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8290 ) FS ; - - _001_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _002_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _003_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _004_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _005_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _006_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _007_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _008_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _009_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _010_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _011_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _012_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _013_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _014_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _015_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _016_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _017_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _018_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _019_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _020_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _021_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _022_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _023_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _024_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _025_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _026_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _027_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _028_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _029_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _030_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _031_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _032_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _033_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _034_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _035_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _036_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _037_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _038_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _039_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _040_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _041_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _042_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _043_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _044_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _045_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _046_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _047_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _048_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _049_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _050_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _051_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _052_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _053_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _054_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _055_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _056_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _057_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _058_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _059_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _060_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _061_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _062_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _063_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _064_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _065_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _066_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _067_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _068_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _069_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _070_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _071_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _072_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _073_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _074_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _075_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _076_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _077_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _078_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _079_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _080_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _081_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _082_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _083_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _084_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _085_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _086_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _087_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _088_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _089_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _090_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _091_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _092_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _093_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _094_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _095_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _096_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _097_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _098_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _099_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _100_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _101_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _102_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _103_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _104_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _105_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _106_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _107_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _108_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _109_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _110_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _111_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _112_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _113_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _114_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _115_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _116_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _117_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _118_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _119_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _120_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _121_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _122_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _123_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _124_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _125_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _126_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _127_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _128_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _129_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _130_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _131_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _132_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _133_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _134_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _135_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _136_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _137_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _138_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _139_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _140_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _141_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _142_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _143_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _144_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _145_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _146_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _147_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _148_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _149_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _150_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _151_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _152_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _153_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _154_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _155_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _156_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _157_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _158_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _159_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _160_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _161_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _162_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _163_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _164_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _165_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _166_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _167_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _168_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _169_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _170_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _171_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _172_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _173_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _174_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _175_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _176_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _177_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _178_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _179_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _180_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _181_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _182_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _183_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _184_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _185_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _186_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _187_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _188_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _189_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _190_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _191_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _192_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _193_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _194_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _195_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _196_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _197_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _198_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _199_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _200_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _201_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _202_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _203_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _204_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _205_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _206_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _207_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _208_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _209_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _210_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _211_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _212_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _213_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _214_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _215_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _216_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _217_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _218_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _219_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _220_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _221_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _222_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _223_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _224_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _225_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _226_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _227_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _228_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _229_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _230_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _231_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _232_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _233_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _234_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _235_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _236_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _237_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _238_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _239_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _240_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _241_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _242_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _243_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _244_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _245_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _246_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _247_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _248_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _249_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _250_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _251_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _252_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _253_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _254_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _255_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _256_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _257_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _258_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _259_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _260_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _261_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _262_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _263_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _264_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _265_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _266_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _267_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _268_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _269_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _270_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _271_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _272_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _273_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _274_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _275_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _276_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _277_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _278_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _279_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _280_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _281_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _282_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _283_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _284_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _285_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _286_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _287_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _288_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _289_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _290_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _291_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _292_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _293_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _294_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _295_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _296_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _297_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _298_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _299_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _300_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _301_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _302_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _303_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _304_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _305_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _306_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _307_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _308_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _309_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _310_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _311_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _312_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _313_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _314_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _315_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _316_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _317_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _318_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _319_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _320_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _321_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _322_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _323_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _324_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _325_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _326_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _327_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _328_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _329_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _330_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _331_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _332_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _333_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _334_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _335_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _336_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _337_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _338_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _339_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _340_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _341_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _342_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _343_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _344_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _345_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _346_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _347_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _348_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _349_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _350_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _351_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _352_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _353_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _354_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _355_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _356_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _357_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _358_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _359_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _360_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _361_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _362_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _363_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _364_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _365_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _366_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _367_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _368_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _369_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _370_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _371_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _372_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _373_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _374_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _375_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _376_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _377_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _378_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _379_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _380_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _381_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _382_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _383_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _384_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _385_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _386_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _387_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _388_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _389_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _390_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _391_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _392_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _393_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _394_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _395_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _396_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _397_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _398_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _399_ DFF_X1 + PLACED ( 38680 123234 ) N ; - - _400_ DFF_X1 + PLACED ( 38680 123234 ) N ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8010 ) S ; + - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _004_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _005_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _006_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _007_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _008_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _009_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _010_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _011_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _012_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _013_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _014_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _015_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _016_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _017_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _018_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _019_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _020_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _021_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _022_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _023_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _024_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _025_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _026_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _027_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _028_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _029_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _030_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _031_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _032_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _033_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _034_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _035_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _036_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _037_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _038_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _039_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _040_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _041_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _042_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _043_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _044_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _045_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _046_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _047_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _048_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _049_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _050_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _051_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _052_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _053_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _054_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _055_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _056_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _057_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _058_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _059_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _060_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _061_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _062_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _063_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _064_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _065_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _066_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _067_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _068_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _069_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _070_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _071_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _072_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _073_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _074_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _075_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _076_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _077_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _078_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _079_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _080_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _081_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _082_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _083_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _084_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _085_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _086_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _087_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _088_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _089_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _090_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _091_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _092_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _093_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _094_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _095_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _096_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _097_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _098_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _099_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _100_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _101_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _102_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _103_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _104_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _105_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _106_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _107_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _108_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _109_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _110_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _111_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _112_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _113_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _114_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _115_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _116_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _117_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _118_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _119_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _120_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _121_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _122_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _123_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _124_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _125_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _126_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _127_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _128_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _129_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _130_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _131_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _132_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _133_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _134_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _135_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _136_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _137_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _138_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _139_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _140_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _141_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _142_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _143_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _144_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _145_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _146_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _147_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _148_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _149_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _150_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _151_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _152_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _153_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _154_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _155_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _156_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _157_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _158_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _159_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _160_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _161_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _162_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _163_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _164_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _165_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _166_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _167_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _168_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _169_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _170_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _171_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _172_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _173_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _174_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _175_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _176_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _177_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _178_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _179_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _180_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _181_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _182_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _183_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _184_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _185_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _186_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _187_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _188_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _189_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _190_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _191_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _192_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _193_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _194_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _195_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _196_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _197_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _198_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _199_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _200_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _201_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _202_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _203_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _204_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _205_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _206_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _207_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _208_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _209_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _210_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _211_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _212_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _213_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _214_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _215_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _216_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _217_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _218_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _219_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _220_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _221_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _222_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _223_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _224_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _225_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _226_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _227_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _228_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _229_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _230_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _231_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _232_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _233_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _234_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _235_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _236_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _237_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _238_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _239_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _240_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _241_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _242_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _243_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _244_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _245_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _246_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _247_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _248_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _249_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _250_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _251_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _252_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _253_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _254_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _255_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _256_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _257_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _258_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _259_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _260_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _261_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _262_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _263_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _264_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _265_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _266_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _267_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _268_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _269_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _270_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _271_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _272_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _273_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _274_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _275_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _276_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _277_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _278_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _279_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _280_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _281_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _282_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _283_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _284_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _285_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _286_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _287_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _288_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _289_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _290_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _291_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _292_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _293_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _294_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _295_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _296_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _297_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _298_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _299_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _300_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _301_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _302_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _303_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _304_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _305_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _306_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _307_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _308_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _309_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _310_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _311_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _312_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _313_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _314_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _315_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _316_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _317_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _318_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _319_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _320_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _321_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _322_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _323_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _324_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _325_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _326_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _327_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _328_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _329_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _330_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _331_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _332_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _333_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _334_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _335_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _336_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _337_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _338_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _339_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _340_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _341_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _342_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _343_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _344_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _345_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _346_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _347_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _348_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _349_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _350_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _351_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _352_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _353_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _354_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _355_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _356_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _357_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _358_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _359_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _360_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _361_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _362_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _363_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _364_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _365_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _366_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _367_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _368_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _369_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _370_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _371_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _372_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _373_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _374_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _375_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _376_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _377_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _378_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _379_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _380_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _381_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _382_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _383_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _384_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _385_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _386_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _387_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _388_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _389_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _390_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _391_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _392_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _393_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _394_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _395_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _396_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _397_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _398_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _399_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _400_ DFF_X1 + PLACED ( 254680 123252 ) N ; END COMPONENTS -PINS 3 ; - - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal6 ( -140 -140 ) ( 140 140 ) - + PLACED ( 254430 140 ) N ; - - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal6 ( -140 -140 ) ( 140 140 ) - + PLACED ( 238750 140 ) N ; - - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal6 ( -140 -140 ) ( 140 140 ) - + PLACED ( 234270 140 ) N ; +PINS 1 ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ; END PINS -NETS 3 ; +NETS 1 ; - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ; - - io_2 ( PIN io_2 ) ( MACRO_1 O1 ) + USE SIGNAL ; - - io_3 ( PIN io_3 ) + USE SIGNAL ; END NETS END DESIGN diff --git a/src/mpl/test/io_constraints6.ok b/src/mpl/test/io_constraints6.ok index 261daa15aad..b84e5c61fe4 100644 --- a/src/mpl/test/io_constraints6.ok +++ b/src/mpl/test/io_constraints6.ok @@ -1,16 +1,9 @@ [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells [INFO ODB-0227] LEF file: testcases/macro_only.lef, created 9 library cells [INFO ODB-0128] Design: io_constraints1 -[INFO ODB-0130] Created 3 pins. +[INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 401 components and 2402 component-terminals. -[INFO ODB-0133] Created 2 nets and 2 connections. -Found 1 macro blocks. -Using 2 tracks default min distance between IO pins. -[INFO PPL-0001] Number of available slots 569 -[INFO PPL-0002] Number of I/O 3 -[INFO PPL-0003] Number of I/O w/sink 2 -[INFO PPL-0004] Number of I/O w/o sink 1 -[INFO PPL-0012] I/O nets HPWL: 221.59 um. +[INFO ODB-0133] Created 1 nets and 1 connections. Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) Number of std cell instances: 400 Area of std cell instances: 1808.79 diff --git a/src/mpl/test/io_constraints6.tcl b/src/mpl/test/io_constraints6.tcl index 8b521996673..aa77f892fad 100644 --- a/src/mpl/test/io_constraints6.tcl +++ b/src/mpl/test/io_constraints6.tcl @@ -9,10 +9,8 @@ read_liberty Nangate45/Nangate45_fast.lib read_def testcases/io_constraints6.def -# Run random PPL to incorporate the -exclude constraints into ODB -place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 \ - -exclude right:40-125 \ - -exclude top:10-150 +exclude_io_pin_region -region bottom:* -region left:* \ + -region top:40-150 -region right:40-125 set_thread_count 0 rtl_macro_placer -report_directory results/io_constraints6 -halo_width 4.0 diff --git a/src/mpl/test/io_constraints7.defok b/src/mpl/test/io_constraints7.defok index 19447be3129..50cd3a1e2b6 100644 --- a/src/mpl/test/io_constraints7.defok +++ b/src/mpl/test/io_constraints7.defok @@ -114,425 +114,412 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8150 ) N ; - - _001_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _002_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _003_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _004_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _005_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _006_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _007_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _008_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _009_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _010_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _011_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _012_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _013_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _014_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _015_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _016_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _017_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _018_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _019_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _020_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _021_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _022_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _023_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _024_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _025_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _026_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _027_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _028_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _029_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _030_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _031_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _032_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _033_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _034_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _035_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _036_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _037_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _038_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _039_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _040_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _041_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _042_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _043_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _044_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _045_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _046_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _047_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _048_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _049_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _050_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _051_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _052_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _053_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _054_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _055_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _056_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _057_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _058_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _059_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _060_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _061_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _062_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _063_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _064_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _065_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _066_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _067_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _068_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _069_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _070_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _071_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _072_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _073_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _074_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _075_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _076_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _077_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _078_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _079_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _080_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _081_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _082_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _083_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _084_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _085_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _086_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _087_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _088_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _089_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _090_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _091_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _092_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _093_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _094_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _095_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _096_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _097_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _098_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _099_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _100_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _101_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _102_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _103_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _104_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _105_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _106_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _107_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _108_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _109_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _110_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _111_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _112_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _113_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _114_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _115_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _116_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _117_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _118_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _119_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _120_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _121_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _122_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _123_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _124_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _125_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _126_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _127_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _128_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _129_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _130_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _131_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _132_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _133_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _134_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _135_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _136_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _137_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _138_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _139_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _140_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _141_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _142_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _143_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _144_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _145_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _146_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _147_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _148_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _149_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _150_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _151_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _152_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _153_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _154_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _155_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _156_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _157_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _158_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _159_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _160_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _161_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _162_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _163_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _164_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _165_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _166_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _167_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _168_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _169_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _170_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _171_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _172_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _173_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _174_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _175_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _176_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _177_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _178_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _179_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _180_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _181_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _182_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _183_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _184_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _185_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _186_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _187_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _188_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _189_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _190_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _191_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _192_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _193_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _194_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _195_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _196_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _197_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _198_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _199_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _200_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _201_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _202_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _203_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _204_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _205_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _206_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _207_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _208_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _209_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _210_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _211_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _212_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _213_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _214_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _215_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _216_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _217_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _218_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _219_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _220_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _221_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _222_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _223_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _224_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _225_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _226_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _227_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _228_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _229_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _230_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _231_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _232_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _233_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _234_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _235_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _236_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _237_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _238_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _239_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _240_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _241_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _242_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _243_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _244_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _245_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _246_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _247_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _248_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _249_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _250_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _251_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _252_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _253_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _254_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _255_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _256_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _257_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _258_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _259_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _260_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _261_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _262_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _263_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _264_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _265_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _266_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _267_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _268_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _269_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _270_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _271_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _272_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _273_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _274_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _275_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _276_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _277_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _278_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _279_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _280_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _281_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _282_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _283_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _284_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _285_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _286_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _287_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _288_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _289_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _290_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _291_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _292_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _293_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _294_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _295_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _296_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _297_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _298_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _299_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _300_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _301_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _302_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _303_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _304_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _305_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _306_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _307_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _308_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _309_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _310_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _311_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _312_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _313_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _314_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _315_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _316_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _317_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _318_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _319_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _320_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _321_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _322_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _323_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _324_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _325_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _326_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _327_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _328_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _329_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _330_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _331_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _332_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _333_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _334_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _335_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _336_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _337_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _338_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _339_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _340_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _341_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _342_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _343_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _344_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _345_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _346_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _347_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _348_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _349_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _350_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _351_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _352_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _353_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _354_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _355_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _356_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _357_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _358_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _359_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _360_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _361_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _362_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _363_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _364_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _365_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _366_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _367_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _368_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _369_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _370_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _371_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _372_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _373_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _374_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _375_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _376_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _377_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _378_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _379_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _380_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _381_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _382_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _383_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _384_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _385_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _386_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _387_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _388_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _389_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _390_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _391_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _392_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _393_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _394_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _395_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _396_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _397_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _398_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _399_ DFF_X1 + PLACED ( 254680 123234 ) N ; - - _400_ DFF_X1 + PLACED ( 254680 123234 ) N ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 24670 ) N ; + - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _004_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _005_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _006_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _007_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _008_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _009_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _010_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _011_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _012_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _013_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _014_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _015_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _016_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _017_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _018_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _019_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _020_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _021_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _022_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _023_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _024_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _025_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _026_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _027_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _028_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _029_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _030_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _031_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _032_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _033_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _034_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _035_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _036_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _037_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _038_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _039_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _040_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _041_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _042_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _043_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _044_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _045_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _046_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _047_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _048_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _049_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _050_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _051_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _052_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _053_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _054_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _055_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _056_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _057_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _058_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _059_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _060_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _061_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _062_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _063_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _064_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _065_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _066_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _067_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _068_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _069_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _070_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _071_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _072_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _073_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _074_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _075_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _076_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _077_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _078_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _079_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _080_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _081_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _082_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _083_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _084_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _085_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _086_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _087_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _088_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _089_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _090_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _091_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _092_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _093_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _094_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _095_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _096_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _097_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _098_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _099_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _100_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _101_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _102_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _103_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _104_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _105_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _106_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _107_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _108_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _109_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _110_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _111_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _112_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _113_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _114_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _115_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _116_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _117_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _118_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _119_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _120_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _121_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _122_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _123_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _124_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _125_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _126_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _127_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _128_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _129_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _130_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _131_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _132_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _133_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _134_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _135_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _136_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _137_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _138_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _139_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _140_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _141_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _142_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _143_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _144_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _145_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _146_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _147_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _148_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _149_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _150_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _151_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _152_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _153_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _154_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _155_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _156_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _157_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _158_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _159_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _160_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _161_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _162_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _163_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _164_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _165_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _166_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _167_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _168_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _169_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _170_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _171_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _172_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _173_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _174_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _175_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _176_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _177_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _178_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _179_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _180_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _181_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _182_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _183_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _184_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _185_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _186_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _187_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _188_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _189_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _190_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _191_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _192_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _193_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _194_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _195_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _196_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _197_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _198_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _199_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _200_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _201_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _202_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _203_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _204_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _205_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _206_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _207_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _208_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _209_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _210_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _211_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _212_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _213_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _214_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _215_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _216_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _217_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _218_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _219_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _220_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _221_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _222_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _223_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _224_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _225_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _226_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _227_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _228_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _229_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _230_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _231_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _232_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _233_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _234_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _235_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _236_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _237_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _238_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _239_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _240_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _241_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _242_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _243_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _244_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _245_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _246_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _247_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _248_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _249_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _250_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _251_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _252_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _253_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _254_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _255_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _256_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _257_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _258_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _259_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _260_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _261_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _262_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _263_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _264_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _265_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _266_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _267_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _268_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _269_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _270_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _271_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _272_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _273_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _274_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _275_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _276_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _277_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _278_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _279_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _280_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _281_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _282_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _283_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _284_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _285_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _286_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _287_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _288_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _289_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _290_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _291_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _292_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _293_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _294_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _295_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _296_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _297_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _298_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _299_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _300_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _301_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _302_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _303_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _304_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _305_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _306_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _307_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _308_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _309_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _310_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _311_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _312_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _313_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _314_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _315_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _316_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _317_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _318_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _319_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _320_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _321_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _322_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _323_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _324_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _325_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _326_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _327_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _328_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _329_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _330_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _331_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _332_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _333_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _334_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _335_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _336_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _337_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _338_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _339_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _340_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _341_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _342_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _343_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _344_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _345_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _346_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _347_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _348_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _349_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _350_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _351_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _352_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _353_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _354_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _355_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _356_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _357_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _358_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _359_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _360_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _361_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _362_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _363_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _364_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _365_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _366_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _367_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _368_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _369_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _370_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _371_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _372_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _373_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _374_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _375_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _376_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _377_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _378_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _379_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _380_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _381_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _382_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _383_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _384_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _385_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _386_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _387_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _388_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _389_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _390_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _391_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _392_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _393_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _394_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _395_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _396_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _397_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _398_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _399_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _400_ DFF_X1 + PLACED ( 254680 123252 ) N ; END COMPONENTS -PINS 3 ; - - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 140 164780 ) N ; - - io_2 + NET io_2 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 140 147980 ) N ; - - io_3 + NET io_3 + DIRECTION INPUT + USE SIGNAL - + PORT - + LAYER metal5 ( -140 -140 ) ( 140 140 ) - + PLACED ( 299860 178220 ) N ; +PINS 1 ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ; END PINS -NETS 3 ; +NETS 1 ; - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ; - - io_2 ( PIN io_2 ) ( MACRO_1 O1 ) + USE SIGNAL ; - - io_3 ( PIN io_3 ) + USE SIGNAL ; END NETS END DESIGN diff --git a/src/mpl/test/io_constraints7.ok b/src/mpl/test/io_constraints7.ok index edee25b88b4..b84e5c61fe4 100644 --- a/src/mpl/test/io_constraints7.ok +++ b/src/mpl/test/io_constraints7.ok @@ -1,18 +1,9 @@ [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells [INFO ODB-0227] LEF file: testcases/macro_only.lef, created 9 library cells [INFO ODB-0128] Design: io_constraints1 -[INFO ODB-0130] Created 3 pins. +[INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 401 components and 2402 component-terminals. -[INFO ODB-0133] Created 2 nets and 2 connections. -[INFO PPL-0048] Restrict pins [ io_1 io_2 ] to region 70.00u-90.00u at the LEFT edge. -[INFO PPL-0048] Restrict pins [ io_3 ] to region 70.00u-90.00u at the RIGHT edge. -Found 1 macro blocks. -Using 2 tracks default min distance between IO pins. -[INFO PPL-0001] Number of available slots 966 -[INFO PPL-0002] Number of I/O 3 -[INFO PPL-0003] Number of I/O w/sink 2 -[INFO PPL-0004] Number of I/O w/o sink 1 -[INFO PPL-0012] I/O nets HPWL: 181.38 um. +[INFO ODB-0133] Created 1 nets and 1 connections. Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) Number of std cell instances: 400 Area of std cell instances: 1808.79 diff --git a/src/mpl/test/io_constraints7.tcl b/src/mpl/test/io_constraints7.tcl index b2bf780783c..23e511980bd 100644 --- a/src/mpl/test/io_constraints7.tcl +++ b/src/mpl/test/io_constraints7.tcl @@ -1,14 +1,5 @@ # Test if the bundled nets inside annealing are correct for a block with # pins with different constraint regions and Macro -> IO connections. - -# -# -# -# TO DO: This test requires the fix terminal bug fix in order to work! -# -# -# - source "helpers.tcl" read_lef Nangate45/Nangate45.lef @@ -18,11 +9,7 @@ read_liberty Nangate45/Nangate45_fast.lib read_def testcases/io_constraints6.def -set_io_pin_constraint -pin_names {io_1 io_2} -region left:70-90 -set_io_pin_constraint -pin_names {io_3} -region right:70-90 - -# Run random PPL to incorporate the constraints into ODB -place_pins -annealing -random -hor_layers metal5 -ver_layer metal6 +set_io_pin_constraint -pin_names {io_1} -region left:70-90 set_thread_count 0 rtl_macro_placer -report_directory results/io_constraints6 -halo_width 4.0 diff --git a/src/mpl/test/testcases/io_constraints6.def b/src/mpl/test/testcases/io_constraints6.def index e33e9f05980..4b392f74b9f 100644 --- a/src/mpl/test/testcases/io_constraints6.def +++ b/src/mpl/test/testcases/io_constraints6.def @@ -517,15 +517,12 @@ COMPONENTS 401 ; - _400_ DFF_X1 ; END COMPONENTS -PINS 2 ; +PINS 1 ; - io_1 + NET io_1 ; - - io_2 + NET io_2 ; - - io_3 + NET io_3 ; END PINS -NETS 2 ; +NETS 1 ; - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ; - - io_2 ( MACRO_1 O1 ) ( PIN io_2 ) + USE SIGNAL ; END NETS END DESIGN \ No newline at end of file From d8bd6b735f20766be564c5a99517c97fd4589b3e Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Mon, 28 Apr 2025 15:27:05 -0300 Subject: [PATCH 20/34] mpl: limit pin access blockages' depth Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 36 +- src/mpl/src/hier_rtlmp.h | 11 +- src/mpl/test/io_constraints7.defok | 802 ++++++++++++++--------------- 3 files changed, 440 insertions(+), 409 deletions(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 5b62d134a43..88dba71e31c 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -911,6 +911,8 @@ void HierRTLMP::createPinAccessBlockages() return; } + computePinAccessDepthLimits(); + if (!available_regions_for_pins_.empty()) { createBlockagesForAvailableRegions(); } else { @@ -918,6 +920,15 @@ void HierRTLMP::createPinAccessBlockages() } } +void HierRTLMP::computePinAccessDepthLimits() +{ + const Rect die = dbuToMicrons(block_->getDieArea()); + constexpr float max_depth_percentage = 0.20; + + pin_access_depth_limits_.horizontal = max_depth_percentage * die.getWidth(); + pin_access_depth_limits_.vertical = max_depth_percentage * die.getHeight(); +} + bool HierRTLMP::treeHasOnlyUnconstrainedIOs() { std::vector io_clusters = getClustersOfUnplacedIOPins(); @@ -1051,6 +1062,17 @@ void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, Rect blockage = micron_region; Boundary region_boundary = getRegionBoundary(micronsToDbu(micron_region)); + float blockage_depth; + if (isVertical(region_boundary)) { + blockage_depth = depth > pin_access_depth_limits_.horizontal + ? pin_access_depth_limits_.horizontal + : depth; + } else { + blockage_depth = depth > pin_access_depth_limits_.vertical + ? pin_access_depth_limits_.vertical + : depth; + } + debugPrint( logger_, MPL, @@ -1059,23 +1081,23 @@ void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, "Creating pin access blockage in {} -> Region shape = {} , Depth = {}", toString(region_boundary), micronsToDbu(micron_region), - depth); + blockage_depth); switch (region_boundary) { case L: { - blockage.setXMax(blockage.xMin() + depth); + blockage.setXMax(blockage.xMin() + blockage_depth); break; } case R: { - blockage.setXMin(blockage.xMax() - depth); + blockage.setXMin(blockage.xMax() - blockage_depth); break; } case B: { - blockage.setYMax(blockage.yMin() + depth); + blockage.setYMax(blockage.yMin() + blockage_depth); break; } case T: { - blockage.setYMin(blockage.yMax() - depth); + blockage.setYMin(blockage.yMax() - blockage_depth); break; } case NONE: { @@ -2946,7 +2968,7 @@ std::vector HierRTLMP::subtractOverlapRegion( odb::Rect a = base; odb::Rect b = base; - if (isHorizontal(base_boundary)) { + if (isVertical(base_boundary)) { a.set_yhi(overlay.yMin()); b.set_ylo(overlay.yMax()); } else { @@ -2965,7 +2987,7 @@ std::vector HierRTLMP::subtractOverlapRegion( return result; } -bool HierRTLMP::isHorizontal(Boundary boundary) +bool HierRTLMP::isVertical(Boundary boundary) { return boundary == L || boundary == R; } diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index 4b5518b478e..1f11da7f628 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -122,6 +122,12 @@ class HierRTLMP void writeMacroPlacement(const std::string& file_name); private: + struct PinAccessDepthLimits + { + float vertical{0.0f}; + float horizontal{0.0f}; + }; + using SoftSAVector = std::vector>; using HardSAVector = std::vector>; @@ -143,6 +149,7 @@ class HierRTLMP IntervalList computeWidthIntervals(const TilingList& tilings); void setTightPackingTilings(Cluster* macro_array); void createPinAccessBlockages(); + void computePinAccessDepthLimits(); bool treeHasOnlyUnconstrainedIOs(); std::vector getClustersOfUnplacedIOPins(); void createPinAccessBlockage(const Rect& micron_region, float depth); @@ -222,7 +229,7 @@ class HierRTLMP Rect dbuToMicrons(const odb::Rect& dbu_rect); odb::Rect getRect(Boundary boundary); - bool isHorizontal(Boundary boundary); + bool isVertical(Boundary boundary); std::vector subtractOverlapRegion(const odb::Rect& base, const odb::Rect& overlay); @@ -285,6 +292,8 @@ class HierRTLMP std::vector macro_blockages_; std::vector io_blockages_; + PinAccessDepthLimits pin_access_depth_limits_; + // Cache needed for orientation improvement. std::vector available_regions_for_pins_; diff --git a/src/mpl/test/io_constraints7.defok b/src/mpl/test/io_constraints7.defok index 50cd3a1e2b6..20b7f648129 100644 --- a/src/mpl/test/io_constraints7.defok +++ b/src/mpl/test/io_constraints7.defok @@ -114,407 +114,407 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 24670 ) N ; - - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _004_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _005_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _006_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _007_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _008_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _009_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _010_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _011_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _012_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _013_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _014_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _015_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _016_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _017_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _018_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _019_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _020_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _021_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _022_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _023_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _024_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _025_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _026_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _027_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _028_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _029_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _030_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _031_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _032_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _033_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _034_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _035_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _036_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _037_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _038_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _039_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _040_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _041_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _042_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _043_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _044_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _045_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _046_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _047_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _048_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _049_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _050_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _051_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _052_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _053_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _054_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _055_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _056_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _057_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _058_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _059_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _060_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _061_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _062_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _063_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _064_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _065_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _066_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _067_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _068_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _069_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _070_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _071_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _072_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _073_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _074_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _075_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _076_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _077_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _078_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _079_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _080_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _081_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _082_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _083_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _084_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _085_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _086_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _087_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _088_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _089_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _090_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _091_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _092_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _093_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _094_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _095_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _096_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _097_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _098_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _099_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _100_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _101_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _102_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _103_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _104_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _105_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _106_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _107_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _108_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _109_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _110_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _111_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _112_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _113_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _114_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _115_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _116_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _117_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _118_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _119_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _120_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _121_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _122_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _123_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _124_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _125_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _126_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _127_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _128_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _129_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _130_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _131_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _132_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _133_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _134_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _135_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _136_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _137_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _138_ DFF_X1 + PLACED ( 254680 123252 ) N ; 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- - _223_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _224_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _225_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _226_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _227_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _228_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _229_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _230_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _231_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _232_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _233_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _234_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _235_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _236_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _237_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _238_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _239_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _240_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _241_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _242_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _243_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _244_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _245_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _246_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _247_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _248_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _249_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _250_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _251_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _252_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _253_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _254_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _255_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _256_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _257_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _258_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _259_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _260_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _261_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _262_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _263_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _264_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _265_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _266_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _267_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _268_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _269_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _270_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _271_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _272_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _273_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _274_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _275_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _276_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _277_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _278_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _279_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _280_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _281_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _282_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _283_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _284_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _285_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _286_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _287_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _288_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _289_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _290_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _291_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _292_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _293_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _294_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _295_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _296_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _297_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _298_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _299_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _300_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _301_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _302_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _303_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _304_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _305_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _306_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _307_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _308_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _309_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _310_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _311_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _312_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _313_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _314_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _315_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _316_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _317_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _318_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _319_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _320_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _321_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _322_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _323_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _324_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _325_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _326_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _327_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _328_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _329_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _330_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _331_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _332_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _333_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _334_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _335_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _336_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _337_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _338_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _339_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _340_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _341_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _342_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _343_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _344_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _345_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _346_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _347_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _348_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _349_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _350_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _351_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _352_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _353_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _354_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _355_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _356_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _357_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _358_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _359_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _360_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _361_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _362_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _363_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _364_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _365_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _366_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _367_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _368_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _369_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _370_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _371_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _372_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _373_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _374_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _375_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _376_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _377_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _378_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _379_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _380_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _381_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _382_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _383_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _384_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _385_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _386_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _387_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _388_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _389_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _390_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _391_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _392_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _393_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _394_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _395_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _396_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _397_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _398_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _399_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _400_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8150 ) N ; + - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _004_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _005_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _006_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _007_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _008_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _009_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _010_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _011_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _012_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _013_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _014_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _015_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _016_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _017_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _018_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _019_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _020_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _021_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _022_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _023_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _024_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _025_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _026_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _027_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _028_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _029_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _030_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _031_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _032_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _033_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _034_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _035_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _036_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _037_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _038_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _039_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _040_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _041_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _042_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _043_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _044_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _045_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _046_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _047_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _048_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _049_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _050_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _051_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _052_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _053_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _054_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _055_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _056_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _057_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _058_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _059_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _060_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _061_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _062_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _063_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _064_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _065_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _066_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _067_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _068_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _069_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _070_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _071_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _072_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _073_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _074_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _075_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _076_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _077_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _078_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _079_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _080_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _081_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _082_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _083_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _084_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _085_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _086_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _087_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _088_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _089_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _090_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _091_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _092_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _093_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _094_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _095_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _096_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _097_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _098_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _099_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _100_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _101_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _102_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _103_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _104_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _105_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _106_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _107_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _108_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _109_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _110_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _111_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _112_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _113_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _114_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _115_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _116_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _117_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _118_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _119_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _120_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _121_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _122_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _123_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _124_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _125_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _126_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _127_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _128_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _129_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _130_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _131_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _132_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _133_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _134_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _135_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _136_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _137_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _138_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _139_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _140_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _141_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _142_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _143_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _144_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _145_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _146_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _147_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _148_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _149_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _150_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _151_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _152_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _153_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _154_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _155_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _156_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _157_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _158_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _159_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _160_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _161_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _162_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _163_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _164_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _165_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _166_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _167_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _168_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _169_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _170_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _171_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _172_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _173_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _174_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _175_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _176_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _177_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _178_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _179_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _180_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _181_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _182_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _183_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _184_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _185_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _186_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _187_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _188_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _189_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _190_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _191_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _192_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _193_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _194_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _195_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _196_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _197_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _198_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _199_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _200_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _201_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _202_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _203_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _204_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _205_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _206_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _207_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _208_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _209_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _210_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _211_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _212_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _213_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _214_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _215_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _216_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _217_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _218_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _219_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _220_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _221_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _222_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _223_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _224_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _225_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _226_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _227_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _228_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _229_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _230_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _231_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _232_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _233_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _234_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _235_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _236_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _237_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _238_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _239_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _240_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _241_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _242_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _243_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _244_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _245_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _246_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _247_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _248_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _249_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _250_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _251_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _252_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _253_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _254_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _255_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _256_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _257_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _258_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _259_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _260_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _261_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _262_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _263_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _264_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _265_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _266_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _267_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _268_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _269_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _270_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _271_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _272_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _273_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _274_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _275_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _276_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _277_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _278_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _279_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _280_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _281_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _282_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _283_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _284_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _285_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _286_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _287_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _288_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _289_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _290_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _291_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _292_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _293_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _294_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _295_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _296_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _297_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _298_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _299_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _300_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _301_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _302_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _303_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _304_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _305_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _306_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _307_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _308_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _309_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _310_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _311_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _312_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _313_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _314_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _315_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _316_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _317_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _318_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _319_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _320_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _321_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _322_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _323_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _324_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _325_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _326_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _327_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _328_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _329_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _330_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _331_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _332_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _333_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _334_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _335_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _336_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _337_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _338_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _339_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _340_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _341_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _342_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _343_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _344_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _345_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _346_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _347_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _348_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _349_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _350_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _351_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _352_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _353_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _354_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _355_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _356_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _357_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _358_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _359_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _360_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _361_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _362_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _363_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _364_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _365_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _366_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _367_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _368_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _369_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _370_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _371_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _372_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _373_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _374_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _375_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _376_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _377_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _378_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _379_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _380_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _381_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _382_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _383_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _384_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _385_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _386_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _387_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _388_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _389_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _390_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _391_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _392_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _393_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _394_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _395_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _396_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _397_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _398_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _399_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _400_ DFF_X1 + PLACED ( 38680 123252 ) N ; END COMPONENTS PINS 1 ; - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ; From 2da59d0175cf9eeae77413309c6bff37dd1c231e Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Mon, 28 Apr 2025 15:40:16 -0300 Subject: [PATCH 21/34] mpl: improve comment Signed-off-by: Arthur Koucher --- src/mpl/src/clusterEngine.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 1a753298f15..38e1eafe70c 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -259,7 +259,7 @@ class ClusteringEngine Metrics* design_metrics_{nullptr}; PhysicalHierarchy* tree_{nullptr}; - // Only for clusters of unplaced IOs. + // Cache the shapes/constraint regions in dbu to avoid comparison problems. std::map unplaced_ios_to_region_; int level_{0}; // Current level From e33ab339c71462a36ef0f27d18c046edace8fda3 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Mon, 28 Apr 2025 16:17:12 -0300 Subject: [PATCH 22/34] mpl: address clang-tidy Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 88dba71e31c..c8a02bf9ff8 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -1065,12 +1065,12 @@ void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, float blockage_depth; if (isVertical(region_boundary)) { blockage_depth = depth > pin_access_depth_limits_.horizontal - ? pin_access_depth_limits_.horizontal - : depth; + ? pin_access_depth_limits_.horizontal + : depth; } else { blockage_depth = depth > pin_access_depth_limits_.vertical - ? pin_access_depth_limits_.vertical - : depth; + ? pin_access_depth_limits_.vertical + : depth; } debugPrint( @@ -3049,11 +3049,10 @@ Pusher::Pusher(utl::Logger* logger, void Pusher::setIOBlockages(const std::vector& io_blockages) { for (const Rect& blockage : io_blockages) { - io_blockages_.emplace_back( - odb::Rect(block_->micronsToDbu(blockage.xMin()), - block_->micronsToDbu(blockage.yMin()), - block_->micronsToDbu(blockage.xMax()), - block_->micronsToDbu(blockage.yMax()))); + io_blockages_.emplace_back(block_->micronsToDbu(blockage.xMin()), + block_->micronsToDbu(blockage.yMin()), + block_->micronsToDbu(blockage.xMax()), + block_->micronsToDbu(blockage.yMax())); } } From 6ee3dd333cb633c83c4883c545c2a28aa10d4642 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Tue, 29 Apr 2025 12:07:54 -0300 Subject: [PATCH 23/34] mpl: 1) Fix association of unconstrained pins with their cluster; 2) Fix available regions' computation when there are no constraints at all. Signed-off-by: Arthur Koucher --- src/mpl/src/clusterEngine.cpp | 22 +- src/mpl/src/clusterEngine.h | 3 + src/mpl/src/hier_rtlmp.cpp | 59 ++-- src/mpl/src/hier_rtlmp.h | 9 +- src/mpl/src/object.cpp | 20 +- src/mpl/src/object.h | 8 +- src/mpl/test/CMakeLists.txt | 1 + src/mpl/test/io_constraints8.defok | 525 +++++++++++++++++++++++++++++ src/mpl/test/io_constraints8.ok | 21 ++ src/mpl/test/io_constraints8.tcl | 20 ++ 10 files changed, 635 insertions(+), 53 deletions(-) create mode 100644 src/mpl/test/io_constraints8.defok create mode 100644 src/mpl/test/io_constraints8.ok create mode 100644 src/mpl/test/io_constraints8.tcl diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 8f7107b4bbc..914d52a1147 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -377,8 +377,13 @@ void ClusteringEngine::createIOClusters() Cluster* ClusteringEngine::findIOClusterWithSameConstraint(odb::dbBTerm* bterm) { + const auto& bterm_constraint = bterm->getConstraintRegion(); + if (!bterm_constraint) { + return cluster_of_unconstrained_io_pins_; + } + for (const auto& [cluster, cluster_constraint] : unplaced_ios_to_region_) { - if (bterm->getConstraintRegion() == cluster_constraint) { + if (bterm_constraint == cluster_constraint) { return cluster; } } @@ -388,28 +393,29 @@ Cluster* ClusteringEngine::findIOClusterWithSameConstraint(odb::dbBTerm* bterm) void ClusteringEngine::createClusterOfUnplacedIOs(odb::dbBTerm* bterm) { - auto cluster = std::make_unique(id_, "", logger_); + auto cluster + = std::make_unique(id_, "ios_" + std::to_string(id_), logger_); cluster->setParent(tree_->root.get()); + bool is_cluster_of_unconstrained_io_pins = false; odb::Rect constraint_shape; const std::optional& bterm_constraint = bterm->getConstraintRegion(); if (bterm_constraint) { constraint_shape = *bterm_constraint; - cluster->setName("ios_" + std::to_string(id_)); + unplaced_ios_to_region_[cluster.get()] = constraint_shape; } else { constraint_shape = block_->getDieArea(); - cluster->setName("unconstrained_ios"); - cluster->setAsClusterOfUnconstrainedIOPins(); + is_cluster_of_unconstrained_io_pins = true; + cluster_of_unconstrained_io_pins_ = cluster.get(); } cluster->setAsClusterOfUnplacedIOPins( {block_->dbuToMicrons(constraint_shape.xMin()), block_->dbuToMicrons(constraint_shape.yMin())}, block_->dbuToMicrons(constraint_shape.dx()), - block_->dbuToMicrons(constraint_shape.dy())); - - unplaced_ios_to_region_[cluster.get()] = constraint_shape; + block_->dbuToMicrons(constraint_shape.dy()), + is_cluster_of_unconstrained_io_pins); tree_->maps.bterm_to_cluster_id[bterm] = id_; tree_->maps.id_to_cluster[id_++] = cluster.get(); diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 38e1eafe70c..f7c1f626811 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -262,6 +262,9 @@ class ClusteringEngine // Cache the shapes/constraint regions in dbu to avoid comparison problems. std::map unplaced_ios_to_region_; + // Keep this pointer to avoid searching for it when creating IO clusters. + Cluster* cluster_of_unconstrained_io_pins_{nullptr}; + int level_{0}; // Current level int id_{0}; // Current "highest" id diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index c8a02bf9ff8..e6071712dfb 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -317,6 +317,7 @@ void HierRTLMP::runCoarseShaping() calculateChildrenTilings(tree_->root.get()); + searchForAvailableRegionsForPins(); createPinAccessBlockages(); setPlacementBlockages(); } @@ -867,40 +868,46 @@ void HierRTLMP::setTightPackingTilings(Cluster* macro_array) macro_array->setTilings(tight_packing_tilings); } -void HierRTLMP::createPinAccessBlockages() +void HierRTLMP::searchForAvailableRegionsForPins() { - if (!tree_->maps.pad_to_bterm.empty()) { + if (!treeHasOnlyUnconstrainedIOs()) { return; } - if (treeHasOnlyUnconstrainedIOs()) { - const std::vector& blocked_regions_for_pins - = block_->getBlockedRegionsForPins(); + const std::vector& blocked_regions_for_pins + = block_->getBlockedRegionsForPins(); - if (blocked_regions_for_pins.empty()) { - // If there are no constraints at all, we give freedom to SA so it - // doesn't have to deal with pin access blockages across the entire - // extension of all edges of the die area. This should help SA not - // relying on extreme utilizations to converge for designs such as - // sky130hd/uW. - return; - } + BoundaryToRegionsMap boundary_to_blocked_regions + = getBoundaryToBlockedRegionsMap(blocked_regions_for_pins); + available_regions_for_pins_ + = computeAvailableRegions(boundary_to_blocked_regions); - BoundaryToRegionsMap boundary_to_blocked_regions - = getBoundaryToBlockedRegionsMap(blocked_regions_for_pins); - available_regions_for_pins_ - = computeAvailableRegions(boundary_to_blocked_regions); + if (graphics_) { + graphics_->setBlockedRegionsForPins(blocked_regions_for_pins); + graphics_->setAvailableRegionsForPins(available_regions_for_pins_); + } - if (graphics_) { - graphics_->setBlockedRegionsForPins(blocked_regions_for_pins); - graphics_->setAvailableRegionsForPins(available_regions_for_pins_); - } + for (const odb::Rect& dbu_available_region : available_regions_for_pins_) { + // Store regions in micron inside the tree to be used inside SA. + tree_->available_regions_for_pins.push_back( + dbuToMicrons(dbu_available_region)); + } +} - for (const odb::Rect& dbu_available_region : available_regions_for_pins_) { - // Store regions in micron inside the tree to be used inside SA. - tree_->available_regions_for_pins.push_back( - dbuToMicrons(dbu_available_region)); - } +void HierRTLMP::createPinAccessBlockages() +{ + if (!tree_->maps.pad_to_bterm.empty()) { + return; + } + + if (treeHasOnlyUnconstrainedIOs() + && block_->getBlockedRegionsForPins().empty()) { + // If there are no constraints at all, we give freedom to SA so it + // doesn't have to deal with pin access blockages across the entire + // extension of all edges of the die area. This should help SA not + // relying on extreme utilizations to converge for designs such as + // sky130hd/uW. + return; } const Metrics* top_module_metrics diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index 1f11da7f628..c53ef860f6d 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -148,16 +148,17 @@ class HierRTLMP void calculateMacroTilings(Cluster* cluster); IntervalList computeWidthIntervals(const TilingList& tilings); void setTightPackingTilings(Cluster* macro_array); + void searchForAvailableRegionsForPins(); + BoundaryToRegionsMap getBoundaryToBlockedRegionsMap( + const std::vector& blocked_regions_for_pins); + std::vector computeAvailableRegions( + BoundaryToRegionsMap& boundary_to_blocked_regions); void createPinAccessBlockages(); void computePinAccessDepthLimits(); bool treeHasOnlyUnconstrainedIOs(); std::vector getClustersOfUnplacedIOPins(); void createPinAccessBlockage(const Rect& micron_region, float depth); float computePinAccessBaseDepth(float io_span); - BoundaryToRegionsMap getBoundaryToBlockedRegionsMap( - const std::vector& blocked_regions_for_pins); - std::vector computeAvailableRegions( - BoundaryToRegionsMap& boundary_to_blocked_regions); void createBlockagesForAvailableRegions(); void createBlockagesForConstraintRegions(); Boundary getRegionBoundary(const odb::Rect& constraint_region); diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp index 8495603e194..b76330bbc46 100644 --- a/src/mpl/src/object.cpp +++ b/src/mpl/src/object.cpp @@ -233,8 +233,12 @@ std::string Cluster::getClusterTypeString() const { std::string cluster_type; + if (is_cluster_of_unconstrained_io_pins_) { + return "Unconstrained IOs"; + } + if (is_cluster_of_unplaced_io_pins_) { - return "Unplaced IO Pins"; + return "Unplaced IOs"; } if (is_io_pad_cluster_) { @@ -300,11 +304,14 @@ void Cluster::copyInstances(const Cluster& cluster) } } -void Cluster::setAsClusterOfUnplacedIOPins(const std::pair& pos, - const float width, - const float height) +void Cluster::setAsClusterOfUnplacedIOPins( + const std::pair& pos, + const float width, + const float height, + const bool is_cluster_of_unconstrained_io_pins) { is_cluster_of_unplaced_io_pins_ = true; + is_cluster_of_unconstrained_io_pins_ = is_cluster_of_unconstrained_io_pins; soft_macro_ = std::make_unique(pos, name_, width, height, this); } @@ -321,11 +328,6 @@ bool Cluster::isIOCluster() const return is_cluster_of_unplaced_io_pins_ || is_io_pad_cluster_; } -void Cluster::setAsClusterOfUnconstrainedIOPins() -{ - is_cluster_of_unconstrained_io_pins_ = true; -} - bool Cluster::isClusterOfUnconstrainedIOPins() const { return is_cluster_of_unconstrained_io_pins_; diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index 8bb8310d1a3..68c9c41feba 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -179,16 +179,12 @@ class Cluster void copyInstances(const Cluster& cluster); // only based on cluster type bool isIOCluster() const; - - // The cluster of unplaced IOs with unconstrained pins. - void setAsClusterOfUnconstrainedIOPins(); bool isClusterOfUnconstrainedIOPins() const; - bool isClusterOfUnplacedIOPins() const; void setAsClusterOfUnplacedIOPins(const std::pair& pos, float width, - float height); - + float height, + bool is_cluster_of_unconstrained_io_pins); bool isIOPadCluster() const { return is_io_pad_cluster_; } void setAsIOPadCluster(const std::pair& pos, float width, diff --git a/src/mpl/test/CMakeLists.txt b/src/mpl/test/CMakeLists.txt index c13ef809cd1..6c65e0dde4c 100644 --- a/src/mpl/test/CMakeLists.txt +++ b/src/mpl/test/CMakeLists.txt @@ -12,6 +12,7 @@ or_integration_tests( io_constraints5 io_constraints6 io_constraints7 + io_constraints8 io_pads1 orientation_improve1 orientation_improve2 diff --git a/src/mpl/test/io_constraints8.defok b/src/mpl/test/io_constraints8.defok new file mode 100644 index 00000000000..ecd8f4d73e8 --- /dev/null +++ b/src/mpl/test/io_constraints8.defok @@ -0,0 +1,525 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN io_constraints1 ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 300000 250000 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 0 0 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 0 2800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 0 5600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 0 8400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 0 11200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 0 14000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 0 16800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 0 19600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 0 22400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 0 25200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 0 28000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 0 30800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 0 33600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 0 36400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 0 39200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 0 42000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 0 44800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 0 47600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 0 50400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 0 53200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 0 56000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 0 58800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 0 61600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 0 64400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 0 67200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 0 70000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 0 72800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 0 75600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 0 78400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 0 81200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 0 84000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 0 86800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 0 89600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 0 92400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 0 95200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 0 98000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 0 100800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 0 103600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 0 106400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 0 109200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 0 112000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 0 114800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 0 117600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 0 120400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 0 123200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 0 126000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 0 128800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 0 131600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 0 134400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 0 137200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 0 140000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 0 142800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 0 145600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 0 148400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 0 151200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 0 154000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 0 156800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 0 159600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 0 162400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 0 165200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 0 168000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 0 170800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 0 173600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 0 176400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 0 179200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 0 182000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 0 184800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 0 187600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 0 190400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 0 193200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 0 196000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 0 198800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 0 201600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 0 204400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 0 207200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 0 210000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 0 212800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 0 215600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 0 218400 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 0 221200 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 0 224000 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 0 226800 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 0 229600 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 0 232400 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 0 235200 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_85 FreePDK45_38x28_10R_NP_162NW_34O 0 238000 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_86 FreePDK45_38x28_10R_NP_162NW_34O 0 240800 N DO 789 BY 1 STEP 380 0 ; +ROW ROW_87 FreePDK45_38x28_10R_NP_162NW_34O 0 243600 FS DO 789 BY 1 STEP 380 0 ; +ROW ROW_88 FreePDK45_38x28_10R_NP_162NW_34O 0 246400 N DO 789 BY 1 STEP 380 0 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 2368 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 3214 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 1607 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 1607 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 563 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 563 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; +COMPONENTS 401 ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8150 ) N ; + - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _004_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _005_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _006_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _007_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _008_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _009_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _010_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _011_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _012_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _013_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _014_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _015_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _016_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _017_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _018_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _019_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _020_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _021_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _022_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _023_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _024_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _025_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _026_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _027_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _028_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _029_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _030_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _031_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _032_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _033_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _034_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _035_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _036_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _037_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _038_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _039_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _040_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _041_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _042_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _043_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _044_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _045_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _046_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _047_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _048_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _049_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _050_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _051_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _052_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _053_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _054_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _055_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _056_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _057_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _058_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _059_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _060_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _061_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _062_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _063_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _064_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _065_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _066_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _067_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _068_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _069_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _070_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _071_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _072_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _073_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _074_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _075_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _076_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _077_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _078_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _079_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _080_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _081_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _082_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _083_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _084_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _085_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _086_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _087_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _088_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _089_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _090_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _091_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _092_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _093_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _094_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _095_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _096_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _097_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _098_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _099_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _100_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _101_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _102_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _103_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _104_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _105_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _106_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _107_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _108_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _109_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _110_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _111_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _112_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _113_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _114_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _115_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _116_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _117_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _118_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _119_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _120_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _121_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _122_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _123_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _124_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _125_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _126_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _127_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _128_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _129_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _130_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _131_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _132_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _133_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _134_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _135_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _136_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _137_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _138_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _139_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _140_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _141_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _142_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _143_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _144_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _145_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _146_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _147_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _148_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _149_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _150_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _151_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _152_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _153_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _154_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _155_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _156_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _157_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _158_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _159_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _160_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _161_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _162_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _163_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _164_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _165_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _166_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _167_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _168_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _169_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _170_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _171_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _172_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _173_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _174_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _175_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _176_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _177_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _178_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _179_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _180_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _181_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _182_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _183_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _184_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _185_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _186_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _187_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _188_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _189_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _190_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _191_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _192_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _193_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _194_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _195_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _196_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _197_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _198_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _199_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _200_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _201_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _202_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _203_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _204_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _205_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _206_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _207_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _208_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _209_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _210_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _211_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _212_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _213_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _214_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _215_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _216_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _217_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _218_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _219_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _220_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _221_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _222_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _223_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _224_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _225_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _226_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _227_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _228_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _229_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _230_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _231_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _232_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _233_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _234_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _235_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _236_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _237_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _238_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _239_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _240_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _241_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _242_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _243_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _244_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _245_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _246_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _247_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _248_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _249_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _250_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _251_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _252_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _253_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _254_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _255_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _256_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _257_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _258_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _259_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _260_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _261_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _262_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _263_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _264_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _265_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _266_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _267_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _268_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _269_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _270_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _271_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _272_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _273_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _274_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _275_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _276_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _277_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _278_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _279_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _280_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _281_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _282_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _283_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _284_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _285_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _286_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _287_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _288_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _289_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _290_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _291_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _292_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _293_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _294_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _295_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _296_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _297_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _298_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _299_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _300_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _301_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _302_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _303_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _304_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _305_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _306_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _307_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _308_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _309_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _310_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _311_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _312_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _313_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _314_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _315_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _316_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _317_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _318_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _319_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _320_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _321_ DFF_X1 + PLACED ( 254680 123252 ) N ; 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+ - _385_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _386_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _387_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _388_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _389_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _390_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _391_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _392_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _393_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _394_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _395_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _396_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _397_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _398_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _399_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - _400_ DFF_X1 + PLACED ( 254680 123252 ) N ; +END COMPONENTS +PINS 1 ; + - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ; +END PINS +NETS 1 ; + - io_1 ( PIN io_1 ) ( MACRO_1 I1 ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/mpl/test/io_constraints8.ok b/src/mpl/test/io_constraints8.ok new file mode 100644 index 00000000000..b84e5c61fe4 --- /dev/null +++ b/src/mpl/test/io_constraints8.ok @@ -0,0 +1,21 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: testcases/macro_only.lef, created 9 library cells +[INFO ODB-0128] Design: io_constraints1 +[INFO ODB-0130] Created 1 pins. +[INFO ODB-0131] Created 401 components and 2402 component-terminals. +[INFO ODB-0133] Created 1 nets and 1 connections. +Die Area: (0.00, 0.00) (150.00, 125.00), Floorplan Area: (0.00, 0.00) (149.91, 124.60) + Number of std cell instances: 400 + Area of std cell instances: 1808.79 + Number of macros: 1 + Area of macros: 10000.00 + Halo width: 4.00 + Halo height: 4.00 + Area of macros with halos: 11664.00 + Area of std cell instances + Area of macros: 11808.79 + Floorplan area: 18678.79 + Design Utilization: 0.63 + Floorplan Utilization: 0.21 + Manufacturing Grid: 10 + +No differences found. diff --git a/src/mpl/test/io_constraints8.tcl b/src/mpl/test/io_constraints8.tcl new file mode 100644 index 00000000000..65b50fb2549 --- /dev/null +++ b/src/mpl/test/io_constraints8.tcl @@ -0,0 +1,20 @@ +# Test if we available regions create based on the blocked regions for pins +# are correctly generated when there are no constraints at all. Connections +# are needed so we trigger the closest available region distance computation +# inside the annealer. +source "helpers.tcl" + +read_lef Nangate45/Nangate45.lef +read_lef testcases/macro_only.lef + +read_liberty Nangate45/Nangate45_fast.lib + +read_def testcases/io_constraints6.def + +set_thread_count 0 +rtl_macro_placer -report_directory results/io_constraints8 -halo_width 4.0 + +set def_file [make_result_file "io_constraints8.def"] +write_def $def_file +diff_files $def_file "io_constraints8.defok" + From 6c3494022f0df38b51e9881c50dbeeacecc55e8d Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Tue, 29 Apr 2025 14:27:15 -0300 Subject: [PATCH 24/34] mpl: 1) Mark methods as const; 2) Some minor performance improvements. Signed-off-by: Arthur Koucher --- src/mpl/src/clusterEngine.cpp | 9 +++------ src/mpl/src/clusterEngine.h | 2 +- src/mpl/src/hier_rtlmp.cpp | 20 ++++++++++---------- src/mpl/src/hier_rtlmp.h | 20 ++++++++++---------- 4 files changed, 24 insertions(+), 27 deletions(-) diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 914d52a1147..87ba5681d17 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -359,8 +359,7 @@ void ClusteringEngine::createIOClusters() return; } - odb::dbSet bterms = block_->getBTerms(); - if (bterms.empty()) { + if (block_->getBTerms().empty()) { logger_->warn(MPL, 26, "Design has no IO pins!"); tree_->has_io_clusters = false; } @@ -2183,16 +2182,14 @@ void ClusteringEngine::clearTempMacroClusterMapping( } } -int ClusteringEngine::getNumberOfIOs(Cluster* target) +int ClusteringEngine::getNumberOfIOs(Cluster* target) const { int number_of_ios = 0; - - for (const auto [pin, io_cluster_id] : tree_->maps.bterm_to_cluster_id) { + for (const auto& [pin, io_cluster_id] : tree_->maps.bterm_to_cluster_id) { if (io_cluster_id == target->getId()) { ++number_of_ios; } } - return number_of_ios; } diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index f7c1f626811..1ca6d7c17d3 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -152,7 +152,7 @@ class ClusteringEngine std::set& masters); void clearTempMacroClusterMapping(const UniqueClusterVector& macro_clusters); - int getNumberOfIOs(Cluster* target); + int getNumberOfIOs(Cluster* target) const; static bool isIgnoredInst(odb::dbInst* inst); diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index e6071712dfb..4b783a7e541 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -936,7 +936,7 @@ void HierRTLMP::computePinAccessDepthLimits() pin_access_depth_limits_.vertical = max_depth_percentage * die.getHeight(); } -bool HierRTLMP::treeHasOnlyUnconstrainedIOs() +bool HierRTLMP::treeHasOnlyUnconstrainedIOs() const { std::vector io_clusters = getClustersOfUnplacedIOPins(); for (Cluster* io_cluster : io_clusters) { @@ -997,7 +997,7 @@ void HierRTLMP::createBlockagesForConstraintRegions() } BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap( - const std::vector& blocked_regions_for_pins) + const std::vector& blocked_regions_for_pins) const { BoundaryToRegionsMap boundary_to_blocked_regions; std::queue blocked_regions; @@ -1024,7 +1024,7 @@ BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap( } std::vector HierRTLMP::computeAvailableRegions( - BoundaryToRegionsMap& boundary_to_blocked_regions) + BoundaryToRegionsMap& boundary_to_blocked_regions) const { std::vector available_regions; @@ -1119,7 +1119,7 @@ void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, io_blockages_.push_back(blockage); } -Boundary HierRTLMP::getRegionBoundary(const odb::Rect& constraint_region) +Boundary HierRTLMP::getRegionBoundary(const odb::Rect& constraint_region) const { const odb::Rect& die = block_->getDieArea(); Boundary constraint_boundary = NONE; @@ -1139,7 +1139,7 @@ Boundary HierRTLMP::getRegionBoundary(const odb::Rect& constraint_region) return constraint_boundary; } -std::vector HierRTLMP::getClustersOfUnplacedIOPins() +std::vector HierRTLMP::getClustersOfUnplacedIOPins() const { std::vector clusters_of_unplaced_io_pins; for (const auto& child : tree_->root->getChildren()) { @@ -1154,7 +1154,7 @@ std::vector HierRTLMP::getClustersOfUnplacedIOPins() // 1) Amount of std cell area in the design. // 2) Extension of IO span. // 3) Macro dominance quadratic factor. -float HierRTLMP::computePinAccessBaseDepth(const float io_span) +float HierRTLMP::computePinAccessBaseDepth(const float io_span) const { float std_cell_area = 0.0; for (auto& cluster : tree_->root->getChildren()) { @@ -2962,7 +2962,7 @@ Rect HierRTLMP::dbuToMicrons(const odb::Rect& dbu_rect) // | | std::vector HierRTLMP::subtractOverlapRegion( const odb::Rect& base, - const odb::Rect& overlay) + const odb::Rect& overlay) const { Boundary base_boundary = getRegionBoundary(base); @@ -2994,12 +2994,12 @@ std::vector HierRTLMP::subtractOverlapRegion( return result; } -bool HierRTLMP::isVertical(Boundary boundary) +bool HierRTLMP::isVertical(Boundary boundary) const { return boundary == L || boundary == R; } -odb::Rect HierRTLMP::getRect(Boundary boundary) +odb::Rect HierRTLMP::getRect(Boundary boundary) const { odb::Rect boundary_rect = block_->getDieArea(); @@ -3337,7 +3337,7 @@ bool Pusher::overlapsWithHardMacro( return false; } -bool Pusher::overlapsWithIOBlockage(const odb::Rect& cluster_box) +bool Pusher::overlapsWithIOBlockage(const odb::Rect& cluster_box) const { for (const odb::Rect& io_blockage : io_blockages_) { if (cluster_box.overlaps(io_blockage)) { diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index c53ef860f6d..df9fc9070eb 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -150,18 +150,18 @@ class HierRTLMP void setTightPackingTilings(Cluster* macro_array); void searchForAvailableRegionsForPins(); BoundaryToRegionsMap getBoundaryToBlockedRegionsMap( - const std::vector& blocked_regions_for_pins); + const std::vector& blocked_regions_for_pins) const; std::vector computeAvailableRegions( - BoundaryToRegionsMap& boundary_to_blocked_regions); + BoundaryToRegionsMap& boundary_to_blocked_regions) const; void createPinAccessBlockages(); void computePinAccessDepthLimits(); - bool treeHasOnlyUnconstrainedIOs(); - std::vector getClustersOfUnplacedIOPins(); + bool treeHasOnlyUnconstrainedIOs() const; + std::vector getClustersOfUnplacedIOPins() const; void createPinAccessBlockage(const Rect& micron_region, float depth); - float computePinAccessBaseDepth(float io_span); + float computePinAccessBaseDepth(float io_span) const; void createBlockagesForAvailableRegions(); void createBlockagesForConstraintRegions(); - Boundary getRegionBoundary(const odb::Rect& constraint_region); + Boundary getRegionBoundary(const odb::Rect& constraint_region) const; void setPlacementBlockages(); // Fine Shaping @@ -229,10 +229,10 @@ class HierRTLMP odb::Rect micronsToDbu(const Rect& micron_rect); Rect dbuToMicrons(const odb::Rect& dbu_rect); - odb::Rect getRect(Boundary boundary); - bool isVertical(Boundary boundary); + odb::Rect getRect(Boundary boundary) const; + bool isVertical(Boundary boundary) const; std::vector subtractOverlapRegion(const odb::Rect& base, - const odb::Rect& overlay); + const odb::Rect& overlay) const; // For debugging template @@ -347,7 +347,7 @@ class Pusher bool overlapsWithHardMacro( const odb::Rect& cluster_box, const std::vector& cluster_hard_macros); - bool overlapsWithIOBlockage(const odb::Rect& cluster_box); + bool overlapsWithIOBlockage(const odb::Rect& cluster_box) const; utl::Logger* logger_; From 6fd0ec56c47048a0766b830af84d610d62a8903f Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Tue, 29 Apr 2025 14:29:53 -0300 Subject: [PATCH 25/34] mpl: missing const Signed-off-by: Arthur Koucher --- src/mpl/src/clusterEngine.cpp | 3 ++- src/mpl/src/clusterEngine.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 87ba5681d17..584c2ffc39e 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -374,7 +374,8 @@ void ClusteringEngine::createIOClusters() } } -Cluster* ClusteringEngine::findIOClusterWithSameConstraint(odb::dbBTerm* bterm) +Cluster* ClusteringEngine::findIOClusterWithSameConstraint( + odb::dbBTerm* bterm) const { const auto& bterm_constraint = bterm->getConstraintRegion(); if (!bterm_constraint) { diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 1ca6d7c17d3..7dd6f442ee7 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -171,7 +171,7 @@ class ClusteringEngine void createRoot(); void setBaseThresholds(); void createIOClusters(); - Cluster* findIOClusterWithSameConstraint(odb::dbBTerm* bterm); + Cluster* findIOClusterWithSameConstraint(odb::dbBTerm* bterm) const; void createClusterOfUnplacedIOs(odb::dbBTerm* bterm); void createIOPadClusters(); void createIOPadCluster(odb::dbInst* pad, odb::dbBTerm* bterm); From f25b016be4872e4878e227e518f347aed6f7f9d3 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Mon, 5 May 2025 18:36:22 -0300 Subject: [PATCH 26/34] mpl: use the minimum distance to the nearest point of the available region when computing WL Signed-off-by: Arthur Koucher --- src/mpl/src/SACoreHardMacro.cpp | 6 +- src/mpl/src/SACoreHardMacro.h | 3 +- src/mpl/src/SACoreSoftMacro.cpp | 6 +- src/mpl/src/SACoreSoftMacro.h | 3 +- src/mpl/src/SimulatedAnnealingCore.cpp | 46 +- src/mpl/src/SimulatedAnnealingCore.h | 10 +- src/mpl/src/clusterEngine.h | 2 +- src/mpl/src/graphics.cpp | 13 +- src/mpl/src/graphics.h | 2 +- src/mpl/src/hier_rtlmp.cpp | 102 ++-- src/mpl/src/hier_rtlmp.h | 8 +- src/mpl/src/util.h | 120 +++- src/mpl/test/io_constraints6.defok | 2 +- src/mpl/test/io_constraints8.defok | 802 ++++++++++++------------- src/mpl/test/io_constraints8.tcl | 2 +- src/odb/include/odb/geom.h | 15 + 16 files changed, 621 insertions(+), 521 deletions(-) diff --git a/src/mpl/src/SACoreHardMacro.cpp b/src/mpl/src/SACoreHardMacro.cpp index a3166a8a07b..ddaa164ab50 100644 --- a/src/mpl/src/SACoreHardMacro.cpp +++ b/src/mpl/src/SACoreHardMacro.cpp @@ -31,8 +31,10 @@ SACoreHardMacro::SACoreHardMacro(PhysicalHierarchy* tree, int num_perturb_per_step, unsigned seed, MplObserver* graphics, - utl::Logger* logger) - : SimulatedAnnealingCore(tree, + utl::Logger* logger, + odb::dbBlock* block) + : SimulatedAnnealingCore(block, + tree, outline, macros, core_weights, diff --git a/src/mpl/src/SACoreHardMacro.h b/src/mpl/src/SACoreHardMacro.h index 632dae2d5c7..df34e1c4183 100644 --- a/src/mpl/src/SACoreHardMacro.h +++ b/src/mpl/src/SACoreHardMacro.h @@ -34,7 +34,8 @@ class SACoreHardMacro : public SimulatedAnnealingCore int num_perturb_per_step, unsigned seed, MplObserver* graphics, - utl::Logger* logger); + utl::Logger* logger, + odb::dbBlock* block); void run() override; diff --git a/src/mpl/src/SACoreSoftMacro.cpp b/src/mpl/src/SACoreSoftMacro.cpp index d174e607525..77fff8a750b 100644 --- a/src/mpl/src/SACoreSoftMacro.cpp +++ b/src/mpl/src/SACoreSoftMacro.cpp @@ -42,8 +42,10 @@ SACoreSoftMacro::SACoreSoftMacro(PhysicalHierarchy* tree, int num_perturb_per_step, unsigned seed, MplObserver* graphics, - utl::Logger* logger) - : SimulatedAnnealingCore(tree, + utl::Logger* logger, + odb::dbBlock* block) + : SimulatedAnnealingCore(block, + tree, outline, macros, core_weights, diff --git a/src/mpl/src/SACoreSoftMacro.h b/src/mpl/src/SACoreSoftMacro.h index b8d8c4f26fa..8e4fef39701 100644 --- a/src/mpl/src/SACoreSoftMacro.h +++ b/src/mpl/src/SACoreSoftMacro.h @@ -42,7 +42,8 @@ class SACoreSoftMacro : public SimulatedAnnealingCore int num_perturb_per_step, unsigned seed, MplObserver* graphics, - utl::Logger* logger); + utl::Logger* logger, + odb::dbBlock* block); void run() override; diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 1fb61e1d36b..81f939bc9ab 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -22,7 +22,8 @@ namespace mpl { using std::string; template -SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, +SimulatedAnnealingCore::SimulatedAnnealingCore(odb::dbBlock* block, + PhysicalHierarchy* tree, const Rect& outline, const std::vector& macros, const SACoreWeights& weights, @@ -37,7 +38,7 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, unsigned seed, MplObserver* graphics, utl::Logger* logger) - : outline_(outline), graphics_(graphics) + : block_(block), outline_(outline), graphics_(graphics) { core_weights_ = weights; @@ -73,13 +74,18 @@ void SimulatedAnnealingCore::setDieArea(const Rect& die_area) template void SimulatedAnnealingCore::setAvailableRegionForPins( - const std::vector& regions) + const std::vector& regions) { - for (const Rect& region : regions) { - Rect offset_region = region; - offset_region.moveHor(-outline_.xMin()); - offset_region.moveVer(-outline_.yMin()); - available_regions_for_pins_.push_back(offset_region); + const float x_offset = -(block_->micronsToDbu(outline_.xMin())); + const float y_offset = -(block_->micronsToDbu(outline_.xMin())); + + available_regions_for_pins_.reserve(regions.size()); + for (const odb::Rect& region : regions) { + odb::Line region_line = rectToLine(block_, region, logger_); + region_line.addX(x_offset); + region_line.addX(y_offset); + available_regions_for_pins_.emplace_back(region_line, + getBoundary(block_, region)); } } @@ -317,17 +323,12 @@ void SimulatedAnnealingCore::addClosestAvailableRegionDistToWL( "There's no available region for the unconstrained pins!"); } - float dist_to_closest_available_region = std::numeric_limits::max(); - for (const Rect& region : available_regions_for_pins_) { - const float dist_to_available_region - = computeDistance(/* from */ {macro.getPinX(), macro.getPinY()}, - /* to */ {region.xCenter(), region.yCenter()}); - if (dist_to_available_region < dist_to_closest_available_region) { - dist_to_closest_available_region = dist_to_available_region; - } - } + const odb::Point macro_location(block_->micronsToDbu(macro.getPinX()), + block_->micronsToDbu(macro.getPinY())); + const double nearest_distance = computeDistToNearestRegion( + macro_location, available_regions_for_pins_, nullptr); - wirelength_ += net_weight * dist_to_closest_available_region; + wirelength_ += net_weight * block_->dbuToMicrons(nearest_distance); } // We consider the macro outside the outline based on the location of @@ -339,15 +340,6 @@ bool SimulatedAnnealingCore::isOutsideTheOutline(const T& macro) const || macro.getPinY() > outline_.getHeight(); } -template -float SimulatedAnnealingCore::computeDistance(const Point& a, - const Point& b) const -{ - const float dx = std::abs(a.first - b.first); - const float dy = std::abs(a.second - b.second); - return std::sqrt(std::pow(dx, 2) + std::pow(dy, 2)); -} - template void SimulatedAnnealingCore::calFencePenalty() { diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 6a50ad4d633..3e0496fe556 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -38,7 +38,8 @@ template class SimulatedAnnealingCore { public: - SimulatedAnnealingCore(PhysicalHierarchy* tree, + SimulatedAnnealingCore(odb::dbBlock* block, + PhysicalHierarchy* tree, const Rect& outline, const std::vector& macros, const SACoreWeights& weights, @@ -97,7 +98,7 @@ class SimulatedAnnealingCore void fastSA(); - void setAvailableRegionForPins(const std::vector& regions); + void setAvailableRegionForPins(const std::vector& regions); void initSequencePair(); void setDieArea(const Rect& die_area); void updateBestValidResult(); @@ -109,7 +110,6 @@ class SimulatedAnnealingCore void calWirelength(); void addClosestAvailableRegionDistToWL(const T& macro, float net_weight); bool isOutsideTheOutline(const T& macro) const; - float computeDistance(const Point& a, const Point& b) const; void calGuidancePenalty(); void calFencePenalty(); @@ -132,10 +132,12 @@ class SimulatedAnnealingCore void reportLocations() const; void report(const PenaltyData& penalty) const; + odb::dbBlock* block_; + Rect outline_; Rect die_area_; // Offset to the current outline. - std::vector available_regions_for_pins_; + std::vector available_regions_for_pins_; // Number of macros that will actually be part of the sequence pair int macros_to_place_ = 0; diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 7dd6f442ee7..dfa6f3fb3b4 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -88,7 +88,7 @@ struct PhysicalHierarchy std::unique_ptr root; PhysicalHierarchyMaps maps; - std::vector available_regions_for_pins; + std::vector available_regions_for_pins; float halo_width{0.0f}; float halo_height{0.0f}; diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp index d5ff80eef90..52b95468666 100644 --- a/src/mpl/src/graphics.cpp +++ b/src/mpl/src/graphics.cpp @@ -591,12 +591,8 @@ void Graphics::drawDistToClosestAvailableRegion(gui::Painter& painter, from.addX(outline_.xMin()); from.addY(outline_.yMin()); - // Differently from what happens inside the SA core - where all - // computations are made using the origin of the current outline as - // reference - here we search for the center of the closest region - // using the die area origin as reference. I.e., we offset the macro - // location instead of offsetting the regions as we do inside SA. - odb::Point to = findCenterOfClosestRegion(from, available_regions_for_pins_); + odb::Point to; + computeDistToNearestRegion(from, available_regions_for_pins_, &to); painter.drawLine(from, to); painter.drawString( @@ -715,7 +711,10 @@ void Graphics::setBlockedRegionsForPins( void Graphics::setAvailableRegionsForPins( const std::vector& available_regions_for_pins) { - available_regions_for_pins_ = available_regions_for_pins; + for (const odb::Rect& region : available_regions_for_pins) { + available_regions_for_pins_.emplace_back( + rectToLine(block_, region, logger_), getBoundary(block_, region)); + } } void Graphics::eraseDrawing() diff --git a/src/mpl/src/graphics.h b/src/mpl/src/graphics.h index 23f3d423394..31e8de158e6 100644 --- a/src/mpl/src/graphics.h +++ b/src/mpl/src/graphics.h @@ -109,7 +109,7 @@ class Graphics : public gui::Renderer, public MplObserver int target_cluster_id_{-1}; std::vector> outlines_; std::vector blocked_regions_for_pins_; - std::vector available_regions_for_pins_; + std::vector available_regions_for_pins_; // In Soft SA, we're shaping/placing the children of a certain parent, // so for this case, the current cluster is actually the current parent. diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 4b783a7e541..1e89a8dfd19 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -482,7 +482,8 @@ void HierRTLMP::calculateChildrenTilings(Cluster* parent) num_perturb_per_step, random_seed_, graphics_.get(), - logger_); + logger_, + block_); sa_batch.push_back(std::move(sa)); } if (sa_batch.size() == 1) { @@ -541,7 +542,8 @@ void HierRTLMP::calculateChildrenTilings(Cluster* parent) num_perturb_per_step, random_seed_, graphics_.get(), - logger_); + logger_, + block_); sa_batch.push_back(std::move(sa)); } if (sa_batch.size() == 1) { @@ -721,7 +723,8 @@ void HierRTLMP::calculateMacroTilings(Cluster* cluster) num_perturb_per_step, random_seed_ + run_id, graphics_.get(), - logger_); + logger_, + block_); sa_batch.push_back(std::move(sa)); } if (sa_batch.size() == 1) { @@ -775,7 +778,8 @@ void HierRTLMP::calculateMacroTilings(Cluster* cluster) num_perturb_per_step, random_seed_ + run_id, graphics_.get(), - logger_); + logger_, + block_); sa_batch.push_back(std::move(sa)); } if (sa_batch.size() == 1) { @@ -879,18 +883,18 @@ void HierRTLMP::searchForAvailableRegionsForPins() BoundaryToRegionsMap boundary_to_blocked_regions = getBoundaryToBlockedRegionsMap(blocked_regions_for_pins); - available_regions_for_pins_ + tree_->available_regions_for_pins = computeAvailableRegions(boundary_to_blocked_regions); - if (graphics_) { - graphics_->setBlockedRegionsForPins(blocked_regions_for_pins); - graphics_->setAvailableRegionsForPins(available_regions_for_pins_); + available_regions_for_pins_.reserve(tree_->available_regions_for_pins.size()); + for (const odb::Rect& region : tree_->available_regions_for_pins) { + available_regions_for_pins_.emplace_back( + rectToLine(block_, region, logger_), getBoundary(block_, region)); } - for (const odb::Rect& dbu_available_region : available_regions_for_pins_) { - // Store regions in micron inside the tree to be used inside SA. - tree_->available_regions_for_pins.push_back( - dbuToMicrons(dbu_available_region)); + if (graphics_) { + graphics_->setBlockedRegionsForPins(blocked_regions_for_pins); + graphics_->setAvailableRegionsForPins(tree_->available_regions_for_pins); } } @@ -920,7 +924,7 @@ void HierRTLMP::createPinAccessBlockages() computePinAccessDepthLimits(); - if (!available_regions_for_pins_.empty()) { + if (!tree_->available_regions_for_pins.empty()) { createBlockagesForAvailableRegions(); } else { createBlockagesForConstraintRegions(); @@ -949,15 +953,15 @@ bool HierRTLMP::treeHasOnlyUnconstrainedIOs() const void HierRTLMP::createBlockagesForAvailableRegions() { - float io_span = 0.0f; - for (const Rect& available_region : tree_->available_regions_for_pins) { - io_span += available_region.getPerimeter() / 2; + int64_t io_span = 0; + for (const odb::Rect& region : tree_->available_regions_for_pins) { + io_span += region.margin() / 2; } - const float depth = computePinAccessBaseDepth(io_span); + const float depth = computePinAccessBaseDepth(block_->dbuToMicrons(io_span)); - for (const Rect& available_region : tree_->available_regions_for_pins) { - createPinAccessBlockage(available_region, depth); + for (const odb::Rect& region : tree_->available_regions_for_pins) { + createPinAccessBlockage(region, depth); } } @@ -992,7 +996,9 @@ void HierRTLMP::createBlockagesForConstraintRegions() const float io_density_factor = cluster_number_of_ios / total_ios; const float depth = base_depth * io_density_factor; - createPinAccessBlockage(cluster_of_unplaced_ios->getBBox(), depth); + odb::Rect blockage_region + = micronsToDbu(cluster_of_unplaced_ios->getBBox()); + createPinAccessBlockage(blockage_region, depth); } } @@ -1008,7 +1014,7 @@ BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap( boundary_to_blocked_regions[T] = blocked_regions; for (const odb::Rect& blocked_region : blocked_regions_for_pins) { - Boundary boundary = getRegionBoundary(blocked_region); + Boundary boundary = getBoundary(block_, blocked_region); boundary_to_blocked_regions.at(boundary).push(blocked_region); debugPrint(logger_, @@ -1063,11 +1069,10 @@ std::vector HierRTLMP::computeAvailableRegions( return available_regions; } -void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, +void HierRTLMP::createPinAccessBlockage(const odb::Rect& region, const float depth) { - Rect blockage = micron_region; - Boundary region_boundary = getRegionBoundary(micronsToDbu(micron_region)); + Boundary region_boundary = getBoundary(block_, region); float blockage_depth; if (isVertical(region_boundary)) { @@ -1087,9 +1092,10 @@ void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, 1, "Creating pin access blockage in {} -> Region shape = {} , Depth = {}", toString(region_boundary), - micronsToDbu(micron_region), + region, blockage_depth); + Rect blockage = dbuToMicrons(region); switch (region_boundary) { case L: { blockage.setXMax(blockage.xMin() + blockage_depth); @@ -1119,26 +1125,6 @@ void HierRTLMP::createPinAccessBlockage(const Rect& micron_region, io_blockages_.push_back(blockage); } -Boundary HierRTLMP::getRegionBoundary(const odb::Rect& constraint_region) const -{ - const odb::Rect& die = block_->getDieArea(); - Boundary constraint_boundary = NONE; - if (constraint_region.dx() == 0) { - if (constraint_region.xMin() == die.xMin()) { - constraint_boundary = L; - } else { - constraint_boundary = R; - } - } else { - if (constraint_region.yMin() == die.yMin()) { - constraint_boundary = B; - } else { - constraint_boundary = T; - } - } - return constraint_boundary; -} - std::vector HierRTLMP::getClustersOfUnplacedIOPins() const { std::vector clusters_of_unplaced_io_pins; @@ -1154,7 +1140,7 @@ std::vector HierRTLMP::getClustersOfUnplacedIOPins() const // 1) Amount of std cell area in the design. // 2) Extension of IO span. // 3) Macro dominance quadratic factor. -float HierRTLMP::computePinAccessBaseDepth(const float io_span) const +float HierRTLMP::computePinAccessBaseDepth(const double io_span) const { float std_cell_area = 0.0; for (auto& cluster : tree_->root->getChildren()) { @@ -1556,7 +1542,8 @@ void HierRTLMP::placeChildren(Cluster* parent) num_perturb_per_step, random_seed_, graphics_.get(), - logger_); + logger_, + block_); sa->setNumberOfMacrosToPlace(num_of_macros_to_place); sa->setCentralizationAttemptOn(true); sa->setFences(fences); @@ -1945,7 +1932,8 @@ void HierRTLMP::placeChildrenUsingMinimumTargetUtil(Cluster* parent) num_perturb_per_step, random_seed_, graphics_.get(), - logger_); + logger_, + block_); sa->setNumberOfMacrosToPlace(macros_to_place); sa->setCentralizationAttemptOn(true); sa->setFences(fences); @@ -2462,7 +2450,8 @@ void HierRTLMP::placeMacros(Cluster* cluster) num_perturb_per_step, random_seed_ + run_id, graphics_.get(), - logger_); + logger_, + block_); sa->setNumberOfMacrosToPlace(macros_to_place); sa->setNets(nets); sa->setFences(fences); @@ -2762,11 +2751,12 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro) odb::Rect region_rect(x, y, x, y); net_box.merge(region_rect); } else { - odb::Point closest_available_region_center - = findCenterOfClosestRegion(macro_pin->getBBox().center(), - available_regions_for_pins_); - odb::Rect center_rect(closest_available_region_center, - closest_available_region_center); + odb::Point nearest_region_point; + computeDistToNearestRegion(macro->getBBox()->getBox().center(), + available_regions_for_pins_, + &nearest_region_point); + + odb::Rect center_rect(nearest_region_point, nearest_region_point); net_box.merge(center_rect); } } @@ -2964,9 +2954,9 @@ std::vector HierRTLMP::subtractOverlapRegion( const odb::Rect& base, const odb::Rect& overlay) const { - Boundary base_boundary = getRegionBoundary(base); + Boundary base_boundary = getBoundary(block_, base); - if (base_boundary != getRegionBoundary(overlay)) { + if (base_boundary != getBoundary(block_, overlay)) { logger_->critical( MPL, 46, "Attempting to subtract regions from different boundaries."); } diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index df9fc9070eb..c8ad3c7b05b 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -157,11 +157,10 @@ class HierRTLMP void computePinAccessDepthLimits(); bool treeHasOnlyUnconstrainedIOs() const; std::vector getClustersOfUnplacedIOPins() const; - void createPinAccessBlockage(const Rect& micron_region, float depth); - float computePinAccessBaseDepth(float io_span) const; + void createPinAccessBlockage(const odb::Rect& region, float depth); + float computePinAccessBaseDepth(double io_span) const; void createBlockagesForAvailableRegions(); void createBlockagesForConstraintRegions(); - Boundary getRegionBoundary(const odb::Rect& constraint_region) const; void setPlacementBlockages(); // Fine Shaping @@ -231,6 +230,7 @@ class HierRTLMP odb::Rect getRect(Boundary boundary) const; bool isVertical(Boundary boundary) const; + std::vector subtractOverlapRegion(const odb::Rect& base, const odb::Rect& overlay) const; @@ -296,7 +296,7 @@ class HierRTLMP PinAccessDepthLimits pin_access_depth_limits_; // Cache needed for orientation improvement. - std::vector available_regions_for_pins_; + std::vector available_regions_for_pins_; // Fast SA hyperparameter float init_prob_ = 0.9; diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index 8e1ff7438de..04592000c1e 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -36,6 +36,18 @@ struct PenaltyData float normalization_factor{0.0f}; }; +// Used inside the annealer and during the orientation improvement step. +struct AvailableRegionForPins +{ + AvailableRegionForPins(const odb::Line& line, const Boundary boundary) + : line(line), boundary(boundary) + { + } + + odb::Line line; + Boundary boundary; +}; + // Utility to help sorting width intervals. inline bool isMinWidthSmaller(const Interval& width_interval_a, const Interval& width_interval_b) @@ -53,21 +65,105 @@ inline bool isAreaSmaller(const Tiling& tiling_a, const Tiling& tiling_b) return tiling_a.width() < tiling_b.width(); } -inline odb::Point findCenterOfClosestRegion( - const odb::Point& from, - const std::vector& regions) +inline Boundary getBoundary(odb::dbBlock* block, const odb::Rect& region) +{ + const odb::Rect& die = block->getDieArea(); + Boundary boundary = NONE; + if (region.dx() == 0) { + if (region.xMin() == die.xMin()) { + boundary = L; + } else { + boundary = R; + } + } else { + if (region.yMin() == die.yMin()) { + boundary = B; + } else { + boundary = T; + } + } + return boundary; +} + +inline odb::Line rectToLine(odb::dbBlock* block, + const odb::Rect& rect, + utl::Logger* logger) +{ + if (rect.dx() != 0 && rect.dy() != 0) { + logger->error(utl::MPL, + 60, + "Coundn't convert rect {} to line. The region is not a line.", + rect); + } + + odb::Line line; + switch (getBoundary(block, rect)) { + case L: + return line = {rect.ll(), rect.ul()}; + case R: + return line = {rect.lr(), rect.ur()}; + case T: + return line = {rect.ul(), rect.ur()}; + case B: + return line = {rect.ll(), rect.lr()}; + case NONE: + logger->error(utl::MPL, + 61, + "Couldn't convert rect {} to line. The is region outside " + "of the die {} boundaries.", + rect, + block->getDieArea()); + } + + return line; +} + +inline odb::Point computeNearestPointInRegion( + const AvailableRegionForPins& region, + const odb::Point& target) +{ + if (region.boundary == L || region.boundary == R) { + if (target.y() >= region.line.pt1().y()) { + return odb::Point(region.line.pt0().x(), region.line.pt1().y()); + } + if (target.y() <= region.line.pt0().y()) { + return odb::Point(region.line.pt0().x(), region.line.pt0().y()); + } + return odb::Point(region.line.pt0().x(), target.y()); + } + + // Top or Bottom + if (target.x() >= region.line.pt1().x()) { + return odb::Point(region.line.pt1().x(), region.line.pt0().y()); + } + if (target.x() <= region.line.pt0().x()) { + return odb::Point(region.line.pt0().x(), region.line.pt0().y()); + } + return odb::Point(target.x(), region.line.pt0().y()); +} + +// The distance in DBU from the macro bundled pin to the nearest point +// of the nearest region. +inline double computeDistToNearestRegion( + const odb::Point& macro_location, + const std::vector& regions, + odb::Point* closest_point) { - odb::Point to; - double dist_to_closest_region = std::numeric_limits::max(); - for (const odb::Rect& region : regions) { - const double dist_to_region - = std::sqrt(odb::Point::squaredDistance(from, region.center())); - if (dist_to_region < dist_to_closest_region) { - dist_to_closest_region = dist_to_region; - to = region.center(); + double smallest_distance = std::numeric_limits::max(); + for (const AvailableRegionForPins& region : regions) { + odb::Point closest_point_in_region + = computeNearestPointInRegion(region, macro_location); + const double dist_to_closest_point_in_region = std::sqrt( + odb::Point::squaredDistance(macro_location, closest_point_in_region)); + if (dist_to_closest_point_in_region < smallest_distance) { + smallest_distance = dist_to_closest_point_in_region; + if (closest_point) { + *closest_point = closest_point_in_region; + } } } - return to; + + return smallest_distance; } } // namespace mpl diff --git a/src/mpl/test/io_constraints6.defok b/src/mpl/test/io_constraints6.defok index 8652f21d6b8..ecd8f4d73e8 100644 --- a/src/mpl/test/io_constraints6.defok +++ b/src/mpl/test/io_constraints6.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8010 ) S ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8150 ) N ; - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ; - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ; - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ; diff --git a/src/mpl/test/io_constraints8.defok b/src/mpl/test/io_constraints8.defok index ecd8f4d73e8..460e1eafdcd 100644 --- a/src/mpl/test/io_constraints8.defok +++ b/src/mpl/test/io_constraints8.defok @@ -114,407 +114,407 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8150 ) N ; - - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _004_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _005_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _006_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _007_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _008_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _009_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _010_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _011_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _012_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _013_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _014_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _015_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _016_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _017_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _018_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _019_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _020_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _021_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _022_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _023_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _024_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _025_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _026_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _027_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _028_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _029_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _030_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _031_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _032_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _033_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _034_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _035_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _036_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _037_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _038_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _039_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _040_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _041_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _042_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _043_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _044_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _045_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _046_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _047_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _048_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _049_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _050_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _051_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _052_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _053_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _054_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _055_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _056_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _057_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _058_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _059_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _060_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _061_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _062_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _063_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _064_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _065_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _066_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _067_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _068_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _069_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _070_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _071_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _072_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _073_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _074_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _075_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _076_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _077_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _078_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _079_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _080_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _081_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _082_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _083_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _084_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _085_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _086_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _087_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _088_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _089_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _090_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _091_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _092_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _093_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _094_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _095_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _096_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _097_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _098_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _099_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _100_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _101_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _102_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _103_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _104_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _105_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _106_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _107_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _108_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _109_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _110_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _111_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _112_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _113_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _114_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _115_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _116_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _117_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _118_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _119_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _120_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _121_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _122_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _123_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _124_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _125_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _126_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _127_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _128_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _129_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _130_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _131_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _132_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _133_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _134_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _135_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _136_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _137_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _138_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _139_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _140_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _141_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _142_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _143_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _144_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _145_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _146_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _147_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _148_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _149_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _150_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _151_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _152_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _153_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _154_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _155_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _156_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _157_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _158_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _159_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _160_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _161_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _162_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _163_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _164_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _165_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _166_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _167_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _168_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _169_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _170_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _171_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _172_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _173_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _174_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _175_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _176_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _177_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _178_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _179_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _180_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _181_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _182_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _183_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _184_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _185_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _186_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _187_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _188_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _189_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _190_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _191_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _192_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _193_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _194_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _195_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _196_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _197_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _198_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _199_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _200_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _201_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _202_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _203_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _204_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _205_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _206_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _207_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _208_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _209_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _210_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _211_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _212_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _213_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _214_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _215_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _216_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _217_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _218_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _219_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _220_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _221_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _222_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _223_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _224_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _225_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _226_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _227_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _228_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _229_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _230_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _231_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _232_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _233_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _234_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _235_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _236_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _237_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _238_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _239_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _240_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _241_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _242_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _243_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _244_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _245_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _246_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _247_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _248_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _249_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _250_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _251_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _252_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _253_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _254_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _255_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _256_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _257_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _258_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _259_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _260_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _261_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _262_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _263_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _264_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _265_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _266_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _267_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _268_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _269_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _270_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _271_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _272_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _273_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _274_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _275_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _276_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _277_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _278_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _279_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _280_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _281_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _282_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _283_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _284_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _285_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _286_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _287_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _288_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _289_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _290_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _291_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _292_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _293_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _294_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _295_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _296_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _297_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _298_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _299_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _300_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _301_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _302_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _303_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _304_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _305_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _306_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _307_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _308_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _309_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _310_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _311_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _312_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _313_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _314_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _315_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _316_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _317_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _318_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _319_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _320_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _321_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _322_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _323_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _324_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _325_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _326_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _327_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _328_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _329_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _330_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _331_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _332_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _333_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _334_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _335_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _336_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _337_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _338_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _339_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _340_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _341_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _342_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _343_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _344_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _345_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _346_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _347_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _348_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _349_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _350_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _351_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _352_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _353_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _354_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _355_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _356_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _357_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _358_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _359_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _360_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _361_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _362_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _363_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _364_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _365_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _366_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _367_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _368_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _369_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _370_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _371_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _372_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _373_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _374_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _375_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _376_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _377_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _378_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _379_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _380_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _381_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _382_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _383_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _384_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _385_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _386_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _387_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _388_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _389_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _390_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _391_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _392_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _393_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _394_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _395_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _396_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _397_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _398_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _399_ DFF_X1 + PLACED ( 254680 123252 ) N ; - - _400_ DFF_X1 + PLACED ( 254680 123252 ) N ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8010 ) FS ; + - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _004_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _005_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _006_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _007_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _008_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _009_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _010_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _011_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _012_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _013_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _014_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _015_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _016_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _017_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _018_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _019_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _020_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _021_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _022_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _023_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _024_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _025_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _026_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _027_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _028_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _029_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _030_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _031_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _032_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _033_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _034_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _035_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _036_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _037_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _038_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _039_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _040_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _041_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _042_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _043_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _044_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _045_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _046_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _047_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _048_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _049_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _050_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _051_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _052_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _053_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _054_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _055_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _056_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _057_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _058_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _059_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _060_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _061_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _062_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _063_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _064_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _065_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _066_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _067_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _068_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _069_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _070_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _071_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _072_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _073_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _074_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _075_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _076_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _077_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _078_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _079_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _080_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _081_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _082_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _083_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _084_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _085_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _086_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _087_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _088_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _089_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _090_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _091_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _092_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _093_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _094_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _095_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _096_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _097_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _098_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _099_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _100_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _101_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _102_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _103_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _104_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _105_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _106_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _107_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _108_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _109_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _110_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _111_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _112_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _113_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _114_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _115_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _116_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _117_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _118_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _119_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _120_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _121_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _122_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _123_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _124_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _125_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _126_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _127_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _128_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _129_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _130_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _131_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _132_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _133_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _134_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _135_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _136_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _137_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _138_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _139_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _140_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _141_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _142_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _143_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _144_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _145_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _146_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _147_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _148_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _149_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _150_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _151_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _152_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _153_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _154_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _155_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _156_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _157_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _158_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _159_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _160_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _161_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _162_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _163_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _164_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _165_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _166_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _167_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _168_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _169_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _170_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _171_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _172_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _173_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _174_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _175_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _176_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _177_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _178_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _179_ DFF_X1 + PLACED ( 38680 123252 ) N ; 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+ - _202_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _203_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _204_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _205_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _206_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _207_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _208_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _209_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _210_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _211_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _212_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _213_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _214_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _215_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _216_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _217_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _218_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _219_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _220_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _221_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _222_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _223_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _224_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _225_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _226_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _227_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _228_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _229_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _230_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _231_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _232_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _233_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _234_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _235_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _236_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _237_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _238_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _239_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _240_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _241_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _242_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _243_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _244_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _245_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _246_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _247_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _248_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _249_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _250_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _251_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _252_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _253_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _254_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _255_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _256_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _257_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _258_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _259_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _260_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _261_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _262_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _263_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _264_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _265_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _266_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _267_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _268_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _269_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _270_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _271_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _272_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _273_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _274_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _275_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _276_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _277_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _278_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _279_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _280_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _281_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _282_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _283_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _284_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _285_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _286_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _287_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _288_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _289_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _290_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _291_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _292_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _293_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _294_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _295_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _296_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _297_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _298_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _299_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _300_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _301_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _302_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _303_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _304_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _305_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _306_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _307_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _308_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _309_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _310_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _311_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _312_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _313_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _314_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _315_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _316_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _317_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _318_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _319_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _320_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _321_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _322_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _323_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _324_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _325_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _326_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _327_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _328_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _329_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _330_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _331_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _332_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _333_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _334_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _335_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _336_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _337_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _338_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _339_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _340_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _341_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _342_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _343_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _344_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _345_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _346_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _347_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _348_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _349_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _350_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _351_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _352_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _353_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _354_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _355_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _356_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _357_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _358_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _359_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _360_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _361_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _362_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _363_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _364_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _365_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _366_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _367_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _368_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _369_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _370_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _371_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _372_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _373_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _374_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _375_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _376_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _377_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _378_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _379_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _380_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _381_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _382_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _383_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _384_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _385_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _386_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _387_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _388_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _389_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _390_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _391_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _392_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _393_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _394_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _395_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _396_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _397_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _398_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _399_ DFF_X1 + PLACED ( 38680 123252 ) N ; + - _400_ DFF_X1 + PLACED ( 38680 123252 ) N ; END COMPONENTS PINS 1 ; - io_1 + NET io_1 + DIRECTION INPUT + USE SIGNAL ; diff --git a/src/mpl/test/io_constraints8.tcl b/src/mpl/test/io_constraints8.tcl index 65b50fb2549..73961c1bbe8 100644 --- a/src/mpl/test/io_constraints8.tcl +++ b/src/mpl/test/io_constraints8.tcl @@ -1,4 +1,4 @@ -# Test if we available regions create based on the blocked regions for pins +# Test if the available regions created based on the blocked regions for pins # are correctly generated when there are no constraints at all. Connections # are needed so we trigger the closest available region distance computation # inside the annealer. diff --git a/src/odb/include/odb/geom.h b/src/odb/include/odb/geom.h index 03c6217ede8..fe26f30182e 100644 --- a/src/odb/include/odb/geom.h +++ b/src/odb/include/odb/geom.h @@ -356,6 +356,9 @@ class Line Point pt0() const; Point pt1() const; + void addX(int value); + void addY(int value); + friend dbIStream& operator>>(dbIStream& stream, Line& l); friend dbOStream& operator<<(dbOStream& stream, const Line& l); @@ -988,6 +991,18 @@ inline Point Line::pt1() const return pt1_; } +inline void Line::addX(int value) +{ + pt0_.setX(pt0_.getX() + value); + pt1_.setX(pt1_.getX() + value); +} + +inline void Line::addY(int value) +{ + pt0_.setY(pt0_.getY() + value); + pt1_.setY(pt1_.getY() + value); +} + inline bool Line::operator==(const Line& r) const { return pt0_ == r.pt0_ && pt1_ == r.pt1_; From 5a9af092ef30bcce01ed0114197e454f7a8bbb55 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Tue, 6 May 2025 12:33:46 -0300 Subject: [PATCH 27/34] mpl: 1) Address clang-tidy; 2) Renaming for clarity; 3) Move 'Boundary' definition and its functions to util; 4) Make usage of available regions consistent across steps. Signed-off-by: Arthur Koucher --- src/mpl/src/MplObserver.h | 5 +- src/mpl/src/SimulatedAnnealingCore.cpp | 19 +++---- src/mpl/src/SimulatedAnnealingCore.h | 4 +- src/mpl/src/clusterEngine.h | 3 +- src/mpl/src/graphics.cpp | 8 +-- src/mpl/src/graphics.h | 5 +- src/mpl/src/hier_rtlmp.cpp | 54 ++++++++++---------- src/mpl/src/hier_rtlmp.h | 5 +- src/mpl/src/object.cpp | 35 ------------- src/mpl/src/object.h | 19 +------ src/mpl/src/util.h | 68 +++++++++++++++++++++++--- 11 files changed, 106 insertions(+), 119 deletions(-) diff --git a/src/mpl/src/MplObserver.h b/src/mpl/src/MplObserver.h index 7a3fccbd3fd..8a282b2dd67 100644 --- a/src/mpl/src/MplObserver.h +++ b/src/mpl/src/MplObserver.h @@ -58,10 +58,7 @@ class MplObserver const std::vector& blocked_regions_for_pins) { } - virtual void setAvailableRegionsForPins( - const std::vector& available_regions_for_pins) - { - } + virtual void setAvailableRegionsForPins(const BoundaryRegionList& regions) {} virtual void setAreaPenalty(const PenaltyData& penalty) {} virtual void setBoundaryPenalty(const PenaltyData& penalty) {} diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 81f939bc9ab..7e3e85e5710 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -74,18 +74,13 @@ void SimulatedAnnealingCore::setDieArea(const Rect& die_area) template void SimulatedAnnealingCore::setAvailableRegionForPins( - const std::vector& regions) -{ - const float x_offset = -(block_->micronsToDbu(outline_.xMin())); - const float y_offset = -(block_->micronsToDbu(outline_.xMin())); - - available_regions_for_pins_.reserve(regions.size()); - for (const odb::Rect& region : regions) { - odb::Line region_line = rectToLine(block_, region, logger_); - region_line.addX(x_offset); - region_line.addX(y_offset); - available_regions_for_pins_.emplace_back(region_line, - getBoundary(block_, region)); + const BoundaryRegionList& regions) +{ + available_regions_for_pins_ = regions; + + for (BoundaryRegion& region : available_regions_for_pins_) { + region.line.addX(-block_->micronsToDbu(outline_.xMin())); + region.line.addY(-block_->micronsToDbu(outline_.xMin())); } } diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 3e0496fe556..6ae062854ce 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -98,7 +98,7 @@ class SimulatedAnnealingCore void fastSA(); - void setAvailableRegionForPins(const std::vector& regions); + void setAvailableRegionForPins(const BoundaryRegionList& regions); void initSequencePair(); void setDieArea(const Rect& die_area); void updateBestValidResult(); @@ -137,7 +137,7 @@ class SimulatedAnnealingCore Rect outline_; Rect die_area_; // Offset to the current outline. - std::vector available_regions_for_pins_; + BoundaryRegionList available_regions_for_pins_; // Number of macros that will actually be part of the sequence pair int macros_to_place_ = 0; diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index dfa6f3fb3b4..8c92303a1b5 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -12,6 +12,7 @@ #include #include "object.h" +#include "util.h" namespace par { class PartitionMgr; @@ -88,7 +89,7 @@ struct PhysicalHierarchy std::unique_ptr root; PhysicalHierarchyMaps maps; - std::vector available_regions_for_pins; + BoundaryRegionList available_regions_for_pins; float halo_width{0.0f}; float halo_height{0.0f}; diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp index 52b95468666..829f8f4335f 100644 --- a/src/mpl/src/graphics.cpp +++ b/src/mpl/src/graphics.cpp @@ -708,13 +708,9 @@ void Graphics::setBlockedRegionsForPins( blocked_regions_for_pins_ = blocked_regions_for_pins; } -void Graphics::setAvailableRegionsForPins( - const std::vector& available_regions_for_pins) +void Graphics::setAvailableRegionsForPins(const BoundaryRegionList& regions) { - for (const odb::Rect& region : available_regions_for_pins) { - available_regions_for_pins_.emplace_back( - rectToLine(block_, region, logger_), getBoundary(block_, region)); - } + available_regions_for_pins_ = regions; } void Graphics::eraseDrawing() diff --git a/src/mpl/src/graphics.h b/src/mpl/src/graphics.h index 31e8de158e6..29e35e58120 100644 --- a/src/mpl/src/graphics.h +++ b/src/mpl/src/graphics.h @@ -63,8 +63,7 @@ class Graphics : public gui::Renderer, public MplObserver void setFences(const std::map& fences) override; void setBlockedRegionsForPins( const std::vector& blocked_regions_for_pins) override; - void setAvailableRegionsForPins( - const std::vector& available_regions_for_pins) override; + void setAvailableRegionsForPins(const BoundaryRegionList& regions) override; void eraseDrawing() override; @@ -109,7 +108,7 @@ class Graphics : public gui::Renderer, public MplObserver int target_cluster_id_{-1}; std::vector> outlines_; std::vector blocked_regions_for_pins_; - std::vector available_regions_for_pins_; + BoundaryRegionList available_regions_for_pins_; // In Soft SA, we're shaping/placing the children of a certain parent, // so for this case, the current cluster is actually the current parent. diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 1e89a8dfd19..cb636fb2a0f 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -883,12 +883,12 @@ void HierRTLMP::searchForAvailableRegionsForPins() BoundaryToRegionsMap boundary_to_blocked_regions = getBoundaryToBlockedRegionsMap(blocked_regions_for_pins); - tree_->available_regions_for_pins + std::vector available_regions = computeAvailableRegions(boundary_to_blocked_regions); - available_regions_for_pins_.reserve(tree_->available_regions_for_pins.size()); - for (const odb::Rect& region : tree_->available_regions_for_pins) { - available_regions_for_pins_.emplace_back( + tree_->available_regions_for_pins.reserve(available_regions.size()); + for (const odb::Rect& region : available_regions) { + tree_->available_regions_for_pins.emplace_back( rectToLine(block_, region, logger_), getBoundary(block_, region)); } @@ -954,13 +954,14 @@ bool HierRTLMP::treeHasOnlyUnconstrainedIOs() const void HierRTLMP::createBlockagesForAvailableRegions() { int64_t io_span = 0; - for (const odb::Rect& region : tree_->available_regions_for_pins) { - io_span += region.margin() / 2; + for (const BoundaryRegion& region : tree_->available_regions_for_pins) { + io_span + += odb::Point::manhattanDistance(region.line.pt0(), region.line.pt1()); } const float depth = computePinAccessBaseDepth(block_->dbuToMicrons(io_span)); - for (const odb::Rect& region : tree_->available_regions_for_pins) { + for (const BoundaryRegion region : tree_->available_regions_for_pins) { createPinAccessBlockage(region, depth); } } @@ -996,9 +997,11 @@ void HierRTLMP::createBlockagesForConstraintRegions() const float io_density_factor = cluster_number_of_ios / total_ios; const float depth = base_depth * io_density_factor; - odb::Rect blockage_region + const odb::Rect region_rect = micronsToDbu(cluster_of_unplaced_ios->getBBox()); - createPinAccessBlockage(blockage_region, depth); + const odb::Line region_line = rectToLine(block_, region_rect, logger_); + const BoundaryRegion region(region_line, getBoundary(block_, region_rect)); + createPinAccessBlockage(region, depth); } } @@ -1069,13 +1072,11 @@ std::vector HierRTLMP::computeAvailableRegions( return available_regions; } -void HierRTLMP::createPinAccessBlockage(const odb::Rect& region, +void HierRTLMP::createPinAccessBlockage(const BoundaryRegion& region, const float depth) { - Boundary region_boundary = getBoundary(block_, region); - float blockage_depth; - if (isVertical(region_boundary)) { + if (isVertical(region.boundary)) { blockage_depth = depth > pin_access_depth_limits_.horizontal ? pin_access_depth_limits_.horizontal : depth; @@ -1085,18 +1086,19 @@ void HierRTLMP::createPinAccessBlockage(const odb::Rect& region, : depth; } - debugPrint( - logger_, - MPL, - "coarse_shaping", - 1, - "Creating pin access blockage in {} -> Region shape = {} , Depth = {}", - toString(region_boundary), - region, - blockage_depth); - - Rect blockage = dbuToMicrons(region); - switch (region_boundary) { + debugPrint(logger_, + MPL, + "coarse_shaping", + 1, + "Creating pin access blockage in {} -> Region line = ({}) ({}) , " + "Depth = {}", + toString(region.boundary), + region.line.pt0(), + region.line.pt1(), + blockage_depth); + + Rect blockage = dbuToMicrons(lineToRect(region.line)); + switch (region.boundary) { case L: { blockage.setXMax(blockage.xMin() + blockage_depth); break; @@ -2753,7 +2755,7 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro) } else { odb::Point nearest_region_point; computeDistToNearestRegion(macro->getBBox()->getBox().center(), - available_regions_for_pins_, + tree_->available_regions_for_pins, &nearest_region_point); odb::Rect center_rect(nearest_region_point, nearest_region_point); diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index c8ad3c7b05b..cdf91b8ee74 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -157,7 +157,7 @@ class HierRTLMP void computePinAccessDepthLimits(); bool treeHasOnlyUnconstrainedIOs() const; std::vector getClustersOfUnplacedIOPins() const; - void createPinAccessBlockage(const odb::Rect& region, float depth); + void createPinAccessBlockage(const BoundaryRegion& region, float depth); float computePinAccessBaseDepth(double io_span) const; void createBlockagesForAvailableRegions(); void createBlockagesForConstraintRegions(); @@ -295,9 +295,6 @@ class HierRTLMP PinAccessDepthLimits pin_access_depth_limits_; - // Cache needed for orientation improvement. - std::vector available_regions_for_pins_; - // Fast SA hyperparameter float init_prob_ = 0.9; const int max_num_step_ = 2000; diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp index b76330bbc46..f1ef71c13eb 100644 --- a/src/mpl/src/object.cpp +++ b/src/mpl/src/object.cpp @@ -18,41 +18,6 @@ namespace mpl { using utl::MPL; -/////////////////////////////////////////////////////////////////////// -// Basic utility functions - -std::string toString(const Boundary& pin_access) -{ - switch (pin_access) { - case L: - return std::string("L"); - case T: - return std::string("T"); - case R: - return std::string("R"); - case B: - return std::string("B"); - default: - return std::string("NONE"); - } -} - -Boundary opposite(const Boundary& pin_access) -{ - switch (pin_access) { - case L: - return R; - case T: - return B; - case R: - return L; - case B: - return T; - default: - return NONE; - } -} - /////////////////////////////////////////////////////////////////////// // Metrics Class Metrics::Metrics(unsigned int num_std_cell, diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index 68c9c41feba..199708b0a87 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -18,6 +18,7 @@ #include "odb/dbTypes.h" #include "odb/odb.h" #include "shapes.h" +#include "util.h" namespace odb { class Rect; @@ -74,24 +75,6 @@ using Point = std::pair; // we do not accept pre-placed std cells as our inputs. //***************************************************************************** -// Define the position of pin access blockage -// It can be {bottom, left, top, right} boundary of the cluster -// Each pin access blockage is modeled by a movable hard macro -// along the corresponding { B, L, T, R } boundary -// The size of the hard macro blockage is determined the by the -// size of that cluster -enum Boundary -{ - NONE, - B, - L, - T, - R -}; - -std::string toString(const Boundary& pin_access); -Boundary opposite(const Boundary& pin_access); - // Define the type for clusters // StdCellCluster only has std cells. In the cluster type, it // only has leaf_std_cells_ and dbModules_ diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index 04592000c1e..e1f40d9e923 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -6,10 +6,56 @@ #include #include +#include "odb/db.h" #include "odb/geom.h" #include "shapes.h" namespace mpl { +struct BoundaryRegion; + +using BoundaryRegionList = std::vector; + +// One of the edges of the die area. +enum Boundary +{ + NONE, + B, + L, + T, + R +}; + +inline std::string toString(const Boundary& pin_access) +{ + switch (pin_access) { + case L: + return std::string("L"); + case T: + return std::string("T"); + case R: + return std::string("R"); + case B: + return std::string("B"); + default: + return std::string("NONE"); + } +} + +inline Boundary opposite(const Boundary& pin_access) +{ + switch (pin_access) { + case L: + return R; + case T: + return B; + case R: + return L; + case B: + return T; + default: + return NONE; + } +} struct SACoreWeights { @@ -36,10 +82,12 @@ struct PenaltyData float normalization_factor{0.0f}; }; -// Used inside the annealer and during the orientation improvement step. -struct AvailableRegionForPins +// Object to help handling the available regions for pins inside MPL. +// Note that the blocked regions are still handled as odb:Rect's which +// is how they're stored in ODB. +struct BoundaryRegion { - AvailableRegionForPins(const odb::Line& line, const Boundary boundary) + BoundaryRegion(const odb::Line& line, const Boundary boundary) : line(line), boundary(boundary) { } @@ -85,6 +133,11 @@ inline Boundary getBoundary(odb::dbBlock* block, const odb::Rect& region) return boundary; } +inline odb::Rect lineToRect(const odb::Line line) +{ + return odb::Rect(line.pt0(), line.pt1()); +} + inline odb::Line rectToLine(odb::dbBlock* block, const odb::Rect& rect, utl::Logger* logger) @@ -118,9 +171,8 @@ inline odb::Line rectToLine(odb::dbBlock* block, return line; } -inline odb::Point computeNearestPointInRegion( - const AvailableRegionForPins& region, - const odb::Point& target) +inline odb::Point computeNearestPointInRegion(const BoundaryRegion& region, + const odb::Point& target) { if (region.boundary == L || region.boundary == R) { if (target.y() >= region.line.pt1().y()) { @@ -146,11 +198,11 @@ inline odb::Point computeNearestPointInRegion( // of the nearest region. inline double computeDistToNearestRegion( const odb::Point& macro_location, - const std::vector& regions, + const std::vector& regions, odb::Point* closest_point) { double smallest_distance = std::numeric_limits::max(); - for (const AvailableRegionForPins& region : regions) { + for (const BoundaryRegion& region : regions) { odb::Point closest_point_in_region = computeNearestPointInRegion(region, macro_location); const double dist_to_closest_point_in_region = std::sqrt( From 284223c334837adf0bfd8fafb60f4823415f08c4 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Tue, 6 May 2025 17:38:03 -0300 Subject: [PATCH 28/34] mpl: 1) Revert to previous fixed terminal approach (have actual SoftMacros with shapes for Unplaced IOs); 2) Use distance to closest point in region for constraint regions; 3) Revert changes to remove unused fixed terminals APIs; 4) Store constraints' region data to be used inside annealer and orient. improvement inside the tree. Signed-off-by: Arthur Koucher --- src/mpl/src/MplObserver.h | 4 +++ src/mpl/src/SimulatedAnnealingCore.cpp | 39 +++++++++++++++++--------- src/mpl/src/SimulatedAnnealingCore.h | 5 +++- src/mpl/src/clusterEngine.cpp | 18 ++++++++++-- src/mpl/src/clusterEngine.h | 6 +++- src/mpl/src/graphics.cpp | 23 +++++++++++---- src/mpl/src/graphics.h | 7 +++-- src/mpl/src/hier_rtlmp.cpp | 15 +++++++--- src/mpl/src/object.cpp | 22 +++++++++++++++ src/mpl/src/object.h | 3 ++ src/mpl/src/util.h | 14 +++++---- 11 files changed, 121 insertions(+), 35 deletions(-) diff --git a/src/mpl/src/MplObserver.h b/src/mpl/src/MplObserver.h index 8a282b2dd67..8405e0d93c5 100644 --- a/src/mpl/src/MplObserver.h +++ b/src/mpl/src/MplObserver.h @@ -54,6 +54,10 @@ class MplObserver virtual void setOutline(const odb::Rect& outline) {} virtual void setGuides(const std::map& guides) {} virtual void setFences(const std::map& fences) {} + virtual void setIOConstraintsMap( + const ClusterToBoundaryRegionMap& io_cluster_to_constraint) + { + } virtual void setBlockedRegionsForPins( const std::vector& blocked_regions_for_pins) { diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 7e3e85e5710..8c49f542f77 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -62,6 +62,8 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(odb::dbBlock* block, setDieArea(tree->die_area); setAvailableRegionForPins(tree->available_regions_for_pins); + + io_cluster_to_constraint_ = tree->io_cluster_to_constraint; } template @@ -274,8 +276,8 @@ void SimulatedAnnealingCore::calWirelength() T& source = macros_[net.terminals.first]; T& target = macros_[net.terminals.second]; - if (target.isClusterOfUnconstrainedIOPins()) { - addClosestAvailableRegionDistToWL(source, net.weight); + if (target.isClusterOfUnplacedIOPins()) { + computeWLForClusterOfUnplacedIOPins(source, target, net.weight); continue; } @@ -299,8 +301,9 @@ void SimulatedAnnealingCore::calWirelength() } template -void SimulatedAnnealingCore::addClosestAvailableRegionDistToWL( +void SimulatedAnnealingCore::computeWLForClusterOfUnplacedIOPins( const T& macro, + const T& unplaced_ios, const float net_weight) { // To generate maximum cost. @@ -311,19 +314,29 @@ void SimulatedAnnealingCore::addClosestAvailableRegionDistToWL( return; } - if (available_regions_for_pins_.empty()) { - logger_->critical( - utl::MPL, - 47, - "There's no available region for the unconstrained pins!"); - } - const odb::Point macro_location(block_->micronsToDbu(macro.getPinX()), block_->micronsToDbu(macro.getPinY())); - const double nearest_distance = computeDistToNearestRegion( - macro_location, available_regions_for_pins_, nullptr); + double smallest_distance; + if (unplaced_ios.getCluster()->isClusterOfUnconstrainedIOPins()) { + if (available_regions_for_pins_.empty()) { + logger_->critical( + utl::MPL, + 47, + "There's no available region for the unconstrained pins!"); + } + + smallest_distance = computeDistToNearestRegion( + macro_location, available_regions_for_pins_, nullptr); + } else { + // This will always have a single element. We do this so can + // we can use the same method as the unconstrained pins case. + BoundaryRegionList constraint + = {io_cluster_to_constraint_.at(unplaced_ios.getCluster())}; + smallest_distance + = computeDistToNearestRegion(macro_location, constraint, nullptr); + } - wirelength_ += net_weight * block_->dbuToMicrons(nearest_distance); + wirelength_ += net_weight * block_->dbuToMicrons(smallest_distance); } // We consider the macro outside the outline based on the location of diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 6ae062854ce..8a27bb14256 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -108,7 +108,9 @@ class SimulatedAnnealingCore virtual void calPenalty() = 0; void calOutlinePenalty(); void calWirelength(); - void addClosestAvailableRegionDistToWL(const T& macro, float net_weight); + void computeWLForClusterOfUnplacedIOPins(const T& macro, + const T& unplaced_ios, + float net_weight); bool isOutsideTheOutline(const T& macro) const; void calGuidancePenalty(); void calFencePenalty(); @@ -138,6 +140,7 @@ class SimulatedAnnealingCore Rect die_area_; // Offset to the current outline. BoundaryRegionList available_regions_for_pins_; + ClusterToBoundaryRegionMap io_cluster_to_constraint_; // Number of macros that will actually be part of the sequence pair int macros_to_place_ = 0; diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index 584c2ffc39e..bb097d0bdb3 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -12,6 +12,7 @@ #include #include +#include "MplObserver.h" #include "db_sta/dbNetwork.hh" #include "par/PartitionMgr.h" #include "sta/Liberty.hh" @@ -22,11 +23,13 @@ using utl::MPL; ClusteringEngine::ClusteringEngine(odb::dbBlock* block, sta::dbNetwork* network, utl::Logger* logger, - par::PartitionMgr* triton_part) + par::PartitionMgr* triton_part, + MplObserver* graphics) : block_(block), network_(network), logger_(logger), - triton_part_(triton_part) + triton_part_(triton_part), + graphics_(graphics) { } @@ -372,6 +375,10 @@ void ClusteringEngine::createIOClusters() createClusterOfUnplacedIOs(bterm); } } + + if (graphics_) { + graphics_->setIOConstraintsMap(tree_->io_cluster_to_constraint); + } } Cluster* ClusteringEngine::findIOClusterWithSameConstraint( @@ -417,6 +424,13 @@ void ClusteringEngine::createClusterOfUnplacedIOs(odb::dbBTerm* bterm) block_->dbuToMicrons(constraint_shape.dy()), is_cluster_of_unconstrained_io_pins); + if (!is_cluster_of_unconstrained_io_pins) { + BoundaryRegion constraint_region( + rectToLine(block_, constraint_shape, logger_), + getBoundary(block_, constraint_shape)); + tree_->io_cluster_to_constraint[cluster.get()] = constraint_region; + } + tree_->maps.bterm_to_cluster_id[bterm] = id_; tree_->maps.id_to_cluster[id_++] = cluster.get(); tree_->root->addChild(std::move(cluster)); diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 8c92303a1b5..73b30c80512 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -27,6 +27,7 @@ class dbNetwork; } namespace mpl { +class MplObserver; using InstToHardMap = std::map>; using ModuleToMetricsMap = std::map>; @@ -90,6 +91,7 @@ struct PhysicalHierarchy PhysicalHierarchyMaps maps; BoundaryRegionList available_regions_for_pins; + ClusterToBoundaryRegionMap io_cluster_to_constraint; float halo_width{0.0f}; float halo_height{0.0f}; @@ -131,7 +133,8 @@ class ClusteringEngine ClusteringEngine(odb::dbBlock* block, sta::dbNetwork* network, utl::Logger* logger, - par::PartitionMgr* triton_part); + par::PartitionMgr* triton_part, + MplObserver* graphics); void run(); @@ -256,6 +259,7 @@ class ClusteringEngine sta::dbNetwork* network_; utl::Logger* logger_; par::PartitionMgr* triton_part_; + MplObserver* graphics_; Metrics* design_metrics_{nullptr}; PhysicalHierarchy* tree_{nullptr}; diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp index 829f8f4335f..aa36b5db864 100644 --- a/src/mpl/src/graphics.cpp +++ b/src/mpl/src/graphics.cpp @@ -559,8 +559,8 @@ void Graphics::drawBundledNets(gui::Painter& painter, const T& source = macros[bundled_net.terminals.first]; const T& target = macros[bundled_net.terminals.second]; - if (target.isClusterOfUnconstrainedIOPins()) { - drawDistToClosestAvailableRegion(painter, source, target); + if (target.isClusterOfUnplacedIOPins()) { + drawDistToRegion(painter, source, target); continue; } @@ -578,9 +578,9 @@ void Graphics::drawBundledNets(gui::Painter& painter, } template -void Graphics::drawDistToClosestAvailableRegion(gui::Painter& painter, - const T& macro, - const T& io) +void Graphics::drawDistToRegion(gui::Painter& painter, + const T& macro, + const T& io) { if (isOutsideTheOutline(macro)) { return; @@ -592,7 +592,12 @@ void Graphics::drawDistToClosestAvailableRegion(gui::Painter& painter, from.addY(outline_.yMin()); odb::Point to; - computeDistToNearestRegion(from, available_regions_for_pins_, &to); + if (io.getCluster()->isClusterOfUnconstrainedIOPins()) { + computeDistToNearestRegion(from, available_regions_for_pins_, &to); + } else { + computeDistToNearestRegion( + from, {io_cluster_to_constraint_.at(io.getCluster())}, &to); + } painter.drawLine(from, to); painter.drawString( @@ -702,6 +707,12 @@ void Graphics::setFences(const std::map& fences) fences_ = fences; } +void Graphics::setIOConstraintsMap( + const ClusterToBoundaryRegionMap& io_cluster_to_constraint) +{ + io_cluster_to_constraint_ = io_cluster_to_constraint; +} + void Graphics::setBlockedRegionsForPins( const std::vector& blocked_regions_for_pins) { diff --git a/src/mpl/src/graphics.h b/src/mpl/src/graphics.h index 29e35e58120..c9ba85ad5ef 100644 --- a/src/mpl/src/graphics.h +++ b/src/mpl/src/graphics.h @@ -61,6 +61,8 @@ class Graphics : public gui::Renderer, public MplObserver void setCurrentCluster(Cluster* current_cluster) override; void setGuides(const std::map& guides) override; void setFences(const std::map& fences) override; + void setIOConstraintsMap( + const ClusterToBoundaryRegionMap& io_cluster_to_constraint) override; void setBlockedRegionsForPins( const std::vector& blocked_regions_for_pins) override; void setAvailableRegionsForPins(const BoundaryRegionList& regions) override; @@ -81,9 +83,7 @@ class Graphics : public gui::Renderer, public MplObserver template void drawBundledNets(gui::Painter& painter, const std::vector& macros); template - void drawDistToClosestAvailableRegion(gui::Painter& painter, - const T& macro, - const T& io); + void drawDistToRegion(gui::Painter& painter, const T& macro, const T& io); template bool isOutsideTheOutline(const T& macro) const; void addOutlineOffsetToLine(odb::Point& from, odb::Point& to); @@ -109,6 +109,7 @@ class Graphics : public gui::Renderer, public MplObserver std::vector> outlines_; std::vector blocked_regions_for_pins_; BoundaryRegionList available_regions_for_pins_; + ClusterToBoundaryRegionMap io_cluster_to_constraint_; // In Soft SA, we're shaping/placing the children of a certain parent, // so for this case, the current cluster is actually the current parent. diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index cb636fb2a0f..6c596cc8223 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -259,7 +259,7 @@ void HierRTLMP::init() void HierRTLMP::runMultilevelAutoclustering() { clustering_engine_ = std::make_unique( - block_, network_, logger_, tritonpart_); + block_, network_, logger_, tritonpart_, graphics_.get()); // Set target structure clustering_engine_->setTree(tree_.get()); @@ -955,6 +955,7 @@ void HierRTLMP::createBlockagesForAvailableRegions() { int64_t io_span = 0; for (const BoundaryRegion& region : tree_->available_regions_for_pins) { + // TO DO: Use square distance. io_span += odb::Point::manhattanDistance(region.line.pt0(), region.line.pt1()); } @@ -2119,14 +2120,20 @@ void HierRTLMP::createFixedTerminal(Cluster* cluster, const Rect& outline, std::vector& macros) { + // A conventional fixed terminal is just a point without + // the cluster data. Point location = cluster->getCenter(); float width = 0.0f; float height = 0.0f; Cluster* terminal_cluster = nullptr; - if (cluster->isClusterOfUnconstrainedIOPins()) { - // The cluster data is needed so that the annealer - // can identify the cluster of unconstrained IOs. + if (cluster->isClusterOfUnplacedIOPins()) { + // Clusters of unplaced IOs are not treated as conventional + // fixed terminals. As they correspond to regions, we need + // both their actual shape and their cluster data inside SA. + location = {cluster->getX(), cluster->getY()}; + width = cluster->getWidth(); + height = cluster->getHeight(); terminal_cluster = cluster; } diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp index f1ef71c13eb..dc37f984dfb 100644 --- a/src/mpl/src/object.cpp +++ b/src/mpl/src/object.cpp @@ -782,6 +782,17 @@ bool HardMacro::operator==(const HardMacro& macro) const return (width_ == macro.width_) && (height_ == macro.height_); } +// Used to identify if a fixed terminal correponds to a cluster of +// unplaced IO pins when running HardMacro SA. +bool HardMacro::isClusterOfUnplacedIOPins() const +{ + if (!cluster_) { + return false; + } + + return cluster_->isClusterOfUnplacedIOPins(); +} + // Cluster support to identify if a fixed terminal correponds // to the cluster of unconstrained IO pins when running HardMacro SA. bool HardMacro::isClusterOfUnconstrainedIOPins() const @@ -1268,6 +1279,17 @@ bool SoftMacro::isMixedCluster() const return (cluster_->getClusterType() == MixedCluster); } +// Used to identify if a fixed terminal correponds to a cluster of +// unplaced IO pins when running SoftMacro SA. +bool SoftMacro::isClusterOfUnplacedIOPins() const +{ + if (!cluster_) { + return false; + } + + return cluster_->isClusterOfUnplacedIOPins(); +} + // Used to identify if a fixed terminal correponds to the cluster of // unconstrained IO pins when running SoftMacro SA. bool SoftMacro::isClusterOfUnconstrainedIOPins() const diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index 199708b0a87..c9e77a2d616 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -323,6 +323,8 @@ class HardMacro bool operator==(const HardMacro& macro) const; void setCluster(Cluster* cluster) { cluster_ = cluster; } + Cluster* getCluster() const { return cluster_; } + bool isClusterOfUnplacedIOPins() const; bool isClusterOfUnconstrainedIOPins() const; // Get Physical Information @@ -489,6 +491,7 @@ class SoftMacro bool isMacroCluster() const; bool isStdCellCluster() const; bool isMixedCluster() const; + bool isClusterOfUnplacedIOPins() const; bool isClusterOfUnconstrainedIOPins() const; void setLocationF(float x, float y); void setShapeF(float width, float height); diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index e1f40d9e923..2debf032cd7 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -3,6 +3,7 @@ #pragma once +#include #include #include @@ -12,7 +13,9 @@ namespace mpl { struct BoundaryRegion; +class Cluster; +using ClusterToBoundaryRegionMap = std::map; using BoundaryRegionList = std::vector; // One of the edges of the die area. @@ -87,6 +90,7 @@ struct PenaltyData // is how they're stored in ODB. struct BoundaryRegion { + BoundaryRegion() = default; BoundaryRegion(const odb::Line& line, const Boundary boundary) : line(line), boundary(boundary) { @@ -194,19 +198,19 @@ inline odb::Point computeNearestPointInRegion(const BoundaryRegion& region, return odb::Point(target.x(), region.line.pt0().y()); } -// The distance in DBU from the macro bundled pin to the nearest point -// of the nearest region. +// The distance in DBU from the source to the nearest point of the nearest +// region. inline double computeDistToNearestRegion( - const odb::Point& macro_location, + const odb::Point& source, const std::vector& regions, odb::Point* closest_point) { double smallest_distance = std::numeric_limits::max(); for (const BoundaryRegion& region : regions) { odb::Point closest_point_in_region - = computeNearestPointInRegion(region, macro_location); + = computeNearestPointInRegion(region, source); const double dist_to_closest_point_in_region = std::sqrt( - odb::Point::squaredDistance(macro_location, closest_point_in_region)); + odb::Point::squaredDistance(source, closest_point_in_region)); if (dist_to_closest_point_in_region < smallest_distance) { smallest_distance = dist_to_closest_point_in_region; if (closest_point) { From a76731b3a66fd6d15016490300986cf4f9fae81e Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Tue, 6 May 2025 18:10:38 -0300 Subject: [PATCH 29/34] mpl: 1) Adapt orientation step to use dist to closest point on both unconstrained and constrained pins; 2) Fix target point of distance computation for unconstrained pins during orientation improvement; 3) Use squared dist. instead of manhattam when computing IO spans. Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 27 +++++++++++++-------------- src/mpl/test/io_constraints6.defok | 2 +- src/mpl/test/io_constraints8.defok | 2 +- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 6c596cc8223..91c206032ca 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -953,11 +953,10 @@ bool HierRTLMP::treeHasOnlyUnconstrainedIOs() const void HierRTLMP::createBlockagesForAvailableRegions() { - int64_t io_span = 0; + double io_span = 0.0; for (const BoundaryRegion& region : tree_->available_regions_for_pins) { - // TO DO: Use square distance. - io_span - += odb::Point::manhattanDistance(region.line.pt0(), region.line.pt1()); + io_span += std::sqrt( + odb::Point::squaredDistance(region.line.pt0(), region.line.pt1())); } const float depth = computePinAccessBaseDepth(block_->dbuToMicrons(io_span)); @@ -2754,20 +2753,20 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro) for (odb::dbBTerm* bterm : net->getBTerms()) { auto constraint_region = bterm->getConstraintRegion(); + odb::Point closest_point; if (constraint_region) { - int x = constraint_region->xCenter(); - int y = constraint_region->yCenter(); - odb::Rect region_rect(x, y, x, y); - net_box.merge(region_rect); + BoundaryRegion constraint( + rectToLine(block_, *constraint_region, logger_), + getBoundary(block_, *constraint_region)); + computeDistToNearestRegion( + macro_pin->getBBox().center(), {constraint}, &closest_point); } else { - odb::Point nearest_region_point; - computeDistToNearestRegion(macro->getBBox()->getBox().center(), + computeDistToNearestRegion(macro_pin->getBBox().center(), tree_->available_regions_for_pins, - &nearest_region_point); - - odb::Rect center_rect(nearest_region_point, nearest_region_point); - net_box.merge(center_rect); + &closest_point); } + odb::Rect point_rect(closest_point, closest_point); + net_box.merge(point_rect); } wirelength += block_->dbuToMicrons(net_box.dx() + net_box.dy()); diff --git a/src/mpl/test/io_constraints6.defok b/src/mpl/test/io_constraints6.defok index ecd8f4d73e8..8652f21d6b8 100644 --- a/src/mpl/test/io_constraints6.defok +++ b/src/mpl/test/io_constraints6.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8150 ) N ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 8000 8010 ) S ; - _001_ DFF_X1 + PLACED ( 254680 123252 ) N ; - _002_ DFF_X1 + PLACED ( 254680 123252 ) N ; - _003_ DFF_X1 + PLACED ( 254680 123252 ) N ; diff --git a/src/mpl/test/io_constraints8.defok b/src/mpl/test/io_constraints8.defok index 460e1eafdcd..5c4706fea61 100644 --- a/src/mpl/test/io_constraints8.defok +++ b/src/mpl/test/io_constraints8.defok @@ -114,7 +114,7 @@ TRACKS Y 140 DO 282 STEP 3200 LAYER metal9 ; TRACKS X 190 DO 282 STEP 3200 LAYER metal10 ; TRACKS Y 140 DO 282 STEP 3200 LAYER metal10 ; COMPONENTS 401 ; - - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8010 ) FS ; + - MACRO_1 HM_100x100_1x1 + FIXED ( 91820 8010 ) S ; - _001_ DFF_X1 + PLACED ( 38680 123252 ) N ; - _002_ DFF_X1 + PLACED ( 38680 123252 ) N ; - _003_ DFF_X1 + PLACED ( 38680 123252 ) N ; From 0ccc66214367ade7734fc3e8849ca4edc887101b Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Wed, 7 May 2025 10:34:23 -0300 Subject: [PATCH 30/34] mpl: 1) Reordering of arguments for clarity; 2) Minor refactor for readability; 3) Removal of cached map cluster -> constraint for simplification; 4) Avoid constraint region copy; 5) Adapt names and comments to preserve concision. Signed-off-by: Arthur Koucher --- src/mpl/src/SACoreHardMacro.cpp | 6 +++--- src/mpl/src/SACoreSoftMacro.cpp | 6 +++--- src/mpl/src/SimulatedAnnealingCore.cpp | 16 +++++++--------- src/mpl/src/SimulatedAnnealingCore.h | 9 ++++----- src/mpl/src/clusterEngine.cpp | 20 ++++++++------------ src/mpl/src/clusterEngine.h | 3 --- src/mpl/src/hier_rtlmp.cpp | 10 +++++----- src/mpl/src/hier_rtlmp.h | 9 +++++---- src/mpl/src/object.cpp | 12 ++++++------ src/mpl/src/object.h | 1 - src/mpl/src/util.h | 20 +++++++++----------- 11 files changed, 50 insertions(+), 62 deletions(-) diff --git a/src/mpl/src/SACoreHardMacro.cpp b/src/mpl/src/SACoreHardMacro.cpp index ddaa164ab50..693c8299671 100644 --- a/src/mpl/src/SACoreHardMacro.cpp +++ b/src/mpl/src/SACoreHardMacro.cpp @@ -33,8 +33,7 @@ SACoreHardMacro::SACoreHardMacro(PhysicalHierarchy* tree, MplObserver* graphics, utl::Logger* logger, odb::dbBlock* block) - : SimulatedAnnealingCore(block, - tree, + : SimulatedAnnealingCore(tree, outline, macros, core_weights, @@ -47,7 +46,8 @@ SACoreHardMacro::SACoreHardMacro(PhysicalHierarchy* tree, num_perturb_per_step, seed, graphics, - logger) + logger, + block) { flip_prob_ = flip_prob; } diff --git a/src/mpl/src/SACoreSoftMacro.cpp b/src/mpl/src/SACoreSoftMacro.cpp index 77fff8a750b..9a99d86ff20 100644 --- a/src/mpl/src/SACoreSoftMacro.cpp +++ b/src/mpl/src/SACoreSoftMacro.cpp @@ -44,8 +44,7 @@ SACoreSoftMacro::SACoreSoftMacro(PhysicalHierarchy* tree, MplObserver* graphics, utl::Logger* logger, odb::dbBlock* block) - : SimulatedAnnealingCore(block, - tree, + : SimulatedAnnealingCore(tree, outline, macros, core_weights, @@ -58,7 +57,8 @@ SACoreSoftMacro::SACoreSoftMacro(PhysicalHierarchy* tree, num_perturb_per_step, seed, graphics, - logger), + logger, + block), root_(tree->root.get()) { boundary_weight_ = boundary_weight; diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 8c49f542f77..4c45c6cfd7c 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -22,8 +22,7 @@ namespace mpl { using std::string; template -SimulatedAnnealingCore::SimulatedAnnealingCore(odb::dbBlock* block, - PhysicalHierarchy* tree, +SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, const Rect& outline, const std::vector& macros, const SACoreWeights& weights, @@ -37,8 +36,9 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(odb::dbBlock* block, int num_perturb_per_step, unsigned seed, MplObserver* graphics, - utl::Logger* logger) - : block_(block), outline_(outline), graphics_(graphics) + utl::Logger* logger, + odb::dbBlock* block) + : outline_(outline), graphics_(graphics), block_(block) { core_weights_ = weights; @@ -328,12 +328,10 @@ void SimulatedAnnealingCore::computeWLForClusterOfUnplacedIOPins( smallest_distance = computeDistToNearestRegion( macro_location, available_regions_for_pins_, nullptr); } else { - // This will always have a single element. We do this so can - // we can use the same method as the unconstrained pins case. - BoundaryRegionList constraint - = {io_cluster_to_constraint_.at(unplaced_ios.getCluster())}; + Cluster* cluster = unplaced_ios.getCluster(); + const BoundaryRegion& constraint = io_cluster_to_constraint_.at(cluster); smallest_distance - = computeDistToNearestRegion(macro_location, constraint, nullptr); + = computeDistToNearestRegion(macro_location, {constraint}, nullptr); } wirelength_ += net_weight * block_->dbuToMicrons(smallest_distance); diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 8a27bb14256..3e897f58fa8 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -38,8 +38,7 @@ template class SimulatedAnnealingCore { public: - SimulatedAnnealingCore(odb::dbBlock* block, - PhysicalHierarchy* tree, + SimulatedAnnealingCore(PhysicalHierarchy* tree, const Rect& outline, const std::vector& macros, const SACoreWeights& weights, @@ -53,7 +52,8 @@ class SimulatedAnnealingCore int num_perturb_per_step, unsigned seed, MplObserver* graphics, - utl::Logger* logger); + utl::Logger* logger, + odb::dbBlock* block); virtual ~SimulatedAnnealingCore() = default; @@ -134,8 +134,6 @@ class SimulatedAnnealingCore void reportLocations() const; void report(const PenaltyData& penalty) const; - odb::dbBlock* block_; - Rect outline_; Rect die_area_; // Offset to the current outline. @@ -206,6 +204,7 @@ class SimulatedAnnealingCore utl::Logger* logger_ = nullptr; MplObserver* graphics_ = nullptr; + odb::dbBlock* block_; Result best_valid_result_; diff --git a/src/mpl/src/clusterEngine.cpp b/src/mpl/src/clusterEngine.cpp index bb097d0bdb3..ba819fe3bc0 100644 --- a/src/mpl/src/clusterEngine.cpp +++ b/src/mpl/src/clusterEngine.cpp @@ -389,8 +389,9 @@ Cluster* ClusteringEngine::findIOClusterWithSameConstraint( return cluster_of_unconstrained_io_pins_; } - for (const auto& [cluster, cluster_constraint] : unplaced_ios_to_region_) { - if (bterm_constraint == cluster_constraint) { + for (const auto& [cluster, constraint_region] : + tree_->io_cluster_to_constraint) { + if (bterm_constraint == lineToRect(constraint_region.line)) { return cluster; } } @@ -406,11 +407,13 @@ void ClusteringEngine::createClusterOfUnplacedIOs(odb::dbBTerm* bterm) bool is_cluster_of_unconstrained_io_pins = false; odb::Rect constraint_shape; - const std::optional& bterm_constraint - = bterm->getConstraintRegion(); + const auto& bterm_constraint = bterm->getConstraintRegion(); if (bterm_constraint) { constraint_shape = *bterm_constraint; - unplaced_ios_to_region_[cluster.get()] = constraint_shape; + BoundaryRegion constraint_region( + rectToLine(block_, constraint_shape, logger_), + getBoundary(block_, constraint_shape)); + tree_->io_cluster_to_constraint[cluster.get()] = constraint_region; } else { constraint_shape = block_->getDieArea(); is_cluster_of_unconstrained_io_pins = true; @@ -424,13 +427,6 @@ void ClusteringEngine::createClusterOfUnplacedIOs(odb::dbBTerm* bterm) block_->dbuToMicrons(constraint_shape.dy()), is_cluster_of_unconstrained_io_pins); - if (!is_cluster_of_unconstrained_io_pins) { - BoundaryRegion constraint_region( - rectToLine(block_, constraint_shape, logger_), - getBoundary(block_, constraint_shape)); - tree_->io_cluster_to_constraint[cluster.get()] = constraint_region; - } - tree_->maps.bterm_to_cluster_id[bterm] = id_; tree_->maps.id_to_cluster[id_++] = cluster.get(); tree_->root->addChild(std::move(cluster)); diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 73b30c80512..320788c2d85 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -264,9 +264,6 @@ class ClusteringEngine Metrics* design_metrics_{nullptr}; PhysicalHierarchy* tree_{nullptr}; - // Cache the shapes/constraint regions in dbu to avoid comparison problems. - std::map unplaced_ios_to_region_; - // Keep this pointer to avoid searching for it when creating IO clusters. Cluster* cluster_of_unconstrained_io_pins_{nullptr}; diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 91c206032ca..ce793620b35 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -2752,20 +2752,20 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro) } for (odb::dbBTerm* bterm : net->getBTerms()) { - auto constraint_region = bterm->getConstraintRegion(); - odb::Point closest_point; + const auto& constraint_region = bterm->getConstraintRegion(); + odb::Point nearest_point; if (constraint_region) { BoundaryRegion constraint( rectToLine(block_, *constraint_region, logger_), getBoundary(block_, *constraint_region)); computeDistToNearestRegion( - macro_pin->getBBox().center(), {constraint}, &closest_point); + macro_pin->getBBox().center(), {constraint}, &nearest_point); } else { computeDistToNearestRegion(macro_pin->getBBox().center(), tree_->available_regions_for_pins, - &closest_point); + &nearest_point); } - odb::Rect point_rect(closest_point, closest_point); + odb::Rect point_rect(nearest_point, nearest_point); net_box.merge(point_rect); } diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index cdf91b8ee74..708345f1e4d 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -192,10 +192,6 @@ class HierRTLMP float offset_x, float offset_y); void mergeNets(std::vector& nets); - template - void createFixedTerminal(Cluster* cluster, - const Rect& outline, - std::vector& macros); // Hierarchical Macro Placement 2nd stage: Macro Placement void placeMacros(Cluster* cluster); @@ -228,6 +224,11 @@ class HierRTLMP odb::Rect micronsToDbu(const Rect& micron_rect); Rect dbuToMicrons(const odb::Rect& dbu_rect); + template + void createFixedTerminal(Cluster* cluster, + const Rect& outline, + std::vector& macros); + odb::Rect getRect(Boundary boundary) const; bool isVertical(Boundary boundary) const; diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp index dc37f984dfb..37362c16c5f 100644 --- a/src/mpl/src/object.cpp +++ b/src/mpl/src/object.cpp @@ -782,8 +782,8 @@ bool HardMacro::operator==(const HardMacro& macro) const return (width_ == macro.width_) && (height_ == macro.height_); } -// Used to identify if a fixed terminal correponds to a cluster of -// unplaced IO pins when running HardMacro SA. +// Cluster support to identify if a fixed terminal correponds +// to a cluster of unplaced IO pins when running HardMacro SA. bool HardMacro::isClusterOfUnplacedIOPins() const { if (!cluster_) { @@ -1279,8 +1279,8 @@ bool SoftMacro::isMixedCluster() const return (cluster_->getClusterType() == MixedCluster); } -// Used to identify if a fixed terminal correponds to a cluster of -// unplaced IO pins when running SoftMacro SA. +// Cluster support to identify if a fixed terminal correponds +// to a cluster of unplaced IO pins when running SoftMacro SA. bool SoftMacro::isClusterOfUnplacedIOPins() const { if (!cluster_) { @@ -1290,8 +1290,8 @@ bool SoftMacro::isClusterOfUnplacedIOPins() const return cluster_->isClusterOfUnplacedIOPins(); } -// Used to identify if a fixed terminal correponds to the cluster of -// unconstrained IO pins when running SoftMacro SA. +// Cluster support to identify if a fixed terminal correponds +// to the cluster of unconstrained IO pins when running SoftMacro SA. bool SoftMacro::isClusterOfUnconstrainedIOPins() const { if (!cluster_) { diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index c9e77a2d616..95be2a0bcec 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -258,7 +258,6 @@ class Cluster // all the macros in the cluster std::vector hard_macros_; - int io_pins_count_{0}; bool is_cluster_of_unplaced_io_pins_{false}; bool is_cluster_of_unconstrained_io_pins_{false}; bool is_io_pad_cluster_{false}; diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index 2debf032cd7..9c7ff09ca8f 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -85,9 +85,7 @@ struct PenaltyData float normalization_factor{0.0f}; }; -// Object to help handling the available regions for pins inside MPL. -// Note that the blocked regions are still handled as odb:Rect's which -// is how they're stored in ODB. +// Object to help handling available regions and constraint regions for pins. struct BoundaryRegion { BoundaryRegion() = default; @@ -203,18 +201,18 @@ inline odb::Point computeNearestPointInRegion(const BoundaryRegion& region, inline double computeDistToNearestRegion( const odb::Point& source, const std::vector& regions, - odb::Point* closest_point) + odb::Point* nearest_point) { double smallest_distance = std::numeric_limits::max(); for (const BoundaryRegion& region : regions) { - odb::Point closest_point_in_region + odb::Point nearest_point_in_region = computeNearestPointInRegion(region, source); - const double dist_to_closest_point_in_region = std::sqrt( - odb::Point::squaredDistance(source, closest_point_in_region)); - if (dist_to_closest_point_in_region < smallest_distance) { - smallest_distance = dist_to_closest_point_in_region; - if (closest_point) { - *closest_point = closest_point_in_region; + const double dist_to_nearest_point = std::sqrt( + odb::Point::squaredDistance(source, nearest_point_in_region)); + if (dist_to_nearest_point < smallest_distance) { + smallest_distance = dist_to_nearest_point; + if (nearest_point) { + *nearest_point = nearest_point_in_region; } } } From 7087692719721073a7a0005f221bec670b96171e Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 9 May 2025 11:58:02 -0300 Subject: [PATCH 31/34] mpl: 1) Use enum class; 2) Remove unused NONE enumeration; 3) Remove all default cases from switch statements; 4) Fix initial value of BoundaryRegion object; 5) Reduce some verbosity. Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 62 ++++++++---------- src/mpl/src/util.h | 128 ++++++++++++++++++------------------- 2 files changed, 86 insertions(+), 104 deletions(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 0d9d7f5911a..e81bd52a150 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -1011,10 +1011,10 @@ BoundaryToRegionsMap HierRTLMP::getBoundaryToBlockedRegionsMap( BoundaryToRegionsMap boundary_to_blocked_regions; std::queue blocked_regions; - boundary_to_blocked_regions[L] = blocked_regions; - boundary_to_blocked_regions[R] = blocked_regions; - boundary_to_blocked_regions[B] = blocked_regions; - boundary_to_blocked_regions[T] = blocked_regions; + boundary_to_blocked_regions[Boundary::L] = blocked_regions; + boundary_to_blocked_regions[Boundary::R] = blocked_regions; + boundary_to_blocked_regions[Boundary::B] = blocked_regions; + boundary_to_blocked_regions[Boundary::T] = blocked_regions; for (const odb::Rect& blocked_region : blocked_regions_for_pins) { Boundary boundary = getBoundary(block_, blocked_region); @@ -1099,28 +1099,22 @@ void HierRTLMP::createPinAccessBlockage(const BoundaryRegion& region, Rect blockage = dbuToMicrons(lineToRect(region.line)); switch (region.boundary) { - case L: { + case (Boundary::L): { blockage.setXMax(blockage.xMin() + blockage_depth); break; } - case R: { + case (Boundary::R): { blockage.setXMin(blockage.xMax() - blockage_depth); break; } - case B: { + case (Boundary::B): { blockage.setYMax(blockage.yMin() + blockage_depth); break; } - case T: { + case (Boundary::T): { blockage.setYMin(blockage.yMax() - blockage_depth); break; } - case NONE: { - logger_->critical(MPL, - 48, - "Attempting to create pin access blockage for cluster " - "of unconstrained IOs!"); - } } macro_blockages_.push_back(blockage); @@ -2994,7 +2988,7 @@ std::vector HierRTLMP::subtractOverlapRegion( bool HierRTLMP::isVertical(Boundary boundary) const { - return boundary == L || boundary == R; + return boundary == Boundary::L || boundary == Boundary::R; } odb::Rect HierRTLMP::getRect(Boundary boundary) const @@ -3002,21 +2996,19 @@ odb::Rect HierRTLMP::getRect(Boundary boundary) const odb::Rect boundary_rect = block_->getDieArea(); switch (boundary) { - case NONE: - break; - case L: { + case (Boundary::L): { boundary_rect.set_xhi(boundary_rect.xMin()); break; } - case R: { + case (Boundary::R): { boundary_rect.set_xlo(boundary_rect.xMax()); break; } - case T: { + case (Boundary::T): { boundary_rect.set_ylo(boundary_rect.yMax()); break; } - case B: { + case (Boundary::B): { boundary_rect.set_yhi(boundary_rect.yMin()); break; } @@ -3167,10 +3159,10 @@ std::map Pusher::getDistanceToCloseBoundaries( int smaller_hor_distance = 0; if (distance_to_left < distance_to_right) { - hor_boundary_to_push = L; + hor_boundary_to_push = Boundary::L; smaller_hor_distance = distance_to_left; } else { - hor_boundary_to_push = R; + hor_boundary_to_push = Boundary::R; smaller_hor_distance = distance_to_right; } @@ -3185,10 +3177,10 @@ std::map Pusher::getDistanceToCloseBoundaries( int smaller_ver_distance = 0; if (distance_to_bottom < distance_to_top) { - ver_boundary_to_push = B; + ver_boundary_to_push = Boundary::B; smaller_ver_distance = distance_to_bottom; } else { - ver_boundary_to_push = T; + ver_boundary_to_push = Boundary::T; smaller_ver_distance = distance_to_top; } @@ -3253,21 +3245,19 @@ void Pusher::moveMacroClusterBox(odb::Rect& cluster_box, const int distance) { switch (boundary) { - case NONE: - return; - case L: { + case (Boundary::L): { cluster_box.moveDelta(-distance, 0); break; } - case R: { + case (Boundary::R): { cluster_box.moveDelta(distance, 0); break; } - case T: { + case (Boundary::T): { cluster_box.moveDelta(0, distance); break; } - case B: { + case (Boundary::B): { cluster_box.moveDelta(0, -distance); break; } @@ -3279,21 +3269,19 @@ void Pusher::moveHardMacro(HardMacro* hard_macro, const int distance) { switch (boundary) { - case NONE: - return; - case L: { + case (Boundary::L): { hard_macro->setXDBU(hard_macro->getXDBU() - distance); break; } - case R: { + case (Boundary::R): { hard_macro->setXDBU(hard_macro->getXDBU() + distance); break; } - case T: { + case (Boundary::T): { hard_macro->setYDBU(hard_macro->getYDBU() + distance); break; } - case B: { + case (Boundary::B): { hard_macro->setYDBU(hard_macro->getYDBU() - distance); break; } diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index 9c7ff09ca8f..23ee613adc2 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -19,45 +19,38 @@ using ClusterToBoundaryRegionMap = std::map; using BoundaryRegionList = std::vector; // One of the edges of the die area. -enum Boundary +enum class Boundary { - NONE, B, L, T, R }; -inline std::string toString(const Boundary& pin_access) +inline std::string toString(const Boundary& boundary) { - switch (pin_access) { - case L: - return std::string("L"); - case T: - return std::string("T"); - case R: - return std::string("R"); - case B: - return std::string("B"); - default: - return std::string("NONE"); - } -} + std::string string; -inline Boundary opposite(const Boundary& pin_access) -{ - switch (pin_access) { - case L: - return R; - case T: - return B; - case R: - return L; - case B: - return T; - default: - return NONE; + switch (boundary) { + case (Boundary::L): { + string = 'L'; + break; + } + case (Boundary::T): { + string = 'T'; + break; + } + case (Boundary::R): { + string = 'R'; + break; + } + case (Boundary::B): { + string = 'B'; + break; + } } + + return string; } struct SACoreWeights @@ -95,7 +88,7 @@ struct BoundaryRegion } odb::Line line; - Boundary boundary; + Boundary boundary = Boundary::L; }; // Utility to help sorting width intervals. @@ -118,21 +111,20 @@ inline bool isAreaSmaller(const Tiling& tiling_a, const Tiling& tiling_b) inline Boundary getBoundary(odb::dbBlock* block, const odb::Rect& region) { const odb::Rect& die = block->getDieArea(); - Boundary boundary = NONE; + if (region.dx() == 0) { if (region.xMin() == die.xMin()) { - boundary = L; - } else { - boundary = R; - } - } else { - if (region.yMin() == die.yMin()) { - boundary = B; - } else { - boundary = T; + return Boundary::L; } + + return Boundary::R; } - return boundary; + + if (region.yMin() == die.yMin()) { + return Boundary::B; + } + + return Boundary::T; } inline odb::Rect lineToRect(const odb::Line line) @@ -153,21 +145,22 @@ inline odb::Line rectToLine(odb::dbBlock* block, odb::Line line; switch (getBoundary(block, rect)) { - case L: - return line = {rect.ll(), rect.ul()}; - case R: - return line = {rect.lr(), rect.ur()}; - case T: - return line = {rect.ul(), rect.ur()}; - case B: - return line = {rect.ll(), rect.lr()}; - case NONE: - logger->error(utl::MPL, - 61, - "Couldn't convert rect {} to line. The is region outside " - "of the die {} boundaries.", - rect, - block->getDieArea()); + case (Boundary::L): { + line = {rect.ll(), rect.ul()}; + break; + } + case (Boundary::R): { + line = {rect.lr(), rect.ur()}; + break; + } + case (Boundary::T): { + line = {rect.ul(), rect.ur()}; + break; + } + case (Boundary::B): { + line = {rect.ll(), rect.lr()}; + break; + } } return line; @@ -176,24 +169,25 @@ inline odb::Line rectToLine(odb::dbBlock* block, inline odb::Point computeNearestPointInRegion(const BoundaryRegion& region, const odb::Point& target) { - if (region.boundary == L || region.boundary == R) { - if (target.y() >= region.line.pt1().y()) { - return odb::Point(region.line.pt0().x(), region.line.pt1().y()); + const odb::Line& line = region.line; + if (region.boundary == Boundary::L || region.boundary == Boundary::R) { + if (target.y() >= line.pt1().y()) { + return odb::Point(line.pt0().x(), line.pt1().y()); } - if (target.y() <= region.line.pt0().y()) { - return odb::Point(region.line.pt0().x(), region.line.pt0().y()); + if (target.y() <= line.pt0().y()) { + return odb::Point(line.pt0().x(), line.pt0().y()); } - return odb::Point(region.line.pt0().x(), target.y()); + return odb::Point(line.pt0().x(), target.y()); } // Top or Bottom - if (target.x() >= region.line.pt1().x()) { - return odb::Point(region.line.pt1().x(), region.line.pt0().y()); + if (target.x() >= line.pt1().x()) { + return odb::Point(line.pt1().x(), line.pt0().y()); } - if (target.x() <= region.line.pt0().x()) { - return odb::Point(region.line.pt0().x(), region.line.pt0().y()); + if (target.x() <= line.pt0().x()) { + return odb::Point(line.pt0().x(), line.pt0().y()); } - return odb::Point(target.x(), region.line.pt0().y()); + return odb::Point(target.x(), line.pt0().y()); } // The distance in DBU from the source to the nearest point of the nearest From 5010d1e7d5e6bd4f2bf468b8d3c6ae1794970852 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 9 May 2025 12:29:42 -0300 Subject: [PATCH 32/34] mpl: renaming and more simplifications Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 6 ++--- src/mpl/src/util.h | 46 ++++++++++++-------------------------- 2 files changed, 17 insertions(+), 35 deletions(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index e81bd52a150..8f7a86e038d 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -934,10 +934,10 @@ void HierRTLMP::createPinAccessBlockages() void HierRTLMP::computePinAccessDepthLimits() { const Rect die = dbuToMicrons(block_->getDieArea()); - constexpr float max_depth_percentage = 0.20; + constexpr float max_depth_proportion = 0.20; - pin_access_depth_limits_.horizontal = max_depth_percentage * die.getWidth(); - pin_access_depth_limits_.vertical = max_depth_percentage * die.getHeight(); + pin_access_depth_limits_.horizontal = max_depth_proportion * die.getWidth(); + pin_access_depth_limits_.vertical = max_depth_proportion * die.getHeight(); } bool HierRTLMP::treeHasOnlyUnconstrainedIOs() const diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h index 23ee613adc2..ddfb6b5b86f 100644 --- a/src/mpl/src/util.h +++ b/src/mpl/src/util.h @@ -143,27 +143,7 @@ inline odb::Line rectToLine(odb::dbBlock* block, rect); } - odb::Line line; - switch (getBoundary(block, rect)) { - case (Boundary::L): { - line = {rect.ll(), rect.ul()}; - break; - } - case (Boundary::R): { - line = {rect.lr(), rect.ur()}; - break; - } - case (Boundary::T): { - line = {rect.ul(), rect.ur()}; - break; - } - case (Boundary::B): { - line = {rect.ll(), rect.lr()}; - break; - } - } - - return line; + return {rect.ll(), rect.ur()}; } inline odb::Point computeNearestPointInRegion(const BoundaryRegion& region, @@ -172,22 +152,22 @@ inline odb::Point computeNearestPointInRegion(const BoundaryRegion& region, const odb::Line& line = region.line; if (region.boundary == Boundary::L || region.boundary == Boundary::R) { if (target.y() >= line.pt1().y()) { - return odb::Point(line.pt0().x(), line.pt1().y()); + return line.pt1(); } if (target.y() <= line.pt0().y()) { - return odb::Point(line.pt0().x(), line.pt0().y()); + return line.pt0(); } - return odb::Point(line.pt0().x(), target.y()); + return {line.pt0().x(), target.y()}; } // Top or Bottom if (target.x() >= line.pt1().x()) { - return odb::Point(line.pt1().x(), line.pt0().y()); + return line.pt1(); } if (target.x() <= line.pt0().x()) { - return odb::Point(line.pt0().x(), line.pt0().y()); + return line.pt0(); } - return odb::Point(target.x(), line.pt0().y()); + return {target.x(), line.pt0().y()}; } // The distance in DBU from the source to the nearest point of the nearest @@ -197,12 +177,14 @@ inline double computeDistToNearestRegion( const std::vector& regions, odb::Point* nearest_point) { - double smallest_distance = std::numeric_limits::max(); + int64_t smallest_distance = std::numeric_limits::max(); + for (const BoundaryRegion& region : regions) { - odb::Point nearest_point_in_region + const odb::Point nearest_point_in_region = computeNearestPointInRegion(region, source); - const double dist_to_nearest_point = std::sqrt( - odb::Point::squaredDistance(source, nearest_point_in_region)); + const int64_t dist_to_nearest_point + = odb::Point::squaredDistance(source, nearest_point_in_region); + if (dist_to_nearest_point < smallest_distance) { smallest_distance = dist_to_nearest_point; if (nearest_point) { @@ -211,7 +193,7 @@ inline double computeDistToNearestRegion( } } - return smallest_distance; + return std::sqrt(smallest_distance); } } // namespace mpl From ece7ecc96f0fb68ec64370f8804577f2b7281256 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Fri, 9 May 2025 12:45:00 -0300 Subject: [PATCH 33/34] mpl: 1) Avoid double-negative checking; 2) Add tests to BUILD. Signed-off-by: Arthur Koucher --- src/mpl/src/hier_rtlmp.cpp | 11 +++++------ src/mpl/src/hier_rtlmp.h | 2 +- src/mpl/test/BUILD | 6 ++++++ 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 8f7a86e038d..6aea4ed86ff 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -874,7 +874,7 @@ void HierRTLMP::setTightPackingTilings(Cluster* macro_array) void HierRTLMP::searchForAvailableRegionsForPins() { - if (!treeHasOnlyUnconstrainedIOs()) { + if (treeHasConstrainedIOs()) { return; } @@ -904,8 +904,7 @@ void HierRTLMP::createPinAccessBlockages() return; } - if (treeHasOnlyUnconstrainedIOs() - && block_->getBlockedRegionsForPins().empty()) { + if (!treeHasConstrainedIOs() && block_->getBlockedRegionsForPins().empty()) { // If there are no constraints at all, we give freedom to SA so it // doesn't have to deal with pin access blockages across the entire // extension of all edges of the die area. This should help SA not @@ -940,15 +939,15 @@ void HierRTLMP::computePinAccessDepthLimits() pin_access_depth_limits_.vertical = max_depth_proportion * die.getHeight(); } -bool HierRTLMP::treeHasOnlyUnconstrainedIOs() const +bool HierRTLMP::treeHasConstrainedIOs() const { std::vector io_clusters = getClustersOfUnplacedIOPins(); for (Cluster* io_cluster : io_clusters) { if (!io_cluster->isClusterOfUnconstrainedIOPins()) { - return false; + return true; } } - return true; + return false; } void HierRTLMP::createBlockagesForAvailableRegions() diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index f37a7582969..54764f9adf8 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -155,7 +155,7 @@ class HierRTLMP BoundaryToRegionsMap& boundary_to_blocked_regions) const; void createPinAccessBlockages(); void computePinAccessDepthLimits(); - bool treeHasOnlyUnconstrainedIOs() const; + bool treeHasConstrainedIOs() const; std::vector getClustersOfUnplacedIOPins() const; void createPinAccessBlockage(const BoundaryRegion& region, float depth); float computePinAccessBaseDepth(double io_span) const; diff --git a/src/mpl/test/BUILD b/src/mpl/test/BUILD index edea651bad1..62bc209c1dc 100644 --- a/src/mpl/test/BUILD +++ b/src/mpl/test/BUILD @@ -10,6 +10,12 @@ COMPULSORY_TESTS = [ "guides2", "io_constraints1", "io_constraints2", + "io_constraints3", + "io_constraints4", + "io_constraints5", + "io_constraints6", + "io_constraints7", + "io_constraints8", "io_pads1", "orientation_improve1", "orientation_improve2", From feae30b29d7dba0068b468a7e39ca549a45529c6 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Tue, 20 May 2025 12:07:17 -0300 Subject: [PATCH 34/34] mpl: 1) Improve naming; 2) Fix outline offset done in available regions for unconstrained pins. Signed-off-by: Arthur Koucher --- src/mpl/src/MplObserver.h | 5 ++++- src/mpl/src/SimulatedAnnealingCore.cpp | 15 +++++++------- src/mpl/src/SimulatedAnnealingCore.h | 5 +++-- src/mpl/src/clusterEngine.h | 2 +- src/mpl/src/graphics.cpp | 8 +++++--- src/mpl/src/graphics.h | 5 +++-- src/mpl/src/hier_rtlmp.cpp | 27 +++++++++++++++----------- src/mpl/src/hier_rtlmp.h | 2 +- 8 files changed, 41 insertions(+), 28 deletions(-) diff --git a/src/mpl/src/MplObserver.h b/src/mpl/src/MplObserver.h index 8405e0d93c5..9e4eedb7e0e 100644 --- a/src/mpl/src/MplObserver.h +++ b/src/mpl/src/MplObserver.h @@ -62,7 +62,10 @@ class MplObserver const std::vector& blocked_regions_for_pins) { } - virtual void setAvailableRegionsForPins(const BoundaryRegionList& regions) {} + virtual void setAvailableRegionsForUnconstrainedPins( + const BoundaryRegionList& regions) + { + } virtual void setAreaPenalty(const PenaltyData& penalty) {} virtual void setBoundaryPenalty(const PenaltyData& penalty) {} diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index 4c45c6cfd7c..dd63d37b8be 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -61,7 +61,8 @@ SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, macros_ = macros; setDieArea(tree->die_area); - setAvailableRegionForPins(tree->available_regions_for_pins); + setAvailableRegionsForUnconstrainedPins( + tree->available_regions_for_unconstrained_pins); io_cluster_to_constraint_ = tree->io_cluster_to_constraint; } @@ -75,14 +76,14 @@ void SimulatedAnnealingCore::setDieArea(const Rect& die_area) } template -void SimulatedAnnealingCore::setAvailableRegionForPins( +void SimulatedAnnealingCore::setAvailableRegionsForUnconstrainedPins( const BoundaryRegionList& regions) { - available_regions_for_pins_ = regions; + available_regions_for_unconstrained_pins_ = regions; - for (BoundaryRegion& region : available_regions_for_pins_) { + for (BoundaryRegion& region : available_regions_for_unconstrained_pins_) { region.line.addX(-block_->micronsToDbu(outline_.xMin())); - region.line.addY(-block_->micronsToDbu(outline_.xMin())); + region.line.addY(-block_->micronsToDbu(outline_.yMin())); } } @@ -318,7 +319,7 @@ void SimulatedAnnealingCore::computeWLForClusterOfUnplacedIOPins( block_->micronsToDbu(macro.getPinY())); double smallest_distance; if (unplaced_ios.getCluster()->isClusterOfUnconstrainedIOPins()) { - if (available_regions_for_pins_.empty()) { + if (available_regions_for_unconstrained_pins_.empty()) { logger_->critical( utl::MPL, 47, @@ -326,7 +327,7 @@ void SimulatedAnnealingCore::computeWLForClusterOfUnplacedIOPins( } smallest_distance = computeDistToNearestRegion( - macro_location, available_regions_for_pins_, nullptr); + macro_location, available_regions_for_unconstrained_pins_, nullptr); } else { Cluster* cluster = unplaced_ios.getCluster(); const BoundaryRegion& constraint = io_cluster_to_constraint_.at(cluster); diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 3e897f58fa8..1f14018cb81 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -98,7 +98,8 @@ class SimulatedAnnealingCore void fastSA(); - void setAvailableRegionForPins(const BoundaryRegionList& regions); + void setAvailableRegionsForUnconstrainedPins( + const BoundaryRegionList& regions); void initSequencePair(); void setDieArea(const Rect& die_area); void updateBestValidResult(); @@ -137,7 +138,7 @@ class SimulatedAnnealingCore Rect outline_; Rect die_area_; // Offset to the current outline. - BoundaryRegionList available_regions_for_pins_; + BoundaryRegionList available_regions_for_unconstrained_pins_; ClusterToBoundaryRegionMap io_cluster_to_constraint_; // Number of macros that will actually be part of the sequence pair diff --git a/src/mpl/src/clusterEngine.h b/src/mpl/src/clusterEngine.h index 320788c2d85..d7d58f11383 100644 --- a/src/mpl/src/clusterEngine.h +++ b/src/mpl/src/clusterEngine.h @@ -90,7 +90,7 @@ struct PhysicalHierarchy std::unique_ptr root; PhysicalHierarchyMaps maps; - BoundaryRegionList available_regions_for_pins; + BoundaryRegionList available_regions_for_unconstrained_pins; ClusterToBoundaryRegionMap io_cluster_to_constraint; float halo_width{0.0f}; diff --git a/src/mpl/src/graphics.cpp b/src/mpl/src/graphics.cpp index aa36b5db864..37b0e256863 100644 --- a/src/mpl/src/graphics.cpp +++ b/src/mpl/src/graphics.cpp @@ -593,7 +593,8 @@ void Graphics::drawDistToRegion(gui::Painter& painter, odb::Point to; if (io.getCluster()->isClusterOfUnconstrainedIOPins()) { - computeDistToNearestRegion(from, available_regions_for_pins_, &to); + computeDistToNearestRegion( + from, available_regions_for_unconstrained_pins_, &to); } else { computeDistToNearestRegion( from, {io_cluster_to_constraint_.at(io.getCluster())}, &to); @@ -719,9 +720,10 @@ void Graphics::setBlockedRegionsForPins( blocked_regions_for_pins_ = blocked_regions_for_pins; } -void Graphics::setAvailableRegionsForPins(const BoundaryRegionList& regions) +void Graphics::setAvailableRegionsForUnconstrainedPins( + const BoundaryRegionList& regions) { - available_regions_for_pins_ = regions; + available_regions_for_unconstrained_pins_ = regions; } void Graphics::eraseDrawing() diff --git a/src/mpl/src/graphics.h b/src/mpl/src/graphics.h index c9ba85ad5ef..230c2b19a15 100644 --- a/src/mpl/src/graphics.h +++ b/src/mpl/src/graphics.h @@ -65,7 +65,8 @@ class Graphics : public gui::Renderer, public MplObserver const ClusterToBoundaryRegionMap& io_cluster_to_constraint) override; void setBlockedRegionsForPins( const std::vector& blocked_regions_for_pins) override; - void setAvailableRegionsForPins(const BoundaryRegionList& regions) override; + void setAvailableRegionsForUnconstrainedPins( + const BoundaryRegionList& regions) override; void eraseDrawing() override; @@ -108,7 +109,7 @@ class Graphics : public gui::Renderer, public MplObserver int target_cluster_id_{-1}; std::vector> outlines_; std::vector blocked_regions_for_pins_; - BoundaryRegionList available_regions_for_pins_; + BoundaryRegionList available_regions_for_unconstrained_pins_; ClusterToBoundaryRegionMap io_cluster_to_constraint_; // In Soft SA, we're shaping/placing the children of a certain parent, diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 6aea4ed86ff..a1ef8cb115d 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -317,7 +317,7 @@ void HierRTLMP::runCoarseShaping() calculateChildrenTilings(tree_->root.get()); - searchForAvailableRegionsForPins(); + searchAvailableRegionsForUnconstrainedPins(); createPinAccessBlockages(); setPlacementBlockages(); } @@ -872,7 +872,7 @@ void HierRTLMP::setTightPackingTilings(Cluster* macro_array) macro_array->setTilings(tight_packing_tilings); } -void HierRTLMP::searchForAvailableRegionsForPins() +void HierRTLMP::searchAvailableRegionsForUnconstrainedPins() { if (treeHasConstrainedIOs()) { return; @@ -886,15 +886,17 @@ void HierRTLMP::searchForAvailableRegionsForPins() std::vector available_regions = computeAvailableRegions(boundary_to_blocked_regions); - tree_->available_regions_for_pins.reserve(available_regions.size()); + tree_->available_regions_for_unconstrained_pins.reserve( + available_regions.size()); for (const odb::Rect& region : available_regions) { - tree_->available_regions_for_pins.emplace_back( + tree_->available_regions_for_unconstrained_pins.emplace_back( rectToLine(block_, region, logger_), getBoundary(block_, region)); } if (graphics_) { graphics_->setBlockedRegionsForPins(blocked_regions_for_pins); - graphics_->setAvailableRegionsForPins(tree_->available_regions_for_pins); + graphics_->setAvailableRegionsForUnconstrainedPins( + tree_->available_regions_for_unconstrained_pins); } } @@ -923,7 +925,7 @@ void HierRTLMP::createPinAccessBlockages() computePinAccessDepthLimits(); - if (!tree_->available_regions_for_pins.empty()) { + if (!tree_->available_regions_for_unconstrained_pins.empty()) { createBlockagesForAvailableRegions(); } else { createBlockagesForConstraintRegions(); @@ -953,14 +955,16 @@ bool HierRTLMP::treeHasConstrainedIOs() const void HierRTLMP::createBlockagesForAvailableRegions() { double io_span = 0.0; - for (const BoundaryRegion& region : tree_->available_regions_for_pins) { + for (const BoundaryRegion& region : + tree_->available_regions_for_unconstrained_pins) { io_span += std::sqrt( odb::Point::squaredDistance(region.line.pt0(), region.line.pt1())); } const float depth = computePinAccessBaseDepth(block_->dbuToMicrons(io_span)); - for (const BoundaryRegion region : tree_->available_regions_for_pins) { + for (const BoundaryRegion region : + tree_->available_regions_for_unconstrained_pins) { createPinAccessBlockage(region, depth); } } @@ -2754,9 +2758,10 @@ float HierRTLMP::calculateRealMacroWirelength(odb::dbInst* macro) computeDistToNearestRegion( macro_pin->getBBox().center(), {constraint}, &nearest_point); } else { - computeDistToNearestRegion(macro_pin->getBBox().center(), - tree_->available_regions_for_pins, - &nearest_point); + computeDistToNearestRegion( + macro_pin->getBBox().center(), + tree_->available_regions_for_unconstrained_pins, + &nearest_point); } odb::Rect point_rect(nearest_point, nearest_point); net_box.merge(point_rect); diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index 54764f9adf8..1d350cde183 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -148,7 +148,7 @@ class HierRTLMP void calculateMacroTilings(Cluster* cluster); IntervalList computeWidthIntervals(const TilingList& tilings); void setTightPackingTilings(Cluster* macro_array); - void searchForAvailableRegionsForPins(); + void searchAvailableRegionsForUnconstrainedPins(); BoundaryToRegionsMap getBoundaryToBlockedRegionsMap( const std::vector& blocked_regions_for_pins) const; std::vector computeAvailableRegions(