Merge remote-tracking branch 'upstream/master'

Author: maliberty

CMakeLists.txt

@@ -202,7 +202,6 @@ set(STA_SOURCE
   search/TagGroup.cc
   search/VertexVisitor.cc
   search/VisitPathEnds.cc
-  search/VisitPathGroupVertices.cc
   search/WorstSlack.cc
 
   spice/WritePathSpice.cc

doc/ApiChanges.txt

@@ -50,6 +50,9 @@ The following classes now return const objects.
   Transition
   TimingRole
 
+Liberty PgPorts are now LibertyPorts with additional member functions for
+liberty pg_pins.
+
 Release 2.6.1 2025/03/??
 -------------------------
 

doc/ChangeLog.txt

@@ -17,6 +17,8 @@ to remove paths through identical pins and rise/fall edges.
 
   report_checks [-unique_edges_to_endpoint]
 
+Instances now have pins for verilog netlist power/ground connections,
+
 Release 2.6.1 2025/03/30
 -------------------------
 

include/sta/Liberty.hh

@@ -43,7 +43,6 @@ class WriteTimingModel;
 class LibertyCellIterator;
 class LibertyCellPortIterator;
 class LibertyCellPortBitIterator;
-class LibertyCellPgPortIterator;
 class LibertyPortMemberIterator;
 class ModeValueDef;
 class TestCell;
@@ -56,7 +55,6 @@ class LibertyReader;
 class OcvDerate;
 class TimingArcAttrs;
 class InternalPowerAttrs;
-class LibertyPgPort;
 class StaState;
 class Corner;
 class Corners;
@@ -90,7 +88,6 @@ typedef Vector<LatchEnable*> LatchEnableSeq;
 typedef Map<const char *, OcvDerate*, CharPtrLess> OcvDerateMap;
 typedef Vector<InternalPowerAttrs*> InternalPowerAttrsSeq;
 typedef Map<std::string, float> SupplyVoltageMap;
-typedef Map<std::string, LibertyPgPort*> LibertyPgPortMap;
 typedef Map<std::string, DriverWaveform*> DriverWaveformMap;
 typedef Vector<DcalcAnalysisPt*> DcalcAnalysisPtSeq;
 
@@ -100,6 +97,12 @@ enum class DelayModelType { cmos_linear, cmos_pwl, cmos2, table, polynomial, dcm
 
 enum class ScanSignalType { enable, enable_inverted, clock, clock_a, clock_b,
                             input, input_inverted, output, output_inverted, none };
+enum class PwrGndType { none,
+			primary_power, primary_ground,
+			backup_power, backup_ground,
+			internal_power, internal_ground,
+			nwell, pwell,
+			deepnwell, deeppwell};
 
 enum class ScaleFactorPvt { process, volt, temp, unknown };
 constexpr int scale_factor_pvt_count = int(ScaleFactorPvt::unknown) + 1;
@@ -423,8 +426,6 @@ public:
   LibertyPort *findLibertyPort(const char *name) const;
   LibertyPortSeq findLibertyPortsMatching(PatternMatch *pattern) const;
   bool hasInternalPorts() const { return has_internal_ports_; }
-  LibertyPgPort *findPgPort(const char *name) const;
-  size_t pgPortCount() const { return pg_port_map_.size(); }
   ScaleFactors *scaleFactors() const { return scale_factors_; }
   void setScaleFactors(ScaleFactors *scale_factors);
   ModeDef *makeModeDef(const char *name);
@@ -533,7 +534,6 @@ public:
   void setOcvArcDepth(float depth);
   void setOcvDerate(OcvDerate *derate);
   void addOcvDerate(OcvDerate *derate);
-  void addPgPort(LibertyPgPort *pg_port);
   void setTestCell(TestCell *test);
   void setHasInferedRegTimingArcs(bool infered);
   void setIsDisabledConstraint(bool is_disabled);
@@ -643,7 +643,6 @@ protected:
   Vector<LibertyCell*> corner_cells_;
   float leakage_power_;
   bool leakage_power_exists_;
-  LibertyPgPortMap pg_port_map_;
   bool has_internal_ports_;
   std::atomic<bool> have_voltage_waveforms_;
   std::mutex waveform_lock_;
@@ -653,7 +652,6 @@ protected:
 private:
   friend class LibertyLibrary;
   friend class LibertyCellPortIterator;
-  friend class LibertyCellPgPortIterator;
   friend class LibertyPort;
   friend class LibertyBuilder;
 };
@@ -681,17 +679,6 @@ private:
   ConcreteCellPortBitIterator *iter_;
 };
 
-class LibertyCellPgPortIterator : public Iterator<LibertyPgPort*>
-{
-public:
-  LibertyCellPgPortIterator(const LibertyCell *cell);
-  bool hasNext();
-  LibertyPgPort *next();
-
-private:
-  LibertyPgPortMap::Iterator iter_;
-};
-
 ////////////////////////////////////////////////////////////////
 
 class LibertyPort : public ConcretePort
@@ -704,6 +691,16 @@ public:
   LibertyPort *bundlePort() const;
   BusDcl *busDcl() const { return bus_dcl_; }
   void setDirection(PortDirection *dir);
+
+  ////////////////////////////////////////////////////////////////
+  // pg_pin functions
+  bool isPwrGnd() const;
+  PwrGndType pwrGndType() const { return pwr_gnd_type_; }
+  void setPwrGndType(PwrGndType type);
+  const char *voltageName() const { return voltage_name_.c_str(); }
+  void setVoltageName(const char *voltage_name);
+  ////////////////////////////////////////////////////////////////
+
   ScanSignalType scanSignalType() const { return scan_signal_type_; }
   void setScanSignalType(ScanSignalType type);
   void fanoutLoad(// Return values.
@@ -887,8 +884,10 @@ protected:
 
   LibertyCell *liberty_cell_;
   BusDcl *bus_dcl_;
-  FuncExpr *function_;
+  PwrGndType pwr_gnd_type_;
+  std::string voltage_name_;
   ScanSignalType scan_signal_type_;
+  FuncExpr *function_;
   FuncExpr *tristate_enable_;
   ScaledPortMap *scaled_ports_;
   RiseFallMinMax capacitance_;
@@ -1136,37 +1135,13 @@ private:
   TablePtr derate_[RiseFall::index_count][EarlyLate::index_count][path_type_count];
 };
 
-// Power/ground port.
-class LibertyPgPort
-{
-public:
-  enum PgType { unknown,
-		primary_power, primary_ground,
-		backup_power, backup_ground,
-		internal_power, internal_ground,
-		nwell, pwell,
-		deepnwell, deeppwell};
-  LibertyPgPort(const char *name,
-		LibertyCell *cell);
-  const char *name() const { return name_.c_str(); }
-  LibertyCell *cell() const { return cell_; }
-  PgType pgType() const { return pg_type_; }
-  void setPgType(PgType type);
-  const char *voltageName() const { return voltage_name_.c_str(); }
-  void setVoltageName(const char *voltage_name);
-  static bool equiv(const LibertyPgPort *port1,
-		    const LibertyPgPort *port2);
-
-private:
-  std::string name_;
-  PgType pg_type_;
-  std::string voltage_name_;
-  LibertyCell *cell_;
-};
-
 std::string
 portLibertyToSta(const char *port_name);
 const char *
 scanSignalTypeName(ScanSignalType scan_type);
+const char *
+pwrGndTypeName(PwrGndType pwr_gnd_type);
+PwrGndType
+findPwrGndType(const char *pg_name);
 
 } // namespace

include/sta/Sdc.hh

@@ -136,15 +136,15 @@ typedef Set<InputDelay*> InputDelaySet;
 typedef Map<const Pin*, InputDelaySet*, PinIdLess> InputDelaysPinMap;
 typedef Set<OutputDelay*> OutputDelaySet;
 typedef Map<const Pin*,OutputDelaySet*, PinIdLess> OutputDelaysPinMap;
-typedef UnorderedMap<const Pin*,ExceptionPathSet*> PinExceptionsMap;
-typedef Map<const Clock*,ExceptionPathSet*> ClockExceptionsMap;
-typedef Map<const Instance*,ExceptionPathSet*> InstanceExceptionsMap;
-typedef Map<const Net*,ExceptionPathSet*> NetExceptionsMap;
-typedef UnorderedMap<EdgePins, ExceptionPathSet*,
+typedef UnorderedMap<const Pin*,ExceptionPathSet> PinExceptionsMap;
+typedef UnorderedMap<const Clock*,ExceptionPathSet> ClockExceptionsMap;
+typedef UnorderedMap<const Instance*,ExceptionPathSet> InstanceExceptionsMap;
+typedef UnorderedMap<const Net*,ExceptionPathSet> NetExceptionsMap;
+typedef UnorderedMap<EdgePins, ExceptionPathSet,
 		     PinPairHash, PinPairEqual> EdgeExceptionsMap;
 typedef Vector<ExceptionThru*> ExceptionThruSeq;
 typedef Map<const Port*,InputDrive*> InputDriveMap;
-typedef Map<size_t, ExceptionPathSet*, std::less<size_t> > ExceptionPathPtHash;
+typedef Map<size_t, ExceptionPathSet, std::less<size_t>> ExceptionPathPtHash;
 typedef Set<ClockLatency*, ClockLatencyLess> ClockLatencies;
 typedef Map<const Pin*, ClockUncertainties*> PinClockUncertaintyMap;
 typedef Set<InterClockUncertainty*, InterClockUncertaintyLess> InterClockUncertaintySet;
@@ -1018,7 +1018,7 @@ public:
   const PinSet &pathDelayInternalFrom() const;
   bool isPathDelayInternalTo(const Pin *pin) const;
   bool isPathDelayInternalToBreak(const Pin *pin) const;
-  ExceptionPathSet *exceptions() { return &exceptions_; }
+  ExceptionPathSet &exceptions() { return exceptions_; }
   void deleteExceptions();
   void deleteException(ExceptionPath *exception);
   void recordException(ExceptionPath *exception);
@@ -1043,7 +1043,6 @@ protected:
   void removeLibertyAnnotations();
   void deleteExceptionsReferencing(Clock *clk);
   void deleteClkPinMappings(Clock *clk);
-  void deleteExceptionPtHashMapSets(ExceptionPathPtHash &map);
   void makeClkPinMappings(Clock *clk);
   void deletePinClocks(Clock *defining_clk,
                        PinSet *pins);

include/sta/SdcClass.hh

@@ -95,7 +95,7 @@ typedef Set<LibertyPortPair, LibertyPortPairLess> LibertyPortPairSet;
 typedef Map<const Instance*, DisabledInstancePorts*> DisabledInstancePortsMap;
 typedef Map<LibertyCell*, DisabledCellPorts*> DisabledCellPortsMap;
 typedef MinMaxValues<float> ClockUncertainties;
-typedef Set<ExceptionPath*> ExceptionPathSet;
+typedef std::set<ExceptionPath*> ExceptionPathSet;
 typedef PinPair EdgePins;
 typedef PinPairSet EdgePinsSet;
 typedef Map<const Pin*, LogicValue> LogicValueMap;

include/sta/Sta.hh

@@ -907,9 +907,6 @@ public:
   PinSet endpointPins();
   VertexSet *endpoints();
   int endpointViolationCount(const MinMax *min_max);
-  // Find the fanin vertices for a group path.
-  // Vertices in the clock network are NOT included.
-  PinSet findGroupPathPins(const char *group_path_name);
   // Find all required times after updateTiming().
   void findRequireds();
   std::string reportDelayCalc(Edge *edge,

liberty/EquivCells.cc

@@ -67,17 +67,9 @@ static unsigned
 hashFuncExpr(const FuncExpr *expr);
 static unsigned
 hashPort(const LibertyPort *port);
-static unsigned
-hashCellPgPorts(const LibertyCell *cell);
-static unsigned
-hashPgPort(const LibertyPgPort *port);
 static bool
 cellHasFuncs(const LibertyCell *cell);
 
-static bool
-equivCellPgPorts(const LibertyCell *cell1,
-                 const LibertyCell *cell2);
-
 static float
 cellDriveResistance(const LibertyCell *cell)
 {
@@ -201,7 +193,6 @@ static unsigned
 hashCell(const LibertyCell *cell)
 {
   return hashCellPorts(cell)
-    + hashCellPgPorts(cell)
     + hashCellSequentials(cell);
 }
 
@@ -226,25 +217,6 @@ hashPort(const LibertyPort *port)
     + port->direction()->index() * 5;
 }
 
-static unsigned
-hashCellPgPorts(const LibertyCell *cell)
-{
-  unsigned hash = 0;
-  LibertyCellPgPortIterator port_iter(cell);
-  while (port_iter.hasNext()) {
-    LibertyPgPort *port = port_iter.next();
-    hash += hashPgPort(port);
-  }
-  return hash;
-}
-
-static unsigned
-hashPgPort(const LibertyPgPort *port)
-{
-  return hashString(port->name()) * 3
-    + static_cast<int>(port->pgType()) * 5;
-}
-
 static unsigned
 hashCellSequentials(const LibertyCell *cell)
 {
@@ -333,7 +305,6 @@ equivCells(const LibertyCell *cell1,
 {
   return equivCellPorts(cell1, cell2)
     && equivCellFuncs(cell1, cell2)
-    && equivCellPgPorts(cell1, cell2)
     && equivCellSequentials(cell1, cell2)
     && equivCellStatetables(cell1, cell2)
     // Reqwuire timing arc equivalence if there are no functions.
@@ -347,7 +318,6 @@ equivCellsArcs(const LibertyCell *cell1,
 {
   return equivCellPorts(cell1, cell2)
     && equivCellFuncs(cell1, cell2)
-    && equivCellPgPorts(cell1, cell2)
     && equivCellSequentials(cell1, cell2)
     && equivCellStatetables(cell1, cell2)
     // Reqwuire timing arc equivalence if there are no functions.
@@ -403,25 +373,6 @@ equivCellPorts(const LibertyCell *cell1,
   }
 }
 
-static bool
-equivCellPgPorts(const LibertyCell *cell1,
-                 const LibertyCell *cell2)
-{
-  if (cell1->pgPortCount() != cell2->pgPortCount())
-    return false;
-  else {
-    LibertyCellPgPortIterator port_iter1(cell1);
-    while (port_iter1.hasNext()) {
-      LibertyPgPort *port1 = port_iter1.next();
-      const char* name = port1->name();
-      LibertyPgPort *port2 = cell2->findPgPort(name);
-      if (!(port2 && LibertyPgPort::equiv(port1, port2)))
-        return false;
-    }
-    return true;
-  }
-}
-
 bool
 equivCellSequentials(const LibertyCell *cell1,
 		     const LibertyCell *cell2)