@@ -489,13 +489,16 @@ PropActivityVisitor::visit(Vertex *vertex)
489489 }
490490 if (network_->isDriver (pin)) {
491491 LibertyPort *port = network_->libertyPort (pin);
492- if (port) {
493- LibertyCell *test_cell = port->libertyCell ()->testCell ();
494- if (test_cell)
495- port = test_cell->findLibertyPort (port->name ());
496- }
497492 if (port) {
498493 FuncExpr *func = port->function ();
494+ if (func == nullptr ) {
495+ LibertyCell *test_cell = port->libertyCell ()->testCell ();
496+ if (test_cell) {
497+ port = test_cell->findLibertyPort (port->name ());
498+ if (port)
499+ func = port->function ();
500+ }
501+ }
499502 if (func) {
500503 PwrActivity activity = power_->evalActivity (func, inst);
501504 changed = setActivityCheck (pin, activity);
@@ -777,10 +780,24 @@ Power::seedRegOutputActivities(const Instance *inst,
777780 BfsFwdIterator &bfs)
778781{
779782 LibertyCell *cell = network_->libertyCell (inst);
780- LibertyCell *test_cell = cell->testCell ();
781- const SequentialSeq &seqs = test_cell
782- ? test_cell->sequentials ()
783- : cell->sequentials ();
783+ const SequentialSeq &seqs = cell->sequentials ();
784+ if (!seqs.empty ())
785+ seedRegOutputActivities (inst, nullptr , seqs, bfs);
786+ else {
787+ LibertyCell *test_cell = cell->testCell ();
788+ if (test_cell) {
789+ const SequentialSeq &seqs = test_cell->sequentials ();
790+ seedRegOutputActivities (inst, test_cell, seqs, bfs);
791+ }
792+ }
793+ }
794+
795+ void
796+ Power::seedRegOutputActivities (const Instance *inst,
797+ const LibertyCell *test_cell,
798+ const SequentialSeq &seqs,
799+ BfsFwdIterator &bfs)
800+ {
784801 for (Sequential *seq : seqs) {
785802 seedRegOutputActivities (inst, seq, seq->output (), false );
786803 seedRegOutputActivities (inst, seq, seq->outputInv (), true );
@@ -791,7 +808,7 @@ Power::seedRegOutputActivities(const Instance *inst,
791808 Pin *pin = pin_iter->next ();
792809 LibertyPort *port = network_->libertyPort (pin);
793810 if (test_cell)
794- port = test_cell->findLibertyPort (port->name ());
811+ port = test_cell->findLibertyPort (port->name ());
795812 if (port) {
796813 FuncExpr *func = port->function ();
797814 Vertex *vertex = graph_->pinDrvrVertex (pin);
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