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Signed-off-by: Matt Liberty <[email protected]>
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verilog/VerilogReader.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -534,7 +534,7 @@ VerilogReader::makeModuleInst(const string *module_vname,
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// to reduce the memory footprint of the verilog parser.
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if (liberty_cell
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&& hasScalarNamedPortRefs(liberty_cell, pins)) {
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int port_count = network_->portBitCount(cell);
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int port_count = liberty_cell->portBitCount();
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StdStringSeq net_names(port_count);
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for (VerilogNet *vnet : *pins) {
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VerilogNetPortRefScalarNet *vpin =

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