Merge branch 'YosysHQ:main' into master

Author: eder-matheus

CHANGELOG

@@ -2,9 +2,25 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.53 .. Yosys 0.54-dev
+Yosys 0.54 .. Yosys 0.55-dev
 --------------------------
 
+Yosys 0.53 .. Yosys 0.54
+--------------------------
+ * New commands and options
+    - Added "-genlib" option to "abc_new" and "abc9_exe" passes.
+    - Added "-verbose" and "-quiet" options to "libcache" pass.
+    - Added "-no-sort" option to "write_aiger" pass.
+
+ * Various
+    - Added "muldiv_c" peepopt.
+    - Accept (and ignore) SystemVerilog unique/priority if.
+    - "read_verilog" copy inout ports in and out of functions/tasks.
+    - Enable single-bit vector wires in RTLIL.
+
+ * Xilinx support
+    - Single-port URAM mapping to support memories 2048 x 144b 
+
 Yosys 0.52 .. Yosys 0.53
 --------------------------
  * New commands and options

CODEOWNERS

@@ -20,6 +20,7 @@ passes/opt/opt_lut.cc          @whitequark
 passes/techmap/abc9*.cc        @eddiehung @Ravenslofty
 backends/aiger/xaiger.cc       @eddiehung
 docs/                          @KrystalDelusion
+docs/source/using_yosys/synthesis/abc.rst @KrystalDelusion @Ravenslofty
 .github/workflows/*.yml        @mmicko
 
 ## External Contributors

Makefile

@@ -160,7 +160,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.53+3
+YOSYS_VER := 0.54+0
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)
@@ -183,7 +183,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 53c22ab.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline db72ec3.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
@@ -204,7 +204,7 @@ endif
 include Makefile.conf
 endif
 
-PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
+PYTHON_EXECUTABLE ?= $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
 ifeq ($(ENABLE_PYOSYS),1)
 PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)"
 PYTHON_VERSION := $(shell $(PYTHON_EXECUTABLE) -c ""$(PYTHON_VERSION_TESTCODE)"")
@@ -455,6 +455,7 @@ endif
 
 ifeq ($(ENABLE_DEBUG),1)
 CXXFLAGS := -Og -DDEBUG $(filter-out $(OPT_LEVEL),$(CXXFLAGS))
+STRIP :=
 endif
 
 ifeq ($(ENABLE_ABC),1)
@@ -894,6 +895,7 @@ SH_TEST_DIRS += tests/bram
 SH_TEST_DIRS += tests/svinterfaces
 SH_TEST_DIRS += tests/xprop
 SH_TEST_DIRS += tests/select
+SH_TEST_DIRS += tests/peepopt
 SH_TEST_DIRS += tests/proc
 SH_TEST_DIRS += tests/blif
 SH_TEST_DIRS += tests/arch
@@ -982,20 +984,20 @@ install: $(TARGETS) $(EXTRA_TARGETS)
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR)
 	$(INSTALL_SUDO) cp $(filter-out libyosys.so,$(TARGETS)) $(DESTDIR)$(BINDIR)
 ifneq ($(filter $(PROGRAM_PREFIX)yosys,$(TARGETS)),)
-	$(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(BINDIR)/$(PROGRAM_PREFIX)yosys
+	if [ -n "$(STRIP)" ]; then $(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(BINDIR)/$(PROGRAM_PREFIX)yosys; fi
 endif
 ifneq ($(filter $(PROGRAM_PREFIX)yosys-abc,$(TARGETS)),)
-	$(INSTALL_SUDO) $(STRIP) $(DESTDIR)$(BINDIR)/$(PROGRAM_PREFIX)yosys-abc
+	if [ -n "$(STRIP)" ]; then $(INSTALL_SUDO) $(STRIP) $(DESTDIR)$(BINDIR)/$(PROGRAM_PREFIX)yosys-abc; fi
 endif
 ifneq ($(filter $(PROGRAM_PREFIX)yosys-filterlib,$(TARGETS)),)
-	$(INSTALL_SUDO) $(STRIP) $(DESTDIR)$(BINDIR)/$(PROGRAM_PREFIX)yosys-filterlib
+	if [ -n "$(STRIP)" ]; then $(INSTALL_SUDO) $(STRIP) $(DESTDIR)$(BINDIR)/$(PROGRAM_PREFIX)yosys-filterlib; fi
 endif
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(DATDIR)
 	$(INSTALL_SUDO) cp -r share/. $(DESTDIR)$(DATDIR)/.
 ifeq ($(ENABLE_LIBYOSYS),1)
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(LIBDIR)
 	$(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(LIBDIR)/
-	$(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(LIBDIR)/libyosys.so
+	if [ -n "$(STRIP)" ]; then $(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(LIBDIR)/libyosys.so; fi
 ifeq ($(ENABLE_PYOSYS),1)
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys
 	$(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/libyosys.so

backends/aiger/aiger.cc

@@ -132,7 +132,7 @@ struct AigerWriter
 		return a;
 	}
 
-	AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
+	AigerWriter(Module *module, bool no_sort, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
@@ -152,16 +152,12 @@ struct AigerWriter
 			if (wire->port_input)
 				sigmap.add(wire);
 
-		for (auto wire : module->wires())
-		{
-			if (wire->attributes.count(ID::init)) {
-				SigSpec initsig = sigmap(wire);
-				Const initval = wire->attributes.at(ID::init);
-				for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
-					if (initval[i] == State::S0 || initval[i] == State::S1)
-						init_map[initsig[i]] = initval[i] == State::S1;
-			}
-
+		// handle ports
+		// provided the input_bits and output_bits don't get sorted they
+		// will be returned in reverse order, so add them in reverse to
+		// match
+		for (auto riter = module->ports.rbegin(); riter != module->ports.rend(); ++riter) {
+			auto *wire = module->wire(*riter);
 			for (int i = 0; i < GetSize(wire); i++)
 			{
 				SigBit wirebit(wire, i);
@@ -175,9 +171,6 @@ struct AigerWriter
 					continue;
 				}
 
-				undriven_bits.insert(bit);
-				unused_bits.insert(bit);
-
 				if (wire->port_input)
 					input_bits.insert(bit);
 
@@ -187,6 +180,32 @@ struct AigerWriter
 					output_bits.insert(wirebit);
 				}
 			}
+		}
+
+		// handle wires
+		for (auto wire : module->wires())
+		{
+			if (wire->attributes.count(ID::init)) {
+				SigSpec initsig = sigmap(wire);
+				Const initval = wire->attributes.at(ID::init);
+				for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
+					if (initval[i] == State::S0 || initval[i] == State::S1)
+						init_map[initsig[i]] = initval[i] == State::S1;
+			}
+
+			for (int i = 0; i < GetSize(wire); i++)
+			{
+				SigBit wirebit(wire, i);
+				SigBit bit = sigmap(wirebit);
+
+				if (bit.wire == nullptr)
+					continue;
+				if (wire->port_input || wire->port_output)
+					continue;
+
+				undriven_bits.insert(bit);
+				unused_bits.insert(bit);
+			}
 
 			if (wire->width == 1) {
 				auto gclk_attr = wire->attributes.find(ID::replaced_by_gclk);
@@ -200,12 +219,6 @@ struct AigerWriter
 			}
 		}
 
-		for (auto bit : input_bits)
-			undriven_bits.erase(bit);
-
-		for (auto bit : output_bits)
-			unused_bits.erase(bit);
-
 		for (auto cell : module->cells())
 		{
 			if (cell->type == ID($_NOT_))
@@ -343,8 +356,11 @@ struct AigerWriter
 		}
 
 		init_map.sort();
-		input_bits.sort();
-		output_bits.sort();
+		// we are relying here on unsorted pools iterating last-in-first-out
+		if (!no_sort) {
+			input_bits.sort();
+			output_bits.sort();
+		}
 		not_map.sort();
 		ff_map.sort();
 		and_map.sort();
@@ -662,8 +678,7 @@ struct AigerWriter
 				f << std::endl;
 			}
 		}
-
-		f << stringf("c\nGenerated by %s\n", yosys_version_str);
+		f << stringf("c\nGenerated by %s\n", yosys_maybe_version());
 	}
 
 	void write_map(std::ostream &f, bool verbose_map, bool no_startoffset)
@@ -698,7 +713,7 @@ struct AigerWriter
 				}
 
 				if (wire->port_output) {
-					int o = ordered_outputs.at(sig[i]);
+					int o = ordered_outputs.at(SigSpec(wire, i));
 					output_lines[o] += stringf("output %d %d %s\n", o, index, log_id(wire));
 				}
 
@@ -746,7 +761,7 @@ struct AigerWriter
 	{
 		json.begin_object();
 		json.entry("version", "Yosys Witness Aiger map");
-		json.entry("gennerator", yosys_version_str);
+		json.entry("gennerator", yosys_maybe_version());
 
 		json.entry("latch_count", aig_l);
 		json.entry("input_count", aig_i);
@@ -902,6 +917,9 @@ struct AigerBackend : public Backend {
 		log("    -symbols\n");
 		log("        include a symbol table in the generated AIGER file\n");
 		log("\n");
+		log("    -no-sort\n");
+		log("        don't sort input/output ports\n");
+		log("\n");
 		log("    -map <filename>\n");
 		log("        write an extra file with port and latch symbols\n");
 		log("\n");
@@ -926,6 +944,7 @@ struct AigerBackend : public Backend {
 		bool zinit_mode = false;
 		bool miter_mode = false;
 		bool symbols_mode = false;
+		bool no_sort = false;
 		bool verbose_map = false;
 		bool imode = false;
 		bool omode = false;
@@ -956,6 +975,10 @@ struct AigerBackend : public Backend {
 				symbols_mode = true;
 				continue;
 			}
+			if (args[argidx] == "-no-sort") {
+				no_sort = true;
+				continue;
+			}
 			if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
 				map_filename = args[++argidx];
 				continue;
@@ -1009,7 +1032,7 @@ struct AigerBackend : public Backend {
 		if (!top_module->memories.empty())
 			log_error("Found unmapped memories in module %s: unmapped memories are not supported in AIGER backend!\n", log_id(top_module));
 
-		AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode);
+		AigerWriter writer(top_module, no_sort, zinit_mode, imode, omode, bmode, lmode);
 		writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
 
 		if (!map_filename.empty()) {

backends/aiger/xaiger.cc

@@ -671,7 +671,7 @@ struct XAigerWriter
 		//f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 		//f.write(buffer_str.data(), buffer_str.size());
 
-		f << stringf("Generated by %s\n", yosys_version_str);
+		f << stringf("Generated by %s\n", yosys_maybe_version());
 
 		design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
 		design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());

backends/blif/blif.cc

@@ -649,7 +649,7 @@ struct BlifBackend : public Backend {
 				if (module->get_bool_attribute(ID::top))
 					top_module_name = module->name.str();
 
-		*f << stringf("# Generated by %s\n", yosys_version_str);
+		*f << stringf("# Generated by %s\n", yosys_maybe_version());
 
 		std::vector<RTLIL::Module*> mod_list;
 

backends/btor/btor.cc

@@ -1499,7 +1499,7 @@ struct BtorWorker
 		{
 			ywmap_json.begin_object();
 			ywmap_json.entry("version", "Yosys Witness BTOR map");
-			ywmap_json.entry("generator", yosys_version_str);
+			ywmap_json.entry("generator", yosys_maybe_version());
 
 			ywmap_json.name("clocks");
 			ywmap_json.begin_array();
@@ -1613,7 +1613,7 @@ struct BtorBackend : public Backend {
 			log_cmd_error("No top module found.\n");
 
 		*f << stringf("; BTOR description generated by %s for module %s.\n",
-				yosys_version_str, log_id(topmod));
+				yosys_maybe_version(), log_id(topmod));
 
 		BtorWorker(*f, topmod, verbose, single_bad, cover_mode, print_internal_names, info_filename, ywmap_filename);
 

backends/cxxrtl/cxxrtl_backend.cc

@@ -2429,15 +2429,16 @@ struct CxxrtlWorker {
 			inc_indent();
 				for (auto wire : module->wires()) {
 					const auto &debug_wire_type = debug_wire_types[wire];
-					if (!wire->name.isPublic())
-						continue;
 					count_public_wires++;
 					switch (debug_wire_type.type) {
 						case WireType::BUFFERED:
 						case WireType::MEMBER: {
 							// Member wire
 							std::vector<std::string> flags;
 
+							if (!wire->name.isPublic())
+								flags.push_back("GENERATED");
+
 							if (wire->port_input && wire->port_output)
 								flags.push_back("INOUT");
 							else if (wire->port_output)

backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h

@@ -200,6 +200,10 @@ enum cxxrtl_flag {
 	// node, such as inputs and dangling wires.
 	CXXRTL_UNDRIVEN = 1 << 4,
 
+	// Generated correspond to netlist nodes that correspond to state with an internal name, that
+	// need to be saved, but wouldn't otherwise have a debug item generated.
+	CXXRTL_GENERATED = 1 << 5,
+
 	// More object flags may be added in the future, but the existing ones will never change.
 };
 

backends/cxxrtl/runtime/cxxrtl/cxxrtl.h

@@ -1294,6 +1294,7 @@ struct debug_item : ::cxxrtl_object {
 		DRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,
 		DRIVEN_COMB = CXXRTL_DRIVEN_COMB,
 		UNDRIVEN    = CXXRTL_UNDRIVEN,
+		GENERATED = CXXRTL_GENERATED,
 	};
 
 	debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}