Use vector pair instructions on Power10.

Author: TheRealMDoerr

src/hotspot/cpu/ppc/assembler_ppc.hpp

@@ -538,6 +538,8 @@ class Assembler : public AbstractAssembler {
     LXVL_OPCODE    = (31u << OPCODE_SHIFT |  269u << 1),
     STXV_OPCODE    = (61u << OPCODE_SHIFT |    5u     ),
     STXVL_OPCODE   = (31u << OPCODE_SHIFT |  397u << 1),
+    LXVP_OPCODE    = ( 6u << OPCODE_SHIFT             ),
+    STXVP_OPCODE   = ( 6u << OPCODE_SHIFT |    1u     ),
     LXVD2X_OPCODE  = (31u << OPCODE_SHIFT |  844u << 1),
     STXVD2X_OPCODE = (31u << OPCODE_SHIFT |  972u << 1),
     MTVSRD_OPCODE  = (31u << OPCODE_SHIFT |  179u << 1),
@@ -1243,6 +1245,11 @@ class Assembler : public AbstractAssembler {
   static int vsdm(      int         x)  { return  opp_u_field(x,            23, 22); }
   static int vsrs_dq(   int         x)  { return  opp_u_field(x & 0x1F,     10,  6) | opp_u_field((x & 0x20) >> 5, 28, 28); }
   static int vsrt_dq(   int         x)  { return  vsrs_dq(x); }
+  static int vsrtp(     int         x)  {
+    assert((x & 1) == 0, "must be even");
+    return opp_u_field((x & 0x1F) >> 1, 9, 6) | opp_u_field((x & 0x20) >> 5, 10, 10);
+  }
+  static int vsrsp(     int         x)  { return  vsrtp(x); }
 
   static int vsra(   VectorSRegister r)  { return  vsra(r->encoding());}
   static int vsrb(   VectorSRegister r)  { return  vsrb(r->encoding());}
@@ -1251,6 +1258,8 @@ class Assembler : public AbstractAssembler {
   static int vsrt(   VectorSRegister r)  { return  vsrt(r->encoding());}
   static int vsrs_dq(VectorSRegister r)  { return  vsrs_dq(r->encoding());}
   static int vsrt_dq(VectorSRegister r)  { return  vsrt_dq(r->encoding());}
+  static int vsrtp(  VectorSRegister r)  { return  vsrtp(r->encoding());}
+  static int vsrsp(  VectorSRegister r)  { return  vsrsp(r->encoding());}
 
   static int vsplt_uim( int        x)  { return  opp_u_field(x,             15, 12); } // for vsplt* instructions
   static int vsplti_sim(int        x)  { return  opp_u_field(x,             15, 11); } // for vsplti* instructions
@@ -2358,6 +2367,8 @@ class Assembler : public AbstractAssembler {
   // Vector-Scalar (VSX) instructions.
   inline void lxv(      VectorSRegister d, int si16, Register a);
   inline void stxv(     VectorSRegister d, int si16, Register a);
+  inline void lxvp(     VectorSRegister d, int si16, Register a);
+  inline void stxvp(    VectorSRegister d, int si16, Register a);
   inline void lxvl(     VectorSRegister d, Register a, Register b);
   inline void stxvl(    VectorSRegister d, Register a, Register b);
   inline void lxvd2x(   VectorSRegister d, Register a);

src/hotspot/cpu/ppc/assembler_ppc.inline.hpp

@@ -862,8 +862,10 @@ inline void Assembler::lvsl(  VectorRegister d, Register s1, Register s2) { emit
 inline void Assembler::lvsr(  VectorRegister d, Register s1, Register s2) { emit_int32( LVSR_OPCODE   | vrt(d) | ra0mem(s1) | rb(s2)); }
 
 // Vector-Scalar (VSX) instructions.
-inline void Assembler::lxv(     VectorSRegister d, int ui16, Register a)     { assert(is_aligned(ui16, 16), "displacement must be a multiple of 16"); emit_int32( LXV_OPCODE  | vsrt_dq(d) | ra0mem(a) | uimm(ui16, 16)); }
-inline void Assembler::stxv(    VectorSRegister d, int ui16, Register a)     { assert(is_aligned(ui16, 16), "displacement must be a multiple of 16"); emit_int32( STXV_OPCODE  | vsrs_dq(d) | ra0mem(a) | uimm(ui16, 16)); }
+inline void Assembler::lxv(     VectorSRegister d, int si16, Register a)     { assert(is_aligned(si16, 16), "displacement must be a multiple of 16"); emit_int32( LXV_OPCODE   | vsrt_dq(d) | ra0mem(a) | simm(si16, 16)); }
+inline void Assembler::stxv(    VectorSRegister d, int si16, Register a)     { assert(is_aligned(si16, 16), "displacement must be a multiple of 16"); emit_int32( STXV_OPCODE  | vsrs_dq(d) | ra0mem(a) | simm(si16, 16)); }
+inline void Assembler::lxvp(    VectorSRegister d, int si16, Register a)     { assert(is_aligned(si16, 16), "displacement must be a multiple of 16"); emit_int32( LXVP_OPCODE  | vsrtp(d)   | ra0mem(a) | simm(si16, 16)); }
+inline void Assembler::stxvp(   VectorSRegister d, int si16, Register a)     { assert(is_aligned(si16, 16), "displacement must be a multiple of 16"); emit_int32( STXVP_OPCODE | vsrsp(d)   | ra0mem(a) | simm(si16, 16)); }
 inline void Assembler::lxvl(    VectorSRegister d, Register s1, Register b)  { emit_int32( LXVL_OPCODE    | vsrt(d) | ra0mem(s1) | rb(b)); }
 inline void Assembler::stxvl(   VectorSRegister d, Register s1, Register b)  { emit_int32( STXVL_OPCODE   | vsrt(d) | ra0mem(s1) | rb(b)); }
 inline void Assembler::lxvd2x(  VectorSRegister d, Register s1)              { emit_int32( LXVD2X_OPCODE  | vsrt(d) | ra(0) | rb(s1)); }

src/hotspot/cpu/ppc/macroAssembler_ppc.cpp

@@ -774,10 +774,6 @@ void MacroAssembler::clobber_carg_stack_slots(Register tmp) {
   }
 }
 
-// Uses ordering which corresponds to ABI:
-//    _savegpr0_14:  std  r14,-144(r1)
-//    _savegpr0_15:  std  r15,-136(r1)
-//    _savegpr0_16:  std  r16,-128(r1)
 void MacroAssembler::save_nonvolatile_registers(Register dst, int offset, bool include_fp_regs, bool include_vector_regs) {
   for (int i = 14; i < 32; i++) {
     std(as_Register(i), offset, dst);
@@ -793,19 +789,22 @@ void MacroAssembler::save_nonvolatile_registers(Register dst, int offset, bool i
 
   if (include_vector_regs) {
     assert(is_aligned(offset, StackAlignmentInBytes), "should be");
-    Register spill_addr = R0;
-    for (int i = 20; i < 32; i++) {
-      addi(spill_addr, dst, offset);
-      stxvd2x(as_VectorRegister(i)->to_vsr(), spill_addr);
-      offset += 16;
+    if (PowerArchitecturePPC64 >= 10) {
+      for (int i = 20; i < 32; i += 2) {
+        stxvp(as_VectorRegister(i)->to_vsr(), offset, dst);
+        offset += 32;
+      }
+    } else {
+      Register spill_addr = R0;
+      for (int i = 20; i < 32; i++) {
+        addi(spill_addr, dst, offset);
+        stxvd2x(as_VectorRegister(i)->to_vsr(), spill_addr);
+        offset += 16;
+      }
     }
   }
 }
 
-// Uses ordering which corresponds to ABI:
-//    _restgpr0_14:  ld   r14,-144(r1)
-//    _restgpr0_15:  ld   r15,-136(r1)
-//    _restgpr0_16:  ld   r16,-128(r1)
 void MacroAssembler::restore_nonvolatile_registers(Register src, int offset, bool include_fp_regs, bool include_vector_regs) {
   for (int i = 14; i < 32; i++) {
     ld(as_Register(i), offset, src);
@@ -821,11 +820,18 @@ void MacroAssembler::restore_nonvolatile_registers(Register src, int offset, boo
 
   if (include_vector_regs) {
     assert(is_aligned(offset, StackAlignmentInBytes), "should be");
-    Register spill_addr = R0;
-    for (int i = 20; i < 32; i++) {
-      addi(spill_addr, src, offset);
-      lxvd2x(as_VectorRegister(i)->to_vsr(), spill_addr);
-      offset += 16;
+    if (PowerArchitecturePPC64 >= 10) {
+      for (int i = 20; i < 32; i += 2) {
+        lxvp(as_VectorRegister(i)->to_vsr(), offset, src);
+        offset += 32;
+      }
+    } else {
+      Register spill_addr = R0;
+      for (int i = 20; i < 32; i++) {
+        addi(spill_addr, src, offset);
+        lxvd2x(as_VectorRegister(i)->to_vsr(), spill_addr);
+        offset += 16;
+      }
     }
   }
 }