Use better spill instructions on Power9/10.

Author: TheRealMDoerr

src/hotspot/cpu/ppc/gc/shared/barrierSetAssembler_ppc.cpp

@@ -340,12 +340,21 @@ int SaveLiveRegisters::iterate_over_register_mask(IterationAction action, int of
         reg_save_index += 2;
 
         Register spill_addr = R0;
+        int spill_offset = offset - reg_save_index * BytesPerWord;
         if (action == ACTION_SAVE) {
-          _masm->addi(spill_addr, R1_SP, offset - reg_save_index * BytesPerWord);
-          _masm->stxvd2x(vs_reg, spill_addr);
+          if (PowerArchitecturePPC64 >= 9) {
+            _masm->stxv(vs_reg, spill_offset, R1_SP);
+          } else {
+            _masm->addi(spill_addr, R1_SP, spill_offset);
+            _masm->stxvd2x(vs_reg, spill_addr);
+          }
         } else if (action == ACTION_RESTORE) {
-          _masm->addi(spill_addr, R1_SP, offset - reg_save_index * BytesPerWord);
-          _masm->lxvd2x(vs_reg, spill_addr);
+          if (PowerArchitecturePPC64 >= 9) {
+            _masm->lxv(vs_reg, spill_offset, R1_SP);
+          } else {
+            _masm->addi(spill_addr, R1_SP, spill_offset);
+            _masm->lxvd2x(vs_reg, spill_addr);
+          }
         } else {
           assert(action == ACTION_COUNT_ONLY, "Sanity");
         }

src/hotspot/cpu/ppc/ppc.ad

@@ -1818,21 +1818,35 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
     else if (src_lo_rc == rc_vs && dst_lo_rc == rc_stack) {
       VectorSRegister Rsrc = as_VectorSRegister(Matcher::_regEncode[src_lo]);
       int dst_offset = ra_->reg2offset(dst_lo);
-      if (masm) {
-        __ addi(R0, R1_SP, dst_offset);
-        __ stxvd2x(Rsrc, R0);
+      if (PowerArchitecturePPC64 >= 9) {
+        if (masm) {
+          __ stxv(Rsrc, dst_offset, R1_SP);
+        }
+        size += 4;
+      } else {
+        if (masm) {
+          __ addi(R0, R1_SP, dst_offset);
+          __ stxvd2x(Rsrc, R0);
+        }
+        size += 8;
       }
-      size += 8;
     }
     // Memory->VectorSRegister Spill.
     else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vs) {
       VectorSRegister Rdst = as_VectorSRegister(Matcher::_regEncode[dst_lo]);
       int src_offset = ra_->reg2offset(src_lo);
-      if (masm) {
-        __ addi(R0, R1_SP, src_offset);
-        __ lxvd2x(Rdst, R0);
+      if (PowerArchitecturePPC64 >= 9) {
+        if (masm) {
+          __ lxv(Rdst, src_offset, R1_SP);
+        }
+        size += 4;
+      } else {
+        if (masm) {
+          __ addi(R0, R1_SP, src_offset);
+          __ lxvd2x(Rdst, R0);
+        }
+        size += 8;
       }
-      size += 8;
     }
     // VectorSRegister->VectorSRegister.
     else if (src_lo_rc == rc_vs && dst_lo_rc == rc_vs) {

src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp

@@ -354,18 +354,34 @@ OopMap* RegisterSaver::push_frame_reg_args_and_save_live_registers(MacroAssemble
     offset += reg_size;
   }
 
-  for (int i = 0; i < vsregstosave_num; i++) {
-    int reg_num  = RegisterSaver_LiveVSRegs[i].reg_num;
-    int reg_type = RegisterSaver_LiveVSRegs[i].reg_type;
+  if (PowerArchitecturePPC64 >= 10) {
+    for (int i = 0; i < vsregstosave_num; i += 2) {
+      int reg_num  = RegisterSaver_LiveVSRegs[i].reg_num;
+      assert(RegisterSaver_LiveVSRegs[i + 1].reg_num == reg_num + 1, "or use other instructions!");
+
+      __ stxvp(as_VectorSRegister(reg_num), offset, R1_SP);
+
+      if (generate_oop_map) {
+        map->set_callee_saved(VMRegImpl::stack2reg(offset >> 2),
+                              RegisterSaver_LiveVSRegs[i].vmreg);
+        map->set_callee_saved(VMRegImpl::stack2reg((offset + vs_reg_size) >> 2),
+                              RegisterSaver_LiveVSRegs[i + 1].vmreg);
+      }
+      offset += (2 * vs_reg_size);
+    }
+  } else {
+    for (int i = 0; i < vsregstosave_num; i++) {
+      int reg_num  = RegisterSaver_LiveVSRegs[i].reg_num;
 
-    __ li(R30, offset);
-    __ stxvd2x(as_VectorSRegister(reg_num), R30, R1_SP);
+      __ li(R31, offset);
+      __ stxvd2x(as_VectorSRegister(reg_num), R31, R1_SP);
 
-    if (generate_oop_map) {
-      map->set_callee_saved(VMRegImpl::stack2reg(offset>>2),
-                            RegisterSaver_LiveVSRegs[i].vmreg);
+      if (generate_oop_map) {
+        map->set_callee_saved(VMRegImpl::stack2reg(offset >> 2),
+                              RegisterSaver_LiveVSRegs[i].vmreg);
+      }
+      offset += vs_reg_size;
     }
-    offset += vs_reg_size;
   }
 
   assert(offset == frame_size_in_bytes, "consistency check");
@@ -428,14 +444,24 @@ void RegisterSaver::restore_live_registers_and_pop_frame(MacroAssembler* masm,
     offset += reg_size;
   }
 
-  for (int i = 0; i < vsregstosave_num; i++) {
-    int reg_num  = RegisterSaver_LiveVSRegs[i].reg_num;
-    int reg_type = RegisterSaver_LiveVSRegs[i].reg_type;
+  if (PowerArchitecturePPC64 >= 10) {
+    for (int i = 0; i < vsregstosave_num; i += 2) {
+      int reg_num  = RegisterSaver_LiveVSRegs[i].reg_num;
+      assert(RegisterSaver_LiveVSRegs[i + 1].reg_num == reg_num + 1, "or use other instructions!");
 
-    __ li(R31, offset);
-    __ lxvd2x(as_VectorSRegister(reg_num), R31, R1_SP);
+      __ lxvp(as_VectorSRegister(reg_num), offset, R1_SP);
 
-    offset += vs_reg_size;
+      offset += (2 * vs_reg_size);
+    }
+  } else {
+    for (int i = 0; i < vsregstosave_num; i++) {
+      int reg_num  = RegisterSaver_LiveVSRegs[i].reg_num;
+
+      __ li(R31, offset);
+      __ lxvd2x(as_VectorSRegister(reg_num), R31, R1_SP);
+
+      offset += vs_reg_size;
+    }
   }
 
   assert(offset == frame_size_in_bytes, "consistency check");