Fix PPC64

Author: TheRealMDoerr

src/hotspot/cpu/ppc/gc/shared/barrierSetAssembler_ppc.cpp

@@ -183,22 +183,23 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm, Register t
   BarrierSetNMethod* bs_nm = BarrierSet::barrier_set()->barrier_set_nmethod();
   assert_different_registers(tmp, R0);
 
-  __ block_comment("nmethod_entry_barrier (nmethod_entry_barrier) {");
+  __ align(8); // must align the following block which requires atomic updates
 
-  // Load stub address using toc (fixed instruction size, unlike load_const_optimized)
-  __ calculate_address_from_global_toc(tmp, StubRoutines::method_entry_barrier(),
-                                       true, true, false); // 2 instructions
-  __ mtctr(tmp);
+  __ block_comment("nmethod_entry_barrier (nmethod_entry_barrier) {");
 
   // This is a compound instruction. Patching support is provided by NativeMovRegMem.
   // Actual patching is done in (platform-specific part of) BarrierSetNMethod.
-  __ align(8); // align for atomic update
   __ load_const32(tmp, 0 /* Value is patched */); // 2 instructions
 
   // Low order half of 64 bit value is currently used.
   __ ld(R0, in_bytes(bs_nm->thread_disarmed_guard_value_offset()), R16_thread);
   __ cmpw(CR0, R0, tmp);
 
+  // Load stub address using toc (fixed instruction size, unlike load_const_optimized)
+  __ calculate_address_from_global_toc(tmp, StubRoutines::method_entry_barrier(),
+                                       true, true, false); // 2 instructions
+  __ mtctr(tmp);
+
   __ bnectrl(CR0);
 
   // Oops may have been changed. Make those updates observable.

src/hotspot/cpu/ppc/gc/shared/barrierSetNMethod_ppc.cpp

@@ -38,7 +38,7 @@ class NativeNMethodBarrier: public NativeInstruction {
 
   NativeMovRegMem* get_patchable_instruction_handle() const {
     // Endianness is handled by NativeMovRegMem
-    return reinterpret_cast<NativeMovRegMem*>(get_barrier_start_address() + 3 * 4);
+    return reinterpret_cast<NativeMovRegMem*>(get_barrier_start_address());
   }
 
 public:
@@ -95,12 +95,6 @@ class NativeNMethodBarrier: public NativeInstruction {
 
     uint* current_instruction = reinterpret_cast<uint*>(get_barrier_start_address());
 
-    // calculate_address_from_global_toc (compound instruction)
-    verify_op_code_manually(current_instruction, MacroAssembler::is_addis(*current_instruction));
-    verify_op_code_manually(current_instruction, MacroAssembler::is_addi(*current_instruction));
-
-    verify_op_code_manually(current_instruction, MacroAssembler::is_mtctr(*current_instruction));
-
     get_patchable_instruction_handle()->verify();
     current_instruction += 2;
 
@@ -109,6 +103,12 @@ class NativeNMethodBarrier: public NativeInstruction {
     // cmpw (mnemonic)
     verify_op_code(current_instruction, Assembler::CMP_OPCODE);
 
+    // calculate_address_from_global_toc (compound instruction)
+    verify_op_code_manually(current_instruction, MacroAssembler::is_addis(*current_instruction));
+    verify_op_code_manually(current_instruction, MacroAssembler::is_addi(*current_instruction));
+
+    verify_op_code_manually(current_instruction, MacroAssembler::is_mtctr(*current_instruction));
+
     // bnectrl (mnemonic) (weak check; not checking the exact type)
     verify_op_code(current_instruction, Assembler::BCCTR_OPCODE);