8359435: AArch64: add support for SB instruction to MacroAssembler::spin_wait

Reviewed-by: shade, aph

Author: Evgeny Astigeevich

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@@ -1136,6 +1136,10 @@ class Assembler : public AbstractAssembler {
     system(0b00, 0b011, 0b00011, SY, 0b110);
   }
 
+  void sb() {
+    system(0b00, 0b011, 0b00011, 0b0000, 0b111);
+  }
+
   void sys(int op1, int CRn, int CRm, int op2,
            Register rt = as_Register(0b11111)) {
     system(0b01, op1, CRn, CRm, op2, rt);

src/hotspot/cpu/aarch64/globals_aarch64.hpp

@@ -117,7 +117,7 @@ define_pd_global(intx, InlineSmallCode,          1000);
   product(ccstr, OnSpinWaitInst, "yield", DIAGNOSTIC,                   \
           "The instruction to use to implement "                        \
           "java.lang.Thread.onSpinWait()."                              \
-          "Options: none, nop, isb, yield.")                            \
+          "Options: none, nop, isb, yield, sb.")                        \
   product(uint, OnSpinWaitInstCount, 1, DIAGNOSTIC,                     \
           "The number of OnSpinWaitInst instructions to generate."      \
           "It cannot be used with OnSpinWaitInst=none.")                \

src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp

@@ -6814,6 +6814,9 @@ void MacroAssembler::spin_wait() {
       case SpinWait::YIELD:
         yield();
         break;
+      case SpinWait::SB:
+        sb();
+        break;
       default:
         ShouldNotReachHere();
     }

src/hotspot/cpu/aarch64/spin_wait_aarch64.hpp

@@ -31,7 +31,8 @@ class SpinWait {
     NONE = -1,
     NOP,
     ISB,
-    YIELD
+    YIELD,
+    SB
   };
 
 private:

src/hotspot/cpu/aarch64/vm_version_aarch64.cpp

@@ -57,8 +57,13 @@ static SpinWait get_spin_wait_desc() {
     return SpinWait(SpinWait::ISB, OnSpinWaitInstCount);
   } else if (strcmp(OnSpinWaitInst, "yield") == 0) {
     return SpinWait(SpinWait::YIELD, OnSpinWaitInstCount);
+  } else if (strcmp(OnSpinWaitInst, "sb") == 0) {
+    if (!VM_Version::supports_sb()) {
+      vm_exit_during_initialization("OnSpinWaitInst is SB but current CPU does not support SB instruction");
+    }
+    return SpinWait(SpinWait::SB, OnSpinWaitInstCount);
   } else if (strcmp(OnSpinWaitInst, "none") != 0) {
-    vm_exit_during_initialization("The options for OnSpinWaitInst are nop, isb, yield, and none", OnSpinWaitInst);
+    vm_exit_during_initialization("The options for OnSpinWaitInst are nop, isb, yield, sb, and none", OnSpinWaitInst);
   }
 
   if (!FLAG_IS_DEFAULT(OnSpinWaitInstCount) && OnSpinWaitInstCount > 0) {

src/hotspot/cpu/aarch64/vm_version_aarch64.hpp

@@ -131,6 +131,7 @@ enum Ampere_CPU_Model {
     decl(SHA3,          sha3,          17)    \
     decl(SHA512,        sha512,        21)    \
     decl(SVE,           sve,           22)    \
+    decl(SB,            sb,            29)    \
     decl(PACA,          paca,          30)    \
     /* flags above must follow Linux HWCAP */ \
     decl(SVEBITPERM,    svebitperm,    27)    \

src/hotspot/os_cpu/bsd_aarch64/vm_version_bsd_aarch64.cpp

@@ -92,6 +92,9 @@ void VM_Version::get_os_cpu_info() {
       cpu_has("hw.optional.armv8_2_sha3")) {
     _features |= CPU_SHA3;
   }
+  if (cpu_has("hw.optional.arm.FEAT_SB")) {
+    _features |= CPU_SB;
+  }
 
   int cache_line_size;
   int hw_conf_cache_line[] = { CTL_HW, HW_CACHELINE };

src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp

@@ -71,6 +71,10 @@
 #define HWCAP_SVE (1 << 22)
 #endif
 
+#ifndef HWCAP_SB
+#define HWCAP_SB (1 << 29)
+#endif
+
 #ifndef HWCAP_PACA
 #define HWCAP_PACA (1 << 30)
 #endif
@@ -143,6 +147,7 @@ void VM_Version::get_os_cpu_info() {
       HWCAP_SHA3    |
       HWCAP_SHA512  |
       HWCAP_SVE     |
+      HWCAP_SB      |
       HWCAP_PACA    |
       HWCAP_FPHP    |
       HWCAP_ASIMDHP);

src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/aarch64/AArch64.java

@@ -179,6 +179,7 @@ public enum CPUFeature implements CPUFeatureName {
         SHA3,
         SHA512,
         SVE,
+        SB,
         PACA,
         SVEBITPERM,
         SVE2,

test/hotspot/gtest/aarch64/aarch64-asmtest.py

@@ -1605,7 +1605,7 @@ def generate(kind, names):
 generate (Op, ["nop", "yield", "wfe", "sev", "sevl",
                "autia1716", "autiasp", "autiaz", "autib1716", "autibsp", "autibz",
                "pacia1716", "paciasp", "paciaz", "pacib1716", "pacibsp", "pacibz",
-               "eret", "drps", "isb",])
+               "eret", "drps", "isb", "sb",])
 
 # Ensure the "i" is not stripped off the end of the instruction
 generate (PostfixExceptionOp, ["wfi", "xpaclri"])