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Fix pylint issues
1 parent db2228a commit 7f1b14d

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+8
-14
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1 file changed

+8
-14
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pystiebeleltron/pystiebeleltron.py

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -208,20 +208,14 @@ def update(self):
208208
ret = False
209209
print("Modbus read failed")
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else:
211-
for k in self._block_1_input_regs:
212-
self._block_1_input_regs[k]['value'] = \
213-
block_1_result_input[
214-
self._block_1_input_regs[k]['addr'] - B1_START_ADDR]
215-
216-
for k in self._block_2_holding_regs:
217-
self._block_2_holding_regs[k]['value'] = \
218-
block_2_result_holding[
219-
self._block_2_holding_regs[k]['addr'] - B2_START_ADDR]
220-
221-
for k in self._block_3_input_regs:
222-
self._block_3_input_regs[k]['value'] = \
223-
block_3_result_input[
224-
self._block_3_input_regs[k]['addr'] - B3_START_ADDR]
211+
for v in self._block_1_input_regs.values():
212+
v['value'] = block_1_result_input[v['addr'] - B1_START_ADDR]
213+
214+
for v in self._block_2_holding_regs.values():
215+
v['value'] = block_2_result_holding[v['addr'] - B2_START_ADDR]
216+
217+
for v in self._block_3_input_regs.values():
218+
v['value'] = block_3_result_input[v['addr'] - B3_START_ADDR]
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226220
return ret
227221

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