Update README.md

- GitHub doesn't keep vertical-align styling on master page (after finished previewing), so triplet of SVGs is a workaround for that and it's also a workaround because SVG external references don't work

Author: TimRudy

README.md

@@ -1,6 +1,4 @@
-<img src="images/proj_icon_a.svg" title="IceChips" align="right" vertical-align="top" width="6.124%">
-<img src="images/proj_icon_b.svg" title="IceChips" align="right" vertical-align="top" width="3.484%">
-<img src="images/proj_icon_c.svg" title="IceChips" align="right" vertical-align="top" width="3.453%">
+<img src="images/proj_icon_triplet.svg" title="IceChips" align="right" width="13%">
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 <br />
 
@@ -59,7 +57,7 @@ It's done with entirely open source tools (the IceStorm toolchain); and most of
 
 A test bench accompanies every device (74xx-tb.v file with 74xx.v file) and the tests are run automatically. You can click on the "tests" badge below the main title at top of page to see the logged results.
 
-Tests are a definitive feature of the library. Test coverage will continue at the highest standard as the library expands going forward.
+Tests are a definitive feature of the library. Count on full test coverage as the library expands going forward.
 
 You have to "trust but verify" when scaling up a hardware design from lower-layer components.
 
@@ -82,15 +80,15 @@ Self-checking: Each test gives a Pass/Fail result. It does this by using an "ass
 
 #### Validation Contract
 
-IceChips is actually built around validation end-to-end. The code files are generated by script, from a template, and all the working parts come together to ensure the Verilog is validated reliably and completely.
+IceChips is actually built around validation end-to-end. The code files are generated by script, from a template, for reliably validated code and .ice components.
 
-Here's an overview, with a visual showing the structure of the code files:
+Here's an overview, with a visual that shows the structure of the code files:
 
-&ensp;&ensp;[Validation scheme and contract](docs/validation-scheme.md) for the Verilog code files and the .ice components
+&ensp;&ensp;[Validation scheme and contract](docs/validation-scheme.md) for the Verilog code
 
-&ensp;&ensp;[Direct to contract](docs/validation-scheme.md#the-contract)
+&ensp;&ensp;Direct to [the contract](docs/validation-scheme.md#the-contract)
 
-Some nerdy stuff is included, by intention, such as [guidelines around test benches](docs/validation-scheme.md#what-is-a-good-test-bench) for open source purposes and community contribution.
+Some nerdy stuff is included, such as [guidelines around test benches](docs/validation-scheme.md#what-is-a-good-test-bench) for open source purposes and community contribution.
 
 #### Running the tests on your machine