Add configurable mtime divider

Author: MichaelBell

docs/info.md

@@ -51,6 +51,7 @@ See also [debug docs](debug.md)
 
 | Register | Address | Description |
 | -------- | ------- | ----------- |
+| MTIME_DIVIDER | 0x800002C | MTIME counts at clock / (MTIME_DIVIDER + 1).  Bits 0 and 1 are fixed at 1, so multiples of 4MHz are supported. |
 | MTIME    | 0xFFFFF00 (RW) | Get/set the 1MHz time count |
 | MTIMECMP | 0xFFFFF04 (RW) | Get/set the time to trigger the timer interrupt |
 

src/project.v

@@ -21,6 +21,7 @@ module tt_um_tt_tinyQV #(parameter CLOCK_MHZ=64) (
     localparam PERI_GPIO_OUT_SEL = 4'h3;
     localparam PERI_DEBUG_UART = 4'h6;
     localparam PERI_DEBUG_UART_STATUS = 4'h7;
+    localparam PERI_TIME_LIMIT = 4'hB;
     localparam PERI_DEBUG = 4'hC;
     localparam PERI_USER = 4'hF;
 
@@ -85,6 +86,7 @@ module tt_um_tt_tinyQV #(parameter CLOCK_MHZ=64) (
     wire debug_uart_tx_start = write_n != 2'b11 && connect_peripheral == PERI_DEBUG_UART;
 
     // Time
+    reg [6:2] time_limit;
     wire time_pulse;
 
     // Peripherals interface
@@ -193,6 +195,7 @@ module tt_um_tt_tinyQV #(parameter CLOCK_MHZ=64) (
         case (connect_peripheral)
             PERI_GPIO_OUT_SEL:data_from_read = {24'h0, gpio_out_sel, 6'h0};
             PERI_DEBUG_UART_STATUS: data_from_read = {31'h0, debug_uart_tx_busy};
+            PERI_TIME_LIMIT:  data_from_read = {25'h0, time_limit, 2'b11};
             PERI_USER:        data_from_read = peri_data_out;
             default:          data_from_read = 32'hFFFF_FFFF;
         endcase
@@ -204,9 +207,11 @@ module tt_um_tt_tinyQV #(parameter CLOCK_MHZ=64) (
     always @(posedge clk) begin
         if (!rst_reg_n) begin
             gpio_out_sel <= {!ui_in[0], 1'b0};
+            time_limit <= (CLOCK_MHZ / 4 - 1);
         end
         if (write_n != 2'b11) begin
             if (connect_peripheral == PERI_GPIO_OUT_SEL) gpio_out_sel <= data_to_write[7:6];
+            if (connect_peripheral == PERI_TIME_LIMIT) time_limit <= data_to_write[6:2];
         end
     end
 
@@ -219,29 +224,17 @@ module tt_um_tt_tinyQV #(parameter CLOCK_MHZ=64) (
         .uart_tx_busy(debug_uart_tx_busy) 
     );
 
-    reg [5:0] time_count;
-
-    generate
-        if (CLOCK_MHZ == 64) begin
-            always @(posedge clk) begin
-                if (!rst_reg_n) begin
-                    time_count <= 0;
-                end else begin
-                    time_count <= time_count + 1;
-                end
-            end
+    reg [6:0] time_count;
+
+    always @(posedge clk) begin
+        if (!rst_reg_n) begin
+            time_count <= 0;
         end else begin
-            always @(posedge clk) begin
-                if (!rst_reg_n) begin
-                    time_count <= 0;
-                end else begin
-                    if (time_count == (CLOCK_MHZ - 1)) time_count <= 0;
-                    else time_count <= time_count + 1;
-                end
-            end
+            if (time_pulse) time_count <= 0;
+            else time_count <= time_count + 1;
         end
-    endgenerate
-    assign time_pulse = time_count == (CLOCK_MHZ - 1);
+    end
+    assign time_pulse = time_count == {time_limit, 2'b11};
 
     // Debug
     always @(posedge clk) begin

test/test.py

@@ -176,6 +176,56 @@ async def test_timer(dut):
     await send_instr(dut, InstructionCSRRS(a0, x0, csrnames.mcause).encode())
     assert await read_reg(dut, a0) == 0x80000007
 
+@cocotb.test()
+async def test_time_limit(dut):
+    dut._log.info("Start")
+
+    clock = Clock(dut.clk, 15.624, units="ns")
+    cocotb.start_soon(clock.start())
+
+    # Reset
+    await reset(dut)
+
+    # Should start reading flash after 1 cycle
+    await ClockCycles(dut.clk, 1)
+    await start_read(dut, 0)
+
+    # Read time limit
+    await send_instr(dut, InstructionLW(x1, tp, 0x2c).encode())
+    assert await read_reg(dut, x1) == 0x3f
+
+    # Halve the divider, time should now advance twice as fast
+    await send_instr(dut, InstructionADDI(x1, x0, 0x1f).encode())
+    await send_instr(dut, InstructionSW(tp, x1, 0x2c).encode())
+
+    # Read time
+    await send_instr(dut, InstructionLW(x1, x0, -0x100).encode())
+    start_time = await read_reg(dut, x1)
+
+    await start_nops(dut)
+    await Timer(5, "us")
+    await stop_nops()
+
+    # Read time
+    await send_instr(dut, InstructionLW(x1, x0, -0x100).encode())
+    assert start_time+10 <= await read_reg(dut, x1) <= start_time+12
+
+    # Set divider to 96, time should advance more slowly
+    await send_instr(dut, InstructionADDI(x1, x0, 0x5f).encode())
+    await send_instr(dut, InstructionSW(tp, x1, 0x2c).encode())
+
+    # Read time
+    await send_instr(dut, InstructionLW(x1, x0, -0x100).encode())
+    start_time = await read_reg(dut, x1)
+
+    await start_nops(dut)
+    await Timer(9, "us")
+    await stop_nops()
+
+    # Read time
+    await send_instr(dut, InstructionLW(x1, x0, -0x100).encode())
+    assert start_time+6 <= await read_reg(dut, x1) <= start_time+8
+
 @cocotb.test()
 async def test_csr(dut):
     dut._log.info("Start")