Drop txt_os_mle_data::boot_params_addr

Signed-off-by: Sergii Dmytruk <[email protected]>

Author: SergiiDmytruk

xen/arch/x86/boot/slaunch_early.c

@@ -68,7 +68,9 @@ void __stdcall slaunch_early_tests(uint32_t load_base_addr,
 {
     void *txt_heap;
     struct txt_os_mle_data *os_mle;
+    struct slr_table *slrt;
     struct txt_os_sinit_data *os_sinit;
+    struct slr_entry_intel_info *intel_info;
     uint32_t size = tgt_end_addr - tgt_base_addr;
 
     if ( !is_intel_cpu() )
@@ -77,7 +79,6 @@ void __stdcall slaunch_early_tests(uint32_t load_base_addr,
          * Not an Intel CPU. Currently the only other option is AMD with SKINIT
          * and secure-kernel-loader (SKL).
          */
-        struct slr_table *slrt;
         struct slr_entry_amd_info *amd_info;
         const struct skinit_sl_header *sl_header = (void *)slaunch_param;
 
@@ -104,9 +105,18 @@ void __stdcall slaunch_early_tests(uint32_t load_base_addr,
     os_mle = txt_os_mle_data_start(txt_heap);
     os_sinit = txt_os_sinit_data_start(txt_heap);
 
-    txt_verify_pmr_ranges(os_mle, os_sinit, load_base_addr, tgt_base_addr,
-                          size);
-
-    result->mbi_pa = os_mle->boot_params_addr;
     result->slrt_pa = os_mle->slrt;
+    result->mbi_pa = 0;
+
+    slrt = (struct slr_table *)result->slrt_pa;
+
+    intel_info = (struct slr_entry_intel_info *)
+               slr_next_entry_by_tag (slrt, NULL, SLR_ENTRY_INTEL_INFO);
+    if ( intel_info == NULL || intel_info->hdr.size != sizeof(*intel_info) )
+        return;
+
+    result->mbi_pa = intel_info->boot_params_base;
+
+    txt_verify_pmr_ranges(os_mle, os_sinit, intel_info,
+                          load_base_addr, tgt_base_addr, size);
 }

xen/arch/x86/efi/efi-boot.h

@@ -258,7 +258,7 @@ void __init noreturn start_xen_from_efi(void)
             struct txt_os_sinit_data *os_sinit =
                 txt_os_sinit_data_start(txt_heap);
 
-            txt_verify_pmr_ranges(os_mle, os_sinit, xen_phys_start,
+            txt_verify_pmr_ranges(os_mle, os_sinit, intel_info, xen_phys_start,
                                   __XEN_VIRT_START, image_size);
         }
     }

xen/arch/x86/include/asm/intel_txt.h

@@ -87,6 +87,7 @@
 extern char txt_ap_entry[];
 extern uint32_t trampoline_gdt[];
 
+#include <xen/slr_table.h>
 #include <xen/types.h>
 
 /* We need to differentiate between pre- and post paging enabled. */
@@ -130,7 +131,6 @@ static inline void txt_reset(uint32_t error)
 struct txt_os_mle_data {
     uint32_t version;
     uint32_t reserved;
-    uint64_t boot_params_addr;
     uint64_t slrt;
     uint64_t txt_info;
     uint32_t ap_wake_block;
@@ -348,6 +348,7 @@ static inline void *txt_init(void)
 
 static inline void txt_verify_pmr_ranges(struct txt_os_mle_data *os_mle,
                                          struct txt_os_sinit_data *os_sinit,
+                                         struct slr_entry_intel_info *info,
                                          uint32_t load_base_addr,
                                          uint64_t tgt_base_addr,
                                          uint32_t xen_size)
@@ -393,8 +394,8 @@ static inline void txt_verify_pmr_ranges(struct txt_os_mle_data *os_mle,
         txt_reset(SLAUNCH_ERROR_LO_PMR_MLE);
 
     /* Check if MBI is covered by PMR. MBI starts with 'uint32_t total_size'. */
-    if ( !is_in_pmr(os_sinit, os_mle->boot_params_addr,
-                    *(uint32_t *)(uintptr_t)os_mle->boot_params_addr,
+    if ( !is_in_pmr(os_sinit, info->boot_params_base,
+                    *(uint32_t *)(uintptr_t)info->boot_params_base,
                     check_high_pmr) )
         txt_reset(SLAUNCH_ERROR_BUFFER_BEYOND_PMR);